73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_CM_IPI_H__
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#define __MTK_CM_IPI_H__
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enum {
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IPI_CM_MGR_SCMI_SET = 0x00000000,
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IPI_CM_MGR_SCMI_GET = 0x10000000,
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};
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enum {
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IPI_CM_MGR_INIT,
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IPI_CM_MGR_ENABLE,
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IPI_CM_MGR_OPP_ENABLE,
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IPI_CM_MGR_SSPM_ENABLE,
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IPI_CM_MGR_BLANK,
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IPI_CM_MGR_DISABLE_FB,
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IPI_CM_MGR_DRAM_TYPE,
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IPI_CM_MGR_CPU_POWER_RATIO_UP,
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IPI_CM_MGR_CPU_POWER_RATIO_DOWN,
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IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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IPI_CM_MGR_VCORE_POWER_RATIO_DOWN,
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IPI_CM_MGR_DEBOUNCE_UP,
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IPI_CM_MGR_DEBOUNCE_DOWN,
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IPI_CM_MGR_DEBOUNCE_TIMES_RESET_ADB = 16,
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IPI_CM_MGR_DRAM_LEVEL,
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IPI_CM_MGR_LIGHT_LOAD_CPS,
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IPI_CM_MGR_LOADING_ENABLE,
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IPI_CM_MGR_LOADING_LEVEL,
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IPI_CM_MGR_EMI_DEMAND_CHECK,
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IPI_CM_MGR_OPP_FREQ_SET,
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IPI_CM_MGR_OPP_VOLT_SET,
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IPI_CM_MGR_BCPU_WEIGHT_MAX_SET,
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IPI_CM_MGR_BCPU_WEIGHT_MIN_SET,
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IPI_CM_MGR_BBCPU_WEIGHT_MAX_SET,
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IPI_CM_MGR_BBCPU_WEIGHT_MIN_SET,
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IPI_CM_MGR_DSU_DEBOUNCE_UP_SET,
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IPI_CM_MGR_DSU_DEBOUNCE_DOWN_SET,
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IPI_CM_MGR_DSU_DIFF_PWR_UP_SET,
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IPI_CM_MGR_DSU_DIFF_PWR_DOWN_SET,
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IPI_CM_MGR_DSU_L_PWR_RATIO_SET,
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IPI_CM_MGR_DSU_B_PWR_RATIO_SET,
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IPI_CM_MGR_DSU_BB_PWR_RATIO_SET,
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IPI_CM_MGR_DSU_ENABLE = 38,
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IPI_CM_MGR_DSU_OPP_SEND = 39,
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IPI_CM_MGR_DSU_MODE = 40,
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IPI_CM_MGR_HINT = 41,
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IPI_CM_MGR_AGGRESSIVE = 42,
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IPI_CM_MGR_DRAM_OPP_CEILING = 43,
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IPI_CM_MGR_DRAM_OPP_FLOOR = 44,
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IPI_CM_MGR_DSU_PERF_HINT = 45,
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IPI_CM_MGR_PASSIVE = 46,
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IPI_CM_MGR_SSPM_VER = 47,
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NR_IPI_CM_MGR,
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};
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struct cm_ipi_data {
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unsigned int cmd;
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unsigned int arg;
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};
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unsigned int cm_mgr_to_sspm_command(unsigned int cmd, unsigned int val);
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extern void cm_ipi_init(void);
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extern void cm_sspm_enable(int enable);
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extern int cm_get_ipi_enable(void);
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extern void cm_set_ipi_enable(int enable);
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#endif /* __MTK_CM_MGR_IPI_H__ */
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