/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 */

#ifndef __MTK_CM_IPI_H__
#define __MTK_CM_IPI_H__

enum {
	IPI_CM_MGR_SCMI_SET = 0x00000000,
	IPI_CM_MGR_SCMI_GET = 0x10000000,
};

enum {
	IPI_CM_MGR_INIT,
	IPI_CM_MGR_ENABLE,
	IPI_CM_MGR_OPP_ENABLE,
	IPI_CM_MGR_SSPM_ENABLE,
	IPI_CM_MGR_BLANK,
	IPI_CM_MGR_DISABLE_FB,
	IPI_CM_MGR_DRAM_TYPE,
	IPI_CM_MGR_CPU_POWER_RATIO_UP,
	IPI_CM_MGR_CPU_POWER_RATIO_DOWN,
	IPI_CM_MGR_VCORE_POWER_RATIO_UP,
	IPI_CM_MGR_VCORE_POWER_RATIO_DOWN,
	IPI_CM_MGR_DEBOUNCE_UP,
	IPI_CM_MGR_DEBOUNCE_DOWN,
	IPI_CM_MGR_DEBOUNCE_TIMES_RESET_ADB = 16,
	IPI_CM_MGR_DRAM_LEVEL,
	IPI_CM_MGR_LIGHT_LOAD_CPS,
	IPI_CM_MGR_LOADING_ENABLE,
	IPI_CM_MGR_LOADING_LEVEL,
	IPI_CM_MGR_EMI_DEMAND_CHECK,
	IPI_CM_MGR_OPP_FREQ_SET,
	IPI_CM_MGR_OPP_VOLT_SET,
	IPI_CM_MGR_BCPU_WEIGHT_MAX_SET,
	IPI_CM_MGR_BCPU_WEIGHT_MIN_SET,
	IPI_CM_MGR_BBCPU_WEIGHT_MAX_SET,
	IPI_CM_MGR_BBCPU_WEIGHT_MIN_SET,
	IPI_CM_MGR_DSU_DEBOUNCE_UP_SET,
	IPI_CM_MGR_DSU_DEBOUNCE_DOWN_SET,
	IPI_CM_MGR_DSU_DIFF_PWR_UP_SET,
	IPI_CM_MGR_DSU_DIFF_PWR_DOWN_SET,
	IPI_CM_MGR_DSU_L_PWR_RATIO_SET,
	IPI_CM_MGR_DSU_B_PWR_RATIO_SET,
	IPI_CM_MGR_DSU_BB_PWR_RATIO_SET,
	IPI_CM_MGR_DSU_ENABLE = 38,
	IPI_CM_MGR_DSU_OPP_SEND = 39,
	IPI_CM_MGR_DSU_MODE = 40,
	IPI_CM_MGR_HINT = 41,
	IPI_CM_MGR_AGGRESSIVE = 42,
	IPI_CM_MGR_DRAM_OPP_CEILING = 43,
	IPI_CM_MGR_DRAM_OPP_FLOOR = 44,
	IPI_CM_MGR_DSU_PERF_HINT = 45,
	IPI_CM_MGR_PASSIVE = 46,
	IPI_CM_MGR_SSPM_VER = 47,
	NR_IPI_CM_MGR,
};


struct cm_ipi_data {
	unsigned int cmd;
	unsigned int arg;
};

unsigned int cm_mgr_to_sspm_command(unsigned int cmd, unsigned int val);
extern void cm_ipi_init(void);
extern void cm_sspm_enable(int enable);
extern int cm_get_ipi_enable(void);
extern void cm_set_ipi_enable(int enable);

#endif /* __MTK_CM_MGR_IPI_H__ */