483 lines
14 KiB
C
483 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef _MT_MFB_H
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#define _MT_MFB_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/* enforce kernel log enable */
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_MFB_FRAME_REQUEST_ 32
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#define _SUPPORT_MAX_MFB_REQUEST_RING_SIZE_ 32
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/******************************************************************************
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*
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******************************************************************************/
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#define MFB_DEV_MAJOR_NUMBER 258
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#define MFB_MAGIC 'm'
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#define MSS_REG_RANGE (0x1000)
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#define MSS_BASE_HW 0x15012000
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#define MSF_REG_RANGE (0x1000)
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#define MSF_BASE_HW 0x15010000
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#define MSS_INT_ST (1<<0)
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#define MSF_INT_ST (1<<0)
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struct MFB_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct MFB_REG_IO_STRUCT {
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struct MFB_REG_STRUCT *pData; /* pointer to MFB_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/* interrupt clear type */
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enum MFB_IRQ_CLEAR_ENUM {
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MFB_IRQ_CLEAR_NONE, /*non-clear wait, clear after wait */
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MFB_IRQ_CLEAR_WAIT, /*clear wait, clear before and after wait */
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MFB_IRQ_WAIT_CLEAR, /*wait the signal and clear it, avoid the hw
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*executime is too short.
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*/
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MFB_IRQ_CLEAR_STATUS, /*clear specific status only */
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MFB_IRQ_CLEAR_ALL /*clear all status */
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};
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/* module's interrupt , each module should have its own isr. */
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/* note: */
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/* mapping to isr table,ISR_TABLE when using no device tree */
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enum MFB_IRQ_TYPE_ENUM {
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MFB_IRQ_TYPE_INT_MSS_ST, /* MSS */
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MFB_IRQ_TYPE_INT_MSF_ST, /* MSF */
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MFB_IRQ_TYPE_AMOUNT
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};
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struct MFB_WAIT_IRQ_STRUCT {
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enum MFB_IRQ_CLEAR_ENUM Clear;
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enum MFB_IRQ_TYPE_ENUM Type;
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unsigned int Status; /*IRQ Status */
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unsigned int Timeout;
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int UserKey; /* user key for interrupt operation */
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int ProcessID; /* user ProcessID (filled in kernel) */
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unsigned int bDumpReg; /* check dump register or not */
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};
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struct MFB_CLEAR_IRQ_STRUCT {
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enum MFB_IRQ_TYPE_ENUM Type;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status; /* Input */
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};
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struct MFB_Config {
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unsigned int C02_CON;
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unsigned int C02_CROP_CON1;
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unsigned int C02_CROP_CON2;
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unsigned int SRZ_CONTROL;
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unsigned int SRZ_IN_IMG;
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unsigned int SRZ_OUT_IMG;
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unsigned int SRZ_HORI_STEP;
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unsigned int SRZ_VERT_STEP;
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unsigned int SRZ_HORI_INT_OFST;
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unsigned int SRZ_HORI_SUB_OFST;
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unsigned int SRZ_VERT_INT_OFST;
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unsigned int SRZ_VERT_SUB_OFST;
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unsigned int CRSP_CTRL;
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unsigned int CRSP_OUT_IMG;
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unsigned int CRSP_STEP_OFST;
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unsigned int CRSP_CROP_X;
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unsigned int CRSP_CROP_Y;
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unsigned int OMC_TOP;
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unsigned int OMC_ATPG;
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unsigned int OMC_FRAME_SIZE;
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unsigned int OMC_TILE_EDGE;
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unsigned int OMC_TILE_OFS;
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unsigned int OMC_TILE_SIZE;
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unsigned int OMC_TILE_CROP_X;
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unsigned int OMC_TILE_CROP_Y;
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unsigned int OMC_MV_RDMA_BASE_ADDR;
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unsigned int OMC_MV_RDMA_STRIDE;
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unsigned int OMCC_OMC_C_CFIFO_CTL;
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unsigned int OMCC_OMC_C_RWCTL_CTL;
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unsigned int OMCC_OMC_C_CACHI_SPECIAL_FUN_EN;
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unsigned int OMCC_OMC_C_ADDR_GEN_BASE_ADDR_0;
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unsigned int OMCC_OMC_C_ADDR_GEN_OFFSET_ADDR_0;
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unsigned int OMCC_OMC_C_ADDR_GEN_STRIDE_0;
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unsigned int OMCC_OMC_C_ADDR_GEN_BASE_ADDR_1;
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unsigned int OMCC_OMC_C_ADDR_GEN_OFFSET_ADDR_1;
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unsigned int OMCC_OMC_C_ADDR_GEN_STRIDE_1;
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unsigned int OMCC_OMC_C_CACHI_CON2_0;
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unsigned int OMCC_OMC_C_CACHI_CON3_0;
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unsigned int OMCC_OMC_C_CTL_SW_CTL;
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unsigned int OMCC_OMC_C_CTL_CFG;
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unsigned int OMCC_OMC_C_CTL_FMT_SEL;
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unsigned int OMCC_OMC_C_CTL_RSV0;
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unsigned int MFB_CON;
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unsigned int MFB_LL_CON1;
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unsigned int MFB_LL_CON2;
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unsigned int MFB_EDGE;
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unsigned int MFB_LL_CON5;
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unsigned int MFB_LL_CON6;
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unsigned int MFB_LL_CON7;
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unsigned int MFB_LL_CON8;
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unsigned int MFB_LL_CON9;
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unsigned int MFB_LL_CON10;
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unsigned int MFB_MBD_CON0;
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unsigned int MFB_MBD_CON1;
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unsigned int MFB_MBD_CON2;
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unsigned int MFB_MBD_CON3;
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unsigned int MFB_MBD_CON4;
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unsigned int MFB_MBD_CON5;
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unsigned int MFB_MBD_CON6;
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unsigned int MFB_MBD_CON7;
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unsigned int MFB_MBD_CON8;
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unsigned int MFB_MBD_CON9;
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unsigned int MFB_MBD_CON10;
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unsigned int MFB_MFB_TOP_CFG0;
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unsigned int MFB_MFB_TOP_CFG1;
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unsigned int MFB_MFB_TOP_CFG2;
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unsigned int MFB_MFB_INT_CTL;
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unsigned int MFB_MFB_INT_STATUS;
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unsigned int MFB_MFB_SW_RST;
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unsigned int MFB_MFB_MAIN_DCM_ST;
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unsigned int MFB_MFB_DMA_DCM_ST;
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unsigned int MFB_MFB_MAIN_DCM_DIS;
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unsigned int MFB_MFB_DBG_CTL0;
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unsigned int MFB_MFB_DBG_CTL1;
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unsigned int MFB_MFB_DBG_CTL2;
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unsigned int MFB_MFB_DBG_OUT0;
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unsigned int MFB_MFB_DBG_OUT1;
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unsigned int MFB_MFB_DBG_OUT2;
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unsigned int MFB_MFB_DBG_OUT3;
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unsigned int MFB_MFB_DBG_OUT4;
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unsigned int MFB_MFB_DBG_OUT5;
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unsigned int MFB_DFTC;
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unsigned int MFBDMA_DMA_SOFT_RSTSTAT;
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unsigned int MFBDMA_TDRI_BASE_ADDR;
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unsigned int MFBDMA_TDRI_OFST_ADDR;
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unsigned int MFBDMA_TDRI_XSIZE;
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unsigned int MFBDMA_VERTICAL_FLIP_EN;
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unsigned int MFBDMA_DMA_SOFT_RESET;
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unsigned int MFBDMA_LAST_ULTRA_EN;
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unsigned int MFBDMA_SPECIAL_FUN_EN;
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unsigned int MFBDMA_MFBO_BASE_ADDR;
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unsigned int MFBDMA_MFBO_OFST_ADDR;
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unsigned int MFBDMA_MFBO_XSIZE;
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unsigned int MFBDMA_MFBO_YSIZE;
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unsigned int MFBDMA_MFBO_STRIDE;
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unsigned int MFBDMA_MFBO_CON;
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unsigned int MFBDMA_MFBO_CON2;
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unsigned int MFBDMA_MFBO_CON3;
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unsigned int MFBDMA_MFBO_CROP;
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unsigned int MFBDMA_MFB2O_BASE_ADDR;
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unsigned int MFBDMA_MFB2O_OFST_ADDR;
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unsigned int MFBDMA_MFB2O_XSIZE;
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unsigned int MFBDMA_MFB2O_YSIZE;
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unsigned int MFBDMA_MFB2O_STRIDE;
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unsigned int MFBDMA_MFB2O_CON;
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unsigned int MFBDMA_MFB2O_CON2;
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unsigned int MFBDMA_MFB2O_CON3;
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unsigned int MFBDMA_MFB2O_CROP;
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unsigned int MFBDMA_MFBI_BASE_ADDR;
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unsigned int MFBDMA_MFBI_OFST_ADDR;
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unsigned int MFBDMA_MFBI_XSIZE;
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unsigned int MFBDMA_MFBI_YSIZE;
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unsigned int MFBDMA_MFBI_STRIDE;
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unsigned int MFBDMA_MFBI_CON;
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unsigned int MFBDMA_MFBI_CON2;
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unsigned int MFBDMA_MFBI_CON3;
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unsigned int MFBDMA_MFB2I_BASE_ADDR;
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unsigned int MFBDMA_MFB2I_OFST_ADDR;
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unsigned int MFBDMA_MFB2I_XSIZE;
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unsigned int MFBDMA_MFB2I_YSIZE;
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unsigned int MFBDMA_MFB2I_STRIDE;
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unsigned int MFBDMA_MFB2I_CON;
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unsigned int MFBDMA_MFB2I_CON2;
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unsigned int MFBDMA_MFB2I_CON3;
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unsigned int MFBDMA_MFB3I_BASE_ADDR;
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unsigned int MFBDMA_MFB3I_OFST_ADDR;
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unsigned int MFBDMA_MFB3I_XSIZE;
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unsigned int MFBDMA_MFB3I_YSIZE;
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unsigned int MFBDMA_MFB3I_STRIDE;
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unsigned int MFBDMA_MFB3I_CON;
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unsigned int MFBDMA_MFB3I_CON2;
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unsigned int MFBDMA_MFB3I_CON3;
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unsigned int MFBDMA_MFB4I_BASE_ADDR;
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unsigned int MFBDMA_MFB4I_OFST_ADDR;
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unsigned int MFBDMA_MFB4I_XSIZE;
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unsigned int MFBDMA_MFB4I_YSIZE;
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unsigned int MFBDMA_MFB4I_STRIDE;
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unsigned int MFBDMA_MFB4I_CON;
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unsigned int MFBDMA_MFB4I_CON2;
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unsigned int MFBDMA_MFB4I_CON3;
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unsigned int MFBDMA_DMA_ERR_CTRL;
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unsigned int MFBDMA_MFBO_ERR_STAT;
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unsigned int MFBDMA_MFB2O_ERR_STAT;
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unsigned int MFBDMA_MFBO_B_ERR_STAT;
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unsigned int MFBDMA_MFBI_ERR_STAT;
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unsigned int MFBDMA_MFB2I_ERR_STAT;
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unsigned int MFBDMA_MFB3I_ERR_STAT;
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unsigned int MFBDMA_MFB4I_ERR_STAT;
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unsigned int MFBDMA_MFBI_B_ERR_STAT;
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unsigned int MFBDMA_MFB2I_B_ERR_STAT;
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unsigned int MFBDMA_DMA_DEBUG_ADDR;
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unsigned int MFBDMA_DMA_RSV1;
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unsigned int MFBDMA_DMA_RSV2;
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unsigned int MFBDMA_DMA_RSV3;
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unsigned int MFBDMA_DMA_RSV4;
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unsigned int MFBDMA_DMA_DEBUG_SEL;
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unsigned int MFBDMA_DMA_BW_SELF_TEST;
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unsigned int MFBDMA_MFBO_B_BASE_ADDR;
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unsigned int MFBDMA_MFBO_B_OFST_ADDR;
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unsigned int MFBDMA_MFBO_B_XSIZE;
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unsigned int MFBDMA_MFBO_B_YSIZE;
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unsigned int MFBDMA_MFBO_B_STRIDE;
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unsigned int MFBDMA_MFBO_B_CON;
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unsigned int MFBDMA_MFBO_B_CON2;
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unsigned int MFBDMA_MFBO_B_CON3;
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unsigned int MFBDMA_MFBO_B_CROP;
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unsigned int MFBDMA_MFBI_B_BASE_ADDR;
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unsigned int MFBDMA_MFBI_B_OFST_ADDR;
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unsigned int MFBDMA_MFBI_B_XSIZE;
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unsigned int MFBDMA_MFBI_B_YSIZE;
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unsigned int MFBDMA_MFBI_B_STRIDE;
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unsigned int MFBDMA_MFBI_B_CON;
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unsigned int MFBDMA_MFBI_B_CON2;
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unsigned int MFBDMA_MFBI_B_CON3;
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unsigned int MFBDMA_MFB2I_B_BASE_ADDR;
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unsigned int MFBDMA_MFB2I_B_OFST_ADDR;
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unsigned int MFBDMA_MFB2I_B_XSIZE;
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unsigned int MFBDMA_MFB2I_B_YSIZE;
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unsigned int MFBDMA_MFB2I_B_STRIDE;
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unsigned int MFBDMA_MFB2I_B_CON;
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unsigned int MFBDMA_MFB2I_B_CON2;
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unsigned int MFBDMA_MFB2I_B_CON3;
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unsigned int PAK_CONT_Y;
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unsigned int PAK_CONT_C;
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unsigned int UNP_OFST_Y;
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unsigned int UNP_CONT_Y;
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unsigned int UNP_OFST_C;
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unsigned int UNP_CONT_C;
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unsigned int USERDUMP_EN;
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unsigned int TPIPE_NO;
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};
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#define MFB_Config struct MFB_Config
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struct mss_dma {
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unsigned int MSSDMT_IY_BASE;
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unsigned int MSSDMT_IC_BASE;
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unsigned int MSSDMT_OY_BASE;
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unsigned int MSSDMT_OC_BASE;
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};
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#define TPIPE_NUM_PER_FRAME (64)
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struct MFB_MSSConfig {
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unsigned int MSSCMDQ_ENABLE[TPIPE_NUM_PER_FRAME];
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unsigned int MSSCMDQ_BASE[TPIPE_NUM_PER_FRAME];
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unsigned int MSSCQLP_CMD_NUM[TPIPE_NUM_PER_FRAME];
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unsigned int MSSCQLP_ENG_EN;
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unsigned int MSSDMT_TDRI_BASE[TPIPE_NUM_PER_FRAME];
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struct mss_dma dmas[TPIPE_NUM_PER_FRAME];
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unsigned int update_dma_en[TPIPE_NUM_PER_FRAME];
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unsigned int tpipe_used;
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unsigned long qos;
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};
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struct MFB_MSFConfig {
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unsigned int MSFCMDQ_ENABLE[TPIPE_NUM_PER_FRAME];
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unsigned int MSFCMDQ_BASE[TPIPE_NUM_PER_FRAME];
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unsigned int MSFCQLP_CMD_NUM[TPIPE_NUM_PER_FRAME];
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unsigned int MSFCQLP_ENG_EN;
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unsigned int MFBDMT_TDRI_BASE[TPIPE_NUM_PER_FRAME];
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unsigned int MFBDMT_TDRI_OFST[TPIPE_NUM_PER_FRAME];
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unsigned int MFBDMT_TDRI_XSIZE[TPIPE_NUM_PER_FRAME];
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unsigned int tpipe_used;
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unsigned long qos;
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};
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/******************************************************************************
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*
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******************************************************************************/
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enum MFB_CMD_ENUM {
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MFB_CMD_MSS_RESET, /* MSS Reset */
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MFB_CMD_MSF_RESET, /* MSF Reset */
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MFB_CMD_MSS_DUMP_REG, /* Dump MSS Register */
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MFB_CMD_MSF_DUMP_REG, /* Dump MSF Register */
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MFB_CMD_MSS_DUMP_ISR_LOG, /* Dump MSS ISR log */
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MFB_CMD_MSF_DUMP_ISR_LOG, /* Dump MSF ISR log */
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MFB_CMD_MSS_READ_REG, /* Read register from driver */
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MFB_CMD_MSF_READ_REG, /* Read register from driver */
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MFB_CMD_MSS_WRITE_REG, /* Write register to driver */
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MFB_CMD_MSF_WRITE_REG, /* Write register to driver */
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MFB_CMD_MSS_WAIT_IRQ, /* Wait IRQ */
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MFB_CMD_MSF_WAIT_IRQ, /* Wait IRQ */
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MFB_CMD_MSS_CLEAR_IRQ, /* Clear IRQ */
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MFB_CMD_MSF_CLEAR_IRQ, /* Clear IRQ */
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MFB_CMD_MSS_ENQUE_REQ, /* MSS Enque Request */
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MFB_CMD_MSF_ENQUE_REQ, /* MSF Enque Request */
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MFB_CMD_MSS_DEQUE_REQ, /* MSS Deque Request */
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MFB_CMD_MSF_DEQUE_REQ, /* MSF Deque Request */
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MFB_CMD_MAP, /* MFB MAP */
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MFB_CMD_UNMAP, /* MFB UNMAP */
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MFB_CMD_TOTAL,
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};
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enum TPIPE_IRQ_MODE {
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TPIPE_IRQ_FRAME = 0,
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TPIPE_IRQ_TILE = 2,
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};
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struct tpipe_ctrl {
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unsigned int used_tpipe_no;
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unsigned int config_no_per_tpipe;
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unsigned int tdri_ba;
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};
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struct cq_ctrl {
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unsigned int ba;
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unsigned int *va;
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unsigned int en;
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unsigned int cmd_num; /* plus 1 NOP/EXE */
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};
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#define OUT_SCALE_MAX (8)
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#define SMVR_FRAME_MAX (8)
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struct scales_ctrl {
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unsigned int out_scale_used;
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struct cq_ctrl cq_ctl[OUT_SCALE_MAX];
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struct tpipe_ctrl tpipe_ctl[OUT_SCALE_MAX];
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struct mss_dma dmas[SMVR_FRAME_MAX][OUT_SCALE_MAX];
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unsigned int update_dma_en;
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unsigned int update_dma_fnum;
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enum TPIPE_IRQ_MODE tpipe_irq_mode;
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};
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enum exec_mode {
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EXEC_MODE_NORM = 0,
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EXEC_MODE_VSS = 1,
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};
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struct MFB_MSSRequest {
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unsigned int m_ReqNum;
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struct MFB_MSSConfig *m_pMssConfig;
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enum exec_mode exec;
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};
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struct MFB_MSFRequest {
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unsigned int m_ReqNum;
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struct MFB_MSFConfig *m_pMsfConfig;
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enum exec_mode exec;
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};
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#ifdef CONFIG_COMPAT
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struct compat_MFB_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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struct compat_MFB_MSSRequest {
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unsigned int m_ReqNum;
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compat_uptr_t m_pMssConfig;
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};
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struct compat_MFB_MSFRequest {
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unsigned int m_ReqNum;
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compat_uptr_t m_pMsfConfig;
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};
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struct MFB_MapTable {
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unsigned int buf_fd;
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unsigned int buf_offset;
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unsigned int buf_pa;
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};
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#endif
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#define MFB_MSS_RESET _IO(MFB_MAGIC, MFB_CMD_MSS_RESET)
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#define MFB_MSS_DUMP_REG _IO(MFB_MAGIC, MFB_CMD_MSS_DUMP_REG)
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#define MFB_MSS_DUMP_ISR_LOG _IO(MFB_MAGIC, MFB_CMD_MSS_DUMP_ISR_LOG)
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#define MFB_MSF_RESET _IO(MFB_MAGIC, MFB_CMD_MSF_RESET)
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#define MFB_MSF_DUMP_REG _IO(MFB_MAGIC, MFB_CMD_MSF_DUMP_REG)
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#define MFB_MSF_DUMP_ISR_LOG _IO(MFB_MAGIC, MFB_CMD_MSF_DUMP_ISR_LOG)
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#define MFB_MSS_READ_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_READ_REG, struct MFB_REG_IO_STRUCT)
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#define MFB_MSS_WRITE_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_WRITE_REG, struct MFB_REG_IO_STRUCT)
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#define MFB_MSS_WAIT_IRQ \
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_IOW(MFB_MAGIC, MFB_CMD_MSS_WAIT_IRQ, struct MFB_WAIT_IRQ_STRUCT)
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#define MFB_MSS_CLEAR_IRQ \
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_IOW(MFB_MAGIC, MFB_CMD_MSS_CLEAR_IRQ, struct MFB_CLEAR_IRQ_STRUCT)
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#define MFB_MSF_READ_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_READ_REG, struct MFB_REG_IO_STRUCT)
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#define MFB_MSF_WRITE_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_WRITE_REG, struct MFB_REG_IO_STRUCT)
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#define MFB_MSF_WAIT_IRQ \
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_IOW(MFB_MAGIC, MFB_CMD_MSF_WAIT_IRQ, struct MFB_WAIT_IRQ_STRUCT)
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#define MFB_MSF_CLEAR_IRQ \
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_IOW(MFB_MAGIC, MFB_CMD_MSF_CLEAR_IRQ, struct MFB_CLEAR_IRQ_STRUCT)
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#define MFB_MSS_ENQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_ENQUE_REQ, struct MFB_MSSRequest)
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#define MFB_MSS_DEQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_DEQUE_REQ, struct MFB_MSSRequest)
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#define MFB_MSF_ENQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_ENQUE_REQ, struct MFB_MSFRequest)
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#define MFB_MSF_DEQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_DEQUE_REQ, struct MFB_MSFRequest)
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#define MFB_MAP \
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_IOWR(MFB_MAGIC, MFB_CMD_MAP, struct MFB_MapTable)
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#define MFB_UNMAP \
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_IOWR(MFB_MAGIC, MFB_CMD_UNMAP, struct MFB_MapTable)
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#ifdef CONFIG_COMPAT
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#define COMPAT_MFB_MSS_WRITE_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_WRITE_REG, struct compat_MFB_REG_IO_STRUCT)
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#define COMPAT_MFB_MSS_READ_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_READ_REG, struct compat_MFB_REG_IO_STRUCT)
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#define COMPAT_MFB_MSF_WRITE_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_WRITE_REG, struct compat_MFB_REG_IO_STRUCT)
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#define COMPAT_MFB_MSF_READ_REGISTER \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_READ_REG, struct compat_MFB_REG_IO_STRUCT)
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#define COMPAT_MFB_MSS_ENQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_ENQUE_REQ, struct compat_MFB_MSSRequest)
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#define COMPAT_MFB_MSS_DEQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSS_DEQUE_REQ, struct compat_MFB_MSSRequest)
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#define COMPAT_MFB_MSF_ENQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_ENQUE_REQ, struct compat_MFB_MSFRequest)
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#define COMPAT_MFB_MSF_DEQUE_REQ \
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_IOWR(MFB_MAGIC, MFB_CMD_MSF_DEQUE_REQ, struct compat_MFB_MSFRequest)
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#endif
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#endif
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