/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 MediaTek Inc. */ #ifndef _MT_MFB_H #define _MT_MFB_H #include #ifdef CONFIG_COMPAT /* 64 bit */ #include #include #endif /* enforce kernel log enable */ #define KERNEL_LOG /* enable debug log flag if defined */ #define _SUPPORT_MAX_MFB_FRAME_REQUEST_ 32 #define _SUPPORT_MAX_MFB_REQUEST_RING_SIZE_ 32 #define SIG_ERESTARTSYS 512 /* ERESTARTSYS */ /****************************************************************************** * ******************************************************************************/ #define MFB_DEV_MAJOR_NUMBER 258 #define MFB_MAGIC 'm' #define MSS_REG_RANGE (0x1000) #define MSS_BASE_HW 0x15012000 #define MSF_REG_RANGE (0x1000) #define MSF_BASE_HW 0x15010000 #define MSS_INT_ST (1<<0) #define MSF_INT_ST (1<<0) struct MFB_REG_STRUCT { unsigned int module; unsigned int Addr; /* register's addr */ unsigned int Val; /* register's value */ }; struct MFB_REG_IO_STRUCT { struct MFB_REG_STRUCT *pData; /* pointer to MFB_REG_STRUCT */ unsigned int Count; /* count */ }; /* interrupt clear type */ enum MFB_IRQ_CLEAR_ENUM { MFB_IRQ_CLEAR_NONE, /*non-clear wait, clear after wait */ MFB_IRQ_CLEAR_WAIT, /*clear wait, clear before and after wait */ MFB_IRQ_WAIT_CLEAR, /*wait the signal and clear it, avoid the hw *executime is too short. */ MFB_IRQ_CLEAR_STATUS, /*clear specific status only */ MFB_IRQ_CLEAR_ALL /*clear all status */ }; /* module's interrupt , each module should have its own isr. */ /* note: */ /* mapping to isr table,ISR_TABLE when using no device tree */ enum MFB_IRQ_TYPE_ENUM { MFB_IRQ_TYPE_INT_MSS_ST, /* MSS */ MFB_IRQ_TYPE_INT_MSF_ST, /* MSF */ MFB_IRQ_TYPE_AMOUNT }; struct MFB_WAIT_IRQ_STRUCT { enum MFB_IRQ_CLEAR_ENUM Clear; enum MFB_IRQ_TYPE_ENUM Type; unsigned int Status; /*IRQ Status */ unsigned int Timeout; int UserKey; /* user key for interrupt operation */ int ProcessID; /* user ProcessID (filled in kernel) */ unsigned int bDumpReg; /* check dump register or not */ }; struct MFB_CLEAR_IRQ_STRUCT { enum MFB_IRQ_TYPE_ENUM Type; int UserKey; /* user key for doing interrupt operation */ unsigned int Status; /* Input */ }; struct MFB_Config { unsigned int C02_CON; unsigned int C02_CROP_CON1; unsigned int C02_CROP_CON2; unsigned int SRZ_CONTROL; unsigned int SRZ_IN_IMG; unsigned int SRZ_OUT_IMG; unsigned int SRZ_HORI_STEP; unsigned int SRZ_VERT_STEP; unsigned int SRZ_HORI_INT_OFST; unsigned int SRZ_HORI_SUB_OFST; unsigned int SRZ_VERT_INT_OFST; unsigned int SRZ_VERT_SUB_OFST; unsigned int CRSP_CTRL; unsigned int CRSP_OUT_IMG; unsigned int CRSP_STEP_OFST; unsigned int CRSP_CROP_X; unsigned int CRSP_CROP_Y; unsigned int OMC_TOP; unsigned int OMC_ATPG; unsigned int OMC_FRAME_SIZE; unsigned int OMC_TILE_EDGE; unsigned int OMC_TILE_OFS; unsigned int OMC_TILE_SIZE; unsigned int OMC_TILE_CROP_X; unsigned int OMC_TILE_CROP_Y; unsigned int OMC_MV_RDMA_BASE_ADDR; unsigned int OMC_MV_RDMA_STRIDE; unsigned int OMCC_OMC_C_CFIFO_CTL; unsigned int OMCC_OMC_C_RWCTL_CTL; unsigned int OMCC_OMC_C_CACHI_SPECIAL_FUN_EN; unsigned int OMCC_OMC_C_ADDR_GEN_BASE_ADDR_0; unsigned int OMCC_OMC_C_ADDR_GEN_OFFSET_ADDR_0; unsigned int OMCC_OMC_C_ADDR_GEN_STRIDE_0; unsigned int OMCC_OMC_C_ADDR_GEN_BASE_ADDR_1; unsigned int OMCC_OMC_C_ADDR_GEN_OFFSET_ADDR_1; unsigned int OMCC_OMC_C_ADDR_GEN_STRIDE_1; unsigned int OMCC_OMC_C_CACHI_CON2_0; unsigned int OMCC_OMC_C_CACHI_CON3_0; unsigned int OMCC_OMC_C_CTL_SW_CTL; unsigned int OMCC_OMC_C_CTL_CFG; unsigned int OMCC_OMC_C_CTL_FMT_SEL; unsigned int OMCC_OMC_C_CTL_RSV0; unsigned int MFB_CON; unsigned int MFB_LL_CON1; unsigned int MFB_LL_CON2; unsigned int MFB_EDGE; unsigned int MFB_LL_CON5; unsigned int MFB_LL_CON6; unsigned int MFB_LL_CON7; unsigned int MFB_LL_CON8; unsigned int MFB_LL_CON9; unsigned int MFB_LL_CON10; unsigned int MFB_MBD_CON0; unsigned int MFB_MBD_CON1; unsigned int MFB_MBD_CON2; unsigned int MFB_MBD_CON3; unsigned int MFB_MBD_CON4; unsigned int MFB_MBD_CON5; unsigned int MFB_MBD_CON6; unsigned int MFB_MBD_CON7; unsigned int MFB_MBD_CON8; unsigned int MFB_MBD_CON9; unsigned int MFB_MBD_CON10; unsigned int MFB_MFB_TOP_CFG0; unsigned int MFB_MFB_TOP_CFG1; unsigned int MFB_MFB_TOP_CFG2; unsigned int MFB_MFB_INT_CTL; unsigned int MFB_MFB_INT_STATUS; unsigned int MFB_MFB_SW_RST; unsigned int MFB_MFB_MAIN_DCM_ST; unsigned int MFB_MFB_DMA_DCM_ST; unsigned int MFB_MFB_MAIN_DCM_DIS; unsigned int MFB_MFB_DBG_CTL0; unsigned int MFB_MFB_DBG_CTL1; unsigned int MFB_MFB_DBG_CTL2; unsigned int MFB_MFB_DBG_OUT0; unsigned int MFB_MFB_DBG_OUT1; unsigned int MFB_MFB_DBG_OUT2; unsigned int MFB_MFB_DBG_OUT3; unsigned int MFB_MFB_DBG_OUT4; unsigned int MFB_MFB_DBG_OUT5; unsigned int MFB_DFTC; unsigned int MFBDMA_DMA_SOFT_RSTSTAT; unsigned int MFBDMA_TDRI_BASE_ADDR; unsigned int MFBDMA_TDRI_OFST_ADDR; unsigned int MFBDMA_TDRI_XSIZE; unsigned int MFBDMA_VERTICAL_FLIP_EN; unsigned int MFBDMA_DMA_SOFT_RESET; unsigned int MFBDMA_LAST_ULTRA_EN; unsigned int MFBDMA_SPECIAL_FUN_EN; unsigned int MFBDMA_MFBO_BASE_ADDR; unsigned int MFBDMA_MFBO_OFST_ADDR; unsigned int MFBDMA_MFBO_XSIZE; unsigned int MFBDMA_MFBO_YSIZE; unsigned int MFBDMA_MFBO_STRIDE; unsigned int MFBDMA_MFBO_CON; unsigned int MFBDMA_MFBO_CON2; unsigned int MFBDMA_MFBO_CON3; unsigned int MFBDMA_MFBO_CROP; unsigned int MFBDMA_MFB2O_BASE_ADDR; unsigned int MFBDMA_MFB2O_OFST_ADDR; unsigned int MFBDMA_MFB2O_XSIZE; unsigned int MFBDMA_MFB2O_YSIZE; unsigned int MFBDMA_MFB2O_STRIDE; unsigned int MFBDMA_MFB2O_CON; unsigned int MFBDMA_MFB2O_CON2; unsigned int MFBDMA_MFB2O_CON3; unsigned int MFBDMA_MFB2O_CROP; unsigned int MFBDMA_MFBI_BASE_ADDR; unsigned int MFBDMA_MFBI_OFST_ADDR; unsigned int MFBDMA_MFBI_XSIZE; unsigned int MFBDMA_MFBI_YSIZE; unsigned int MFBDMA_MFBI_STRIDE; unsigned int MFBDMA_MFBI_CON; unsigned int MFBDMA_MFBI_CON2; unsigned int MFBDMA_MFBI_CON3; unsigned int MFBDMA_MFB2I_BASE_ADDR; unsigned int MFBDMA_MFB2I_OFST_ADDR; unsigned int MFBDMA_MFB2I_XSIZE; unsigned int MFBDMA_MFB2I_YSIZE; unsigned int MFBDMA_MFB2I_STRIDE; unsigned int MFBDMA_MFB2I_CON; unsigned int MFBDMA_MFB2I_CON2; unsigned int MFBDMA_MFB2I_CON3; unsigned int MFBDMA_MFB3I_BASE_ADDR; unsigned int MFBDMA_MFB3I_OFST_ADDR; unsigned int MFBDMA_MFB3I_XSIZE; unsigned int MFBDMA_MFB3I_YSIZE; unsigned int MFBDMA_MFB3I_STRIDE; unsigned int MFBDMA_MFB3I_CON; unsigned int MFBDMA_MFB3I_CON2; unsigned int MFBDMA_MFB3I_CON3; unsigned int MFBDMA_MFB4I_BASE_ADDR; unsigned int MFBDMA_MFB4I_OFST_ADDR; unsigned int MFBDMA_MFB4I_XSIZE; unsigned int MFBDMA_MFB4I_YSIZE; unsigned int MFBDMA_MFB4I_STRIDE; unsigned int MFBDMA_MFB4I_CON; unsigned int MFBDMA_MFB4I_CON2; unsigned int MFBDMA_MFB4I_CON3; unsigned int MFBDMA_DMA_ERR_CTRL; unsigned int MFBDMA_MFBO_ERR_STAT; unsigned int MFBDMA_MFB2O_ERR_STAT; unsigned int MFBDMA_MFBO_B_ERR_STAT; unsigned int MFBDMA_MFBI_ERR_STAT; unsigned int MFBDMA_MFB2I_ERR_STAT; unsigned int MFBDMA_MFB3I_ERR_STAT; unsigned int MFBDMA_MFB4I_ERR_STAT; unsigned int MFBDMA_MFBI_B_ERR_STAT; unsigned int MFBDMA_MFB2I_B_ERR_STAT; unsigned int MFBDMA_DMA_DEBUG_ADDR; unsigned int MFBDMA_DMA_RSV1; unsigned int MFBDMA_DMA_RSV2; unsigned int MFBDMA_DMA_RSV3; unsigned int MFBDMA_DMA_RSV4; unsigned int MFBDMA_DMA_DEBUG_SEL; unsigned int MFBDMA_DMA_BW_SELF_TEST; unsigned int MFBDMA_MFBO_B_BASE_ADDR; unsigned int MFBDMA_MFBO_B_OFST_ADDR; unsigned int MFBDMA_MFBO_B_XSIZE; unsigned int MFBDMA_MFBO_B_YSIZE; unsigned int MFBDMA_MFBO_B_STRIDE; unsigned int MFBDMA_MFBO_B_CON; unsigned int MFBDMA_MFBO_B_CON2; unsigned int MFBDMA_MFBO_B_CON3; unsigned int MFBDMA_MFBO_B_CROP; unsigned int MFBDMA_MFBI_B_BASE_ADDR; unsigned int MFBDMA_MFBI_B_OFST_ADDR; unsigned int MFBDMA_MFBI_B_XSIZE; unsigned int MFBDMA_MFBI_B_YSIZE; unsigned int MFBDMA_MFBI_B_STRIDE; unsigned int MFBDMA_MFBI_B_CON; unsigned int MFBDMA_MFBI_B_CON2; unsigned int MFBDMA_MFBI_B_CON3; unsigned int MFBDMA_MFB2I_B_BASE_ADDR; unsigned int MFBDMA_MFB2I_B_OFST_ADDR; unsigned int MFBDMA_MFB2I_B_XSIZE; unsigned int MFBDMA_MFB2I_B_YSIZE; unsigned int MFBDMA_MFB2I_B_STRIDE; unsigned int MFBDMA_MFB2I_B_CON; unsigned int MFBDMA_MFB2I_B_CON2; unsigned int MFBDMA_MFB2I_B_CON3; unsigned int PAK_CONT_Y; unsigned int PAK_CONT_C; unsigned int UNP_OFST_Y; unsigned int UNP_CONT_Y; unsigned int UNP_OFST_C; unsigned int UNP_CONT_C; unsigned int USERDUMP_EN; unsigned int TPIPE_NO; }; #define MFB_Config struct MFB_Config struct mss_dma { unsigned int MSSDMT_IY_BASE; unsigned int MSSDMT_IC_BASE; unsigned int MSSDMT_OY_BASE; unsigned int MSSDMT_OC_BASE; }; #define TPIPE_NUM_PER_FRAME (64) struct MFB_MSSConfig { unsigned int MSSCMDQ_ENABLE[TPIPE_NUM_PER_FRAME]; unsigned int MSSCMDQ_BASE[TPIPE_NUM_PER_FRAME]; unsigned int MSSCQLP_CMD_NUM[TPIPE_NUM_PER_FRAME]; unsigned int MSSCQLP_ENG_EN; unsigned int MSSDMT_TDRI_BASE[TPIPE_NUM_PER_FRAME]; struct mss_dma dmas[TPIPE_NUM_PER_FRAME]; unsigned int update_dma_en[TPIPE_NUM_PER_FRAME]; unsigned int tpipe_used; unsigned long qos; }; struct MFB_MSFConfig { unsigned int MSFCMDQ_ENABLE[TPIPE_NUM_PER_FRAME]; unsigned int MSFCMDQ_BASE[TPIPE_NUM_PER_FRAME]; unsigned int MSFCQLP_CMD_NUM[TPIPE_NUM_PER_FRAME]; unsigned int MSFCQLP_ENG_EN; unsigned int MFBDMT_TDRI_BASE[TPIPE_NUM_PER_FRAME]; unsigned int MFBDMT_TDRI_OFST[TPIPE_NUM_PER_FRAME]; unsigned int MFBDMT_TDRI_XSIZE[TPIPE_NUM_PER_FRAME]; unsigned int tpipe_used; unsigned long qos; }; /****************************************************************************** * ******************************************************************************/ enum MFB_CMD_ENUM { MFB_CMD_MSS_RESET, /* MSS Reset */ MFB_CMD_MSF_RESET, /* MSF Reset */ MFB_CMD_MSS_DUMP_REG, /* Dump MSS Register */ MFB_CMD_MSF_DUMP_REG, /* Dump MSF Register */ MFB_CMD_MSS_DUMP_ISR_LOG, /* Dump MSS ISR log */ MFB_CMD_MSF_DUMP_ISR_LOG, /* Dump MSF ISR log */ MFB_CMD_MSS_READ_REG, /* Read register from driver */ MFB_CMD_MSF_READ_REG, /* Read register from driver */ MFB_CMD_MSS_WRITE_REG, /* Write register to driver */ MFB_CMD_MSF_WRITE_REG, /* Write register to driver */ MFB_CMD_MSS_WAIT_IRQ, /* Wait IRQ */ MFB_CMD_MSF_WAIT_IRQ, /* Wait IRQ */ MFB_CMD_MSS_CLEAR_IRQ, /* Clear IRQ */ MFB_CMD_MSF_CLEAR_IRQ, /* Clear IRQ */ MFB_CMD_MSS_ENQUE_REQ, /* MSS Enque Request */ MFB_CMD_MSF_ENQUE_REQ, /* MSF Enque Request */ MFB_CMD_MSS_DEQUE_REQ, /* MSS Deque Request */ MFB_CMD_MSF_DEQUE_REQ, /* MSF Deque Request */ MFB_CMD_MAP, /* MFB MAP */ MFB_CMD_UNMAP, /* MFB UNMAP */ MFB_CMD_TOTAL, }; enum TPIPE_IRQ_MODE { TPIPE_IRQ_FRAME = 0, TPIPE_IRQ_TILE = 2, }; struct tpipe_ctrl { unsigned int used_tpipe_no; unsigned int config_no_per_tpipe; unsigned int tdri_ba; }; struct cq_ctrl { unsigned int ba; unsigned int *va; unsigned int en; unsigned int cmd_num; /* plus 1 NOP/EXE */ }; #define OUT_SCALE_MAX (8) #define SMVR_FRAME_MAX (8) struct scales_ctrl { unsigned int out_scale_used; struct cq_ctrl cq_ctl[OUT_SCALE_MAX]; struct tpipe_ctrl tpipe_ctl[OUT_SCALE_MAX]; struct mss_dma dmas[SMVR_FRAME_MAX][OUT_SCALE_MAX]; unsigned int update_dma_en; unsigned int update_dma_fnum; enum TPIPE_IRQ_MODE tpipe_irq_mode; }; enum exec_mode { EXEC_MODE_NORM = 0, EXEC_MODE_VSS = 1, }; struct MFB_MSSRequest { unsigned int m_ReqNum; struct MFB_MSSConfig *m_pMssConfig; enum exec_mode exec; }; struct MFB_MSFRequest { unsigned int m_ReqNum; struct MFB_MSFConfig *m_pMsfConfig; enum exec_mode exec; }; #ifdef CONFIG_COMPAT struct compat_MFB_REG_IO_STRUCT { compat_uptr_t pData; unsigned int Count; /* count */ }; struct compat_MFB_MSSRequest { unsigned int m_ReqNum; compat_uptr_t m_pMssConfig; }; struct compat_MFB_MSFRequest { unsigned int m_ReqNum; compat_uptr_t m_pMsfConfig; }; struct MFB_MapTable { unsigned int buf_fd; unsigned int buf_offset; unsigned int buf_pa; }; #endif #define MFB_MSS_RESET _IO(MFB_MAGIC, MFB_CMD_MSS_RESET) #define MFB_MSS_DUMP_REG _IO(MFB_MAGIC, MFB_CMD_MSS_DUMP_REG) #define MFB_MSS_DUMP_ISR_LOG _IO(MFB_MAGIC, MFB_CMD_MSS_DUMP_ISR_LOG) #define MFB_MSF_RESET _IO(MFB_MAGIC, MFB_CMD_MSF_RESET) #define MFB_MSF_DUMP_REG _IO(MFB_MAGIC, MFB_CMD_MSF_DUMP_REG) #define MFB_MSF_DUMP_ISR_LOG _IO(MFB_MAGIC, MFB_CMD_MSF_DUMP_ISR_LOG) #define MFB_MSS_READ_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_READ_REG, struct MFB_REG_IO_STRUCT) #define MFB_MSS_WRITE_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_WRITE_REG, struct MFB_REG_IO_STRUCT) #define MFB_MSS_WAIT_IRQ \ _IOW(MFB_MAGIC, MFB_CMD_MSS_WAIT_IRQ, struct MFB_WAIT_IRQ_STRUCT) #define MFB_MSS_CLEAR_IRQ \ _IOW(MFB_MAGIC, MFB_CMD_MSS_CLEAR_IRQ, struct MFB_CLEAR_IRQ_STRUCT) #define MFB_MSF_READ_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_READ_REG, struct MFB_REG_IO_STRUCT) #define MFB_MSF_WRITE_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_WRITE_REG, struct MFB_REG_IO_STRUCT) #define MFB_MSF_WAIT_IRQ \ _IOW(MFB_MAGIC, MFB_CMD_MSF_WAIT_IRQ, struct MFB_WAIT_IRQ_STRUCT) #define MFB_MSF_CLEAR_IRQ \ _IOW(MFB_MAGIC, MFB_CMD_MSF_CLEAR_IRQ, struct MFB_CLEAR_IRQ_STRUCT) #define MFB_MSS_ENQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_ENQUE_REQ, struct MFB_MSSRequest) #define MFB_MSS_DEQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_DEQUE_REQ, struct MFB_MSSRequest) #define MFB_MSF_ENQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_ENQUE_REQ, struct MFB_MSFRequest) #define MFB_MSF_DEQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_DEQUE_REQ, struct MFB_MSFRequest) #define MFB_MAP \ _IOWR(MFB_MAGIC, MFB_CMD_MAP, struct MFB_MapTable) #define MFB_UNMAP \ _IOWR(MFB_MAGIC, MFB_CMD_UNMAP, struct MFB_MapTable) #ifdef CONFIG_COMPAT #define COMPAT_MFB_MSS_WRITE_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_WRITE_REG, struct compat_MFB_REG_IO_STRUCT) #define COMPAT_MFB_MSS_READ_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_READ_REG, struct compat_MFB_REG_IO_STRUCT) #define COMPAT_MFB_MSF_WRITE_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_WRITE_REG, struct compat_MFB_REG_IO_STRUCT) #define COMPAT_MFB_MSF_READ_REGISTER \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_READ_REG, struct compat_MFB_REG_IO_STRUCT) #define COMPAT_MFB_MSS_ENQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_ENQUE_REQ, struct compat_MFB_MSSRequest) #define COMPAT_MFB_MSS_DEQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSS_DEQUE_REQ, struct compat_MFB_MSSRequest) #define COMPAT_MFB_MSF_ENQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_ENQUE_REQ, struct compat_MFB_MSFRequest) #define COMPAT_MFB_MSF_DEQUE_REQ \ _IOWR(MFB_MAGIC, MFB_CMD_MSF_DEQUE_REQ, struct compat_MFB_MSFRequest) #endif #endif