1523 lines
55 KiB
C
1523 lines
55 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef OPLUS_LTPO_1080P_H
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#define OPLUS_LTPO_1080P_H
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#include <linux/trace_events.h>
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#define REGFLAG_CMD 0xFFFA
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#define REGFLAG_DELAY 0xFFFC
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#define REGFLAG_UDELAY 0xFFFB
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#define REGFLAG_END_OF_TABLE 0xFFFD
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enum MODE_ID {
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WQHD_SDC60 = 0,
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WQHD_SDC120 = 1,
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WQHD_SDC90 = 2,
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FHD_SDC60 = 3,
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FHD_SDC120 = 4,
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FHD_SDC90 = 5,
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MODE_NUM = 6
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};
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extern bool g_trace_log;
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extern unsigned long mtk_drm_get_tracing_mark(void);
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#define mtk_drm_trace_begin(fmt, args...) do { \
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if (g_trace_log) { \
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preempt_disable(); \
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event_trace_printk(mtk_drm_get_tracing_mark(), \
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"B|%d|"fmt"\n", current->tgid, ##args); \
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preempt_enable();\
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} \
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} while (0)
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#define mtk_drm_trace_end() do { \
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if (g_trace_log) { \
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preempt_disable(); \
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event_trace_printk(mtk_drm_get_tracing_mark(), "E\n"); \
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preempt_enable(); \
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} \
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} while (0)
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#define mtk_drm_trace_c(fmt, args...) do { \
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if (g_trace_log) { \
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preempt_disable(); \
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event_trace_printk(mtk_drm_get_tracing_mark(), \
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"C|"fmt"\n", ##args); \
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preempt_enable();\
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} \
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} while (0)
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struct LCM_setting_table {
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unsigned int cmd;
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unsigned int count;
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unsigned char para_list[256];
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};
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//fake frame cmd, used for sdc 90/120
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struct LCM_setting_table fakeframe_cmd[] = {
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{REGFLAG_CMD, 1, {0x2C}},
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{REGFLAG_CMD, 1, {0x3C}},
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{REGFLAG_CMD, 1, {0x2C}},
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{REGFLAG_CMD, 1, {0x3C}},
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{REGFLAG_CMD, 1, {0x00}},
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};
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//auto on cmd
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struct LCM_setting_table autoon_cmd[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x10}}, // 0x00:1frame 0x10:2frame 0x20:3frame
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{REGFLAG_CMD, 2, {0xBD, 0x23}}, // 0x21:Manual On 0x23:Auto On
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//auto off sdc60 cmd
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struct LCM_setting_table autooff_cmd_sdc60[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0xBD, 0x21}}, // 0x21:Manual On 0x23:Auto On
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//auto off sdc120 cmd
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struct LCM_setting_table autooff_cmd_sdc120[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0xBD, 0x21}}, // 0x21:Manual On 0x23:Auto On
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x00}}, // 0x00:1frame 0x10:2frame 0x20:3frame
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//min-fps 0 cmd
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struct LCM_setting_table minfps0_cmd[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0x60, 0x00}}, /* Manual Setting */
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//min-fps 1 cmd
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struct LCM_setting_table minfps1_cmd[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x14, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x00}}, //SDC Auto mode Low Freq. Setting
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//WQHD DSC 10bit
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struct LCM_setting_table wqhd_dsc_cmd[] = {
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{REGFLAG_CMD, 90,
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{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
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0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
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0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
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0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
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0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
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0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
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0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
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0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
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0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
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0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
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{REGFLAG_CMD, 2, {0x9D, 0x01}},
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};
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//FHD DSC 10bit
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struct LCM_setting_table fhd_dsc_cmd[] = {
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{REGFLAG_CMD, 90,
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{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
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0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
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0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
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0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
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0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
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0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
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0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
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0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
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0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
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0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
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{REGFLAG_CMD, 2, {0x9D, 0x01}},
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};
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//pre-switch cmd
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struct LCM_setting_table pre_switch_cmd[] = {
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}}, // Level2 key Access Enable
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x14, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x00}}, //SDC auto mode min == max
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{REGFLAG_CMD, 2, {0xBD, 0x23}}, //21 : Manual On 23 Auto On
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}}, // Level2 key Access Disable
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};
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//wqhd sdc 120 param setting
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//timing-switch cmd
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struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc120[] = {
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/* CASET/PASET Setting */
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{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
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{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
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/* Scaler Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0xC3, 0x00}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc120[] = {
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/* OPLUS ADFR OFF */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
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{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
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/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
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{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* TSP_SYNC1 Fixed Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x02}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* TSP_SYNC3 Fixed Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x21}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x02}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* 120hz Transition */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
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{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
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{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
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{REGFLAG_CMD, 2, {0x60, 0x00}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x10}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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};
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//dsi-on cmd
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struct LCM_setting_table wqhd_dsi_on_cmd_sdc120[] = {
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//DSC 10bit
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{REGFLAG_CMD, 90,
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{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
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0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
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0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
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0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
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0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
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0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
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0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
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0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
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0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
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0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
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{REGFLAG_CMD, 2, {0x9D, 0x01}},
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{REGFLAG_CMD, 1, {0x11}},
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{REGFLAG_DELAY, 6, {}},
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/* TSP_SYNC1 Fixed Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x02}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* TSP_SYNC3 Fixed Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x21}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
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{REGFLAG_CMD, 2, {0xB9, 0x02}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
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{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* 120hz Transition */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
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{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
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{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
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{REGFLAG_CMD, 2, {0x60, 0x00}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
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{REGFLAG_CMD, 2, {0xBD, 0x10}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* Common Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* TE(Vsync) ON */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0x35, 0x00}},
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{REGFLAG_CMD, 2, {0xB9, 0x02}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* CASET/PASET Setting */
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{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
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{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
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/* Scaler Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0xC3, 0x00}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* Pre-charge time setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
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{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* HLPM Power Saving */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
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{REGFLAG_CMD, 2, {0xF4, 0x08}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* DCDC setting of AOD Sequence */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
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{REGFLAG_CMD, 2, {0xB1, 0x05}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* Brightness Control */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
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{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
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{REGFLAG_CMD, 2, {0x63, 0x00}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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{REGFLAG_CMD, 2, {0x53, 0x28}},
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{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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/* ACL Mode */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0x55, 0x00}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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/* OPEC Setting */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
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{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06,
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|
0x89, 0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//wqhd sdc 60 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc60[] = {
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc60[] = {
|
|
/* OPLUS ADFR OFF */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},//miss
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
|
|
/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},//miss
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},//miss
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},//miss
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},//miss
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},//miss
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},//miss
|
|
|
|
/* 60hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x01}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},//miss
|
|
{REGFLAG_CMD, 2, {0xBD, 0x00}}, /* HOP force off */
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}}, //miss
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table wqhd_dsi_on_cmd_sdc60[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
|
|
0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
|
|
0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
|
|
0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 60hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x01}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
/* ACL Mode */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x55, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* OPEC Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
|
|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
|
|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//wqhd sdc 90 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc90[] = {
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc90[] = {
|
|
/* OPLUS ADFR OFF */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
|
|
/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* 90hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x08}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
//dsi-on cmd
|
|
struct LCM_setting_table wqhd_dsi_on_cmd_sdc90[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
|
|
0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
|
|
0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
|
|
0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 90hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x08}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
/* ACL Mode */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x55, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* OPEC Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
|
|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
|
|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//wqhd OA 120 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table wqhd_timing_switch_cmd_oa120[] = {
|
|
};
|
|
|
|
//dsi-on cmd
|
|
struct LCM_setting_table wqhd_dsi_on_cmd_oa120[] = {
|
|
//DSC 10bit
|
|
};
|
|
|
|
//wqhd OM 60 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table wqhd_timing_switch_cmd_om60[] = {
|
|
};
|
|
|
|
//dsi-on cmd
|
|
struct LCM_setting_table wqhd_dsi_on_cmd_om60[] = {
|
|
//DSC 10bit
|
|
};
|
|
|
|
//fhd sdc 120 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc120[] = {
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
struct LCM_setting_table fhd_timing_switch_2_cmd_sdc120[] = {
|
|
/* OPLUS ADFR OFF */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
|
|
/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* 120hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table fhd_dsi_on_cmd_sdc120[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
|
|
0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
|
|
0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
|
|
0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 120hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
/* ACL Mode */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x55, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* OPEC Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
|
|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
|
|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//fhd sdc 60 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc60[] = {
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
struct LCM_setting_table fhd_timing_switch_2_cmd_sdc60[] = {
|
|
/* OPLUS ADFR OFF */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
|
|
/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* 60hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x01}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x00}}, /* HOP force off */
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table fhd_dsi_on_cmd_sdc60[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
|
|
0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
|
|
0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
|
|
0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x05}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 60hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x01}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
/* ACL Mode */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x55, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* OPEC Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
|
|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
|
|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//fhd sdc 90 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc90[] = {
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
struct LCM_setting_table fhd_timing_switch_2_cmd_sdc90[] = {
|
|
/* OPLUS ADFR OFF */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x00}}, /* TP shift fixed */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}}, /* OPLUS ADFR OFF */
|
|
/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
|
|
/* 90hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x08}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table fhd_dsi_on_cmd_sdc90[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
|
|
0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
|
|
0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
|
|
0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x03}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 90hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x08}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x89}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
|
|
0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
|
|
0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
|
|
{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
|
|
0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
|
|
{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
|
|
0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
|
|
0xFE, 0x00, 0xFE, 0x00, 0xFE}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
/* ACL Mode */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x55, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* OPEC Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
|
|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
|
|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
|
|
{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
|
|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
|
|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
|
|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
|
|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//fhd osync 120 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table fhd_timing_switch_cmd_oa120[] = {
|
|
};
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table fhd_dsi_on_cmd_oa120[] = {
|
|
//DSC 10bit
|
|
};
|
|
|
|
//fhd OM 60 params setting
|
|
//timing-switch cmd
|
|
struct LCM_setting_table fhd_timing_switch_cmd_om60[] = {
|
|
};
|
|
|
|
//dsi-on command
|
|
struct LCM_setting_table fhd_dsi_on_cmd_om60[] = {
|
|
//DSC 10bit
|
|
};
|
|
|
|
struct LCM_setting_table lcm_setbrightness_normal[] = {
|
|
{REGFLAG_CMD, 2, {0x53, 0x20}},
|
|
{REGFLAG_CMD, 3, {0x51, 0x00, 0x00}},
|
|
};
|
|
|
|
struct LCM_setting_table lcm_setbrightness_hbm[] = {
|
|
{REGFLAG_CMD, 3, {0x51, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x53, 0xE8}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
//HBM command
|
|
struct LCM_setting_table lcm_finger_HBM_on_setting[] = {
|
|
|
|
{REGFLAG_CMD, 2, {0x53, 0xE0}},
|
|
{REGFLAG_CMD, 3, {0x51, 0x0F, 0xFF}},
|
|
};
|
|
|
|
struct LCM_setting_table lcm_normal_HBM_on_setting[] = {
|
|
/* ELVSS DIM OFF, DLY OFF*/
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0x51, 0x07, 0xFF}},
|
|
{REGFLAG_DELAY, 20, {}},
|
|
{REGFLAG_CMD, 3, {0xB0, 0x01, 0x49}},
|
|
//{REGFLAG_CMD, 1, {0x49, 0x28}},
|
|
{REGFLAG_CMD, 2, {0x53, 0xE0}},
|
|
{REGFLAG_CMD, 3, {0x51, 0x08, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
};
|
|
struct LCM_setting_table lcm_normal_to_aod_sam[] = {
|
|
//DSC 10bit
|
|
{REGFLAG_CMD, 90,
|
|
{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
|
|
0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
|
|
0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
|
|
0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
|
|
0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
|
|
0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
|
|
0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
|
|
0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
|
|
0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
|
|
0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
|
|
{REGFLAG_CMD, 2, {0x9D, 0x01}},
|
|
{REGFLAG_CMD, 1, {0x11}},
|
|
{REGFLAG_DELAY, 6, {}},
|
|
/* TSP_SYNC1 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TSP_SYNC3 Fixed Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x21}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
|
|
{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* 120hz Transition */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
|
|
{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
|
|
{REGFLAG_CMD, 2, {0x60, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
|
|
{REGFLAG_CMD, 2, {0xBD, 0x10}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Common Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* TE(Vsync) ON */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x35, 0x00}},
|
|
{REGFLAG_CMD, 2, {0xB9, 0x02}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* CASET/PASET Setting */
|
|
{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
|
|
{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
|
|
/* Scaler Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0xC3, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Pre-charge time setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
|
|
{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* HLPM Power Saving */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
|
|
{REGFLAG_CMD, 2, {0xF4, 0x08}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* DCDC setting of AOD Sequence */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
|
|
{REGFLAG_CMD, 2, {0xB1, 0x05}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* Brightness Control */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x01}}, /* Dimming Setting */
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
|
|
{REGFLAG_CMD, 2, {0x63, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0xF7, 0x0F}},
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/* ACL Mode */
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{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 2, {0x55, 0x00}},
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{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
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|
/* OPEC Setting */
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|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
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|
{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
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|
0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
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{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
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{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
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|
0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
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|
0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
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|
0x10, 0x53}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
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|
{REGFLAG_CMD, 2, {0x1F, 0x02}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
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|
{REGFLAG_CMD, 2, {0x1F, 0x00}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
/* AOD Mode ON Setting */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x24}},
|
|
{REGFLAG_CMD, 2, {0x49, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_DELAY, 20, {}},
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|
{REGFLAG_CMD, 1, {0x29}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
struct LCM_setting_table lcm_aod_to_normal[] = {
|
|
{REGFLAG_CMD, 1, {0x28}},
|
|
{REGFLAG_DELAY, 20, {}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x28}},
|
|
{REGFLAG_CMD, 2, {0x49, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_DELAY, 20, {}},
|
|
{REGFLAG_CMD, 1, {0x29}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
|
|
};
|
|
struct LCM_setting_table lcm_aod_high_mode[] = {
|
|
/* aod 50nit*/
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x24}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
struct LCM_setting_table lcm_aod_low_mode[] = {
|
|
/* aod 10nit*/
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x53, 0x27}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
struct LCM_setting_table lcm_seed_mode0[] = {
|
|
/* SEED CRC OFF*/
|
|
{REGFLAG_CMD, 2, {0x1C, 0x00}},
|
|
/* SEED CRC BYPASS */
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 2, {0x1D, 0x01}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
|
|
struct LCM_setting_table lcm_seed_mode1[] = {
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x02, 0xB6, 0x1D}},
|
|
{REGFLAG_CMD, 2, {0x1D, 0x25}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xA5, 0x1F}},
|
|
{REGFLAG_CMD, 9, {0x1F, 0xE2, 0x00, 0x00, 0x00, 0x92, 0x2C, 0x6A, 0x80}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xAD, 0x1F}},
|
|
{REGFLAG_CMD, 7, {0x1F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x90}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xB5, 0x1F}},
|
|
{REGFLAG_CMD, 4, {0x1F, 0x49, 0x00, 0x10}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xBA, 0x1F}},
|
|
{REGFLAG_CMD, 6, {0x1F, 0x05, 0xFF, 0x10, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC1, 0x1F}},
|
|
{REGFLAG_CMD, 5, {0x1F, 0x00, 0x00, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC5, 0x1F}},
|
|
{REGFLAG_CMD, 5, {0x1F, 0x03, 0xFF, 0x21, 0x3C}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
struct LCM_setting_table lcm_seed_mode2[] = {
|
|
{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x02, 0xB6, 0x1D}},
|
|
{REGFLAG_CMD, 2, {0x1D, 0x25}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xA5, 0x1F}},
|
|
{REGFLAG_CMD, 9, {0x1F, 0xE2, 0x00, 0x00, 0x00, 0x92, 0x2C, 0x6A, 0x80}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xAD, 0x1F}},
|
|
{REGFLAG_CMD, 7, {0x1F, 0x7D, 0x64, 0x7E, 0x65, 0xFF, 0x90}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xB5, 0x1F}},
|
|
{REGFLAG_CMD, 4, {0x1F, 0x49, 0x00, 0x10}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xBA, 0x1F}},
|
|
{REGFLAG_CMD, 6, {0x1F, 0x05, 0xFF, 0x10, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC1, 0x1F}},
|
|
{REGFLAG_CMD, 5, {0x1F, 0x00, 0x00, 0x00, 0x00}},
|
|
{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC5, 0x1F}},
|
|
{REGFLAG_CMD, 5, {0x1F, 0x03, 0xFF, 0x21, 0x3C}},
|
|
{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
|
|
{REGFLAG_END_OF_TABLE, 0x00, {}}
|
|
};
|
|
#endif
|