/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

#ifndef OPLUS_LTPO_1080P_H
#define OPLUS_LTPO_1080P_H

#include <linux/trace_events.h>

#define REGFLAG_CMD       0xFFFA
#define REGFLAG_DELAY       0xFFFC
#define REGFLAG_UDELAY  0xFFFB
#define REGFLAG_END_OF_TABLE    0xFFFD


enum MODE_ID {
	WQHD_SDC60 = 0,
	WQHD_SDC120 = 1,
	WQHD_SDC90 = 2,
	FHD_SDC60 = 3,
	FHD_SDC120 = 4,
	FHD_SDC90 = 5,
	MODE_NUM = 6
};

extern bool g_trace_log;
extern unsigned long mtk_drm_get_tracing_mark(void);

#define mtk_drm_trace_begin(fmt, args...) do { \
	if (g_trace_log) { \
		preempt_disable(); \
		event_trace_printk(mtk_drm_get_tracing_mark(), \
			"B|%d|"fmt"\n", current->tgid, ##args); \
		preempt_enable();\
	} \
} while (0)

#define mtk_drm_trace_end() do { \
	if (g_trace_log) { \
		preempt_disable(); \
		event_trace_printk(mtk_drm_get_tracing_mark(), "E\n"); \
		preempt_enable(); \
	} \
} while (0)

#define mtk_drm_trace_c(fmt, args...) do { \
	if (g_trace_log) { \
		preempt_disable(); \
		event_trace_printk(mtk_drm_get_tracing_mark(), \
			"C|"fmt"\n", ##args); \
		preempt_enable();\
	} \
} while (0)

struct LCM_setting_table {
	unsigned int cmd;
	unsigned int count;
	unsigned char para_list[256];
};

//fake frame cmd, used for sdc 90/120
struct LCM_setting_table fakeframe_cmd[] = {
	{REGFLAG_CMD, 1, {0x2C}},
	{REGFLAG_CMD, 1, {0x3C}},
	{REGFLAG_CMD, 1, {0x2C}},
	{REGFLAG_CMD, 1, {0x3C}},
	{REGFLAG_CMD, 1, {0x00}},
};
//auto on cmd
struct LCM_setting_table autoon_cmd[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}}, // 0x00:1frame 0x10:2frame 0x20:3frame
	{REGFLAG_CMD, 2, {0xBD, 0x23}}, // 0x21:Manual On 0x23:Auto On
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//auto off sdc60 cmd
struct LCM_setting_table autooff_cmd_sdc60[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xBD, 0x21}}, // 0x21:Manual On 0x23:Auto On
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//auto off sdc120 cmd
struct LCM_setting_table autooff_cmd_sdc120[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xBD, 0x21}}, // 0x21:Manual On 0x23:Auto On
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}}, // 0x00:1frame 0x10:2frame 0x20:3frame
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//min-fps 0 cmd
struct LCM_setting_table minfps0_cmd[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* Manual Setting */
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};
//min-fps 1 cmd
struct LCM_setting_table minfps1_cmd[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x14, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}}, //SDC Auto mode Low Freq. Setting
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//WQHD DSC 10bit
struct LCM_setting_table wqhd_dsc_cmd[] = {
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
			0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
			0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
			0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
};

//FHD DSC 10bit
struct LCM_setting_table fhd_dsc_cmd[] = {
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
			0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
			0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
			0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
};

//pre-switch cmd
struct LCM_setting_table pre_switch_cmd[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}}, // Level2 key Access Enable
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x14, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}}, //SDC auto mode min == max
	{REGFLAG_CMD, 2, {0xBD, 0x23}}, //21 : Manual On  23 Auto On
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}}, // Level2 key Access Disable
};

//wqhd sdc 120 param setting
//timing-switch cmd
struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc120[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc120[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},

	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},

	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* 120hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},

	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},

	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};


//dsi-on cmd
struct LCM_setting_table wqhd_dsi_on_cmd_sdc120[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
			0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
			0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
			0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},

	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},

	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 120hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},

	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},

	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06,
			0x89, 0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//wqhd sdc 60 params setting
//timing-switch cmd
struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc60[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc60[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},//miss
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},//miss
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},//miss
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},//miss
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},//miss
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},//miss
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},//miss

	/* 60hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x01}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},//miss
	{REGFLAG_CMD, 2, {0xBD, 0x00}},	/* HOP force off */
	{REGFLAG_CMD, 2, {0xF7, 0x0F}}, //miss
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//dsi-on command
struct LCM_setting_table wqhd_dsi_on_cmd_sdc60[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
			0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
			0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
			0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 60hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x01}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//wqhd sdc 90 params setting
//timing-switch cmd
struct LCM_setting_table wqhd_timing_switch_1_cmd_sdc90[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table wqhd_timing_switch_2_cmd_sdc90[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* 90hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
	{REGFLAG_CMD, 2, {0x60, 0x08}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//dsi-on cmd
struct LCM_setting_table wqhd_dsi_on_cmd_sdc90[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
			0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
			0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
			0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 90hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
	{REGFLAG_CMD, 2, {0x60, 0x08}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//wqhd OA 120 params setting
//timing-switch cmd
struct LCM_setting_table wqhd_timing_switch_cmd_oa120[] = {
};

//dsi-on cmd
struct LCM_setting_table wqhd_dsi_on_cmd_oa120[] = {
	//DSC 10bit
};

//wqhd OM 60 params setting
//timing-switch cmd
struct LCM_setting_table wqhd_timing_switch_cmd_om60[] = {
};

//dsi-on cmd
struct LCM_setting_table wqhd_dsi_on_cmd_om60[] = {
	//DSC 10bit
};

//fhd sdc 120 params setting
//timing-switch cmd
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc120[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table fhd_timing_switch_2_cmd_sdc120[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* 120hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//dsi-on command
struct LCM_setting_table fhd_dsi_on_cmd_sdc120[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
			0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
			0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
			0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 120hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//fhd sdc 60 params setting
//timing-switch cmd
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc60[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table fhd_timing_switch_2_cmd_sdc60[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* 60hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x01}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}},	  /* HOP force off */
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

//dsi-on command
struct LCM_setting_table fhd_dsi_on_cmd_sdc60[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
			0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
			0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
			0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x05}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 60hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x01}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//fhd sdc 90 params setting
//timing-switch cmd
struct LCM_setting_table fhd_timing_switch_1_cmd_sdc90[] = {
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};

struct LCM_setting_table fhd_timing_switch_2_cmd_sdc90[] = {
	/* OPLUS ADFR OFF */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xFC, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xB9, 0x00}},	/* TP shift fixed */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x02, 0x60}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},	/* OPLUS ADFR OFF */
	/* 0x01 0x00:ADFR ON setting 0x00 0x01:ADFR OFF Setting */
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xFC, 0xA5, 0xA5}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},

	/* 90hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
	{REGFLAG_CMD, 2, {0x60, 0x08}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};


//dsi-on command
struct LCM_setting_table fhd_dsi_on_cmd_sdc90[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x09, 0x6C, 0x04,
			0x38, 0x00, 0x24, 0x02, 0x1C, 0x02, 0x1C, 0x02, 0x00,
			0x02, 0x3B, 0x00, 0x20, 0x03, 0x35, 0x00, 0x07, 0x00,
			0x0E, 0x03, 0x34, 0x02, 0xD4, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x03}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 90hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x24, 0x70}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x03}},
	{REGFLAG_CMD, 2, {0x60, 0x08}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x04, 0x37}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x09, 0x6B}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x89}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00,
			0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD, 0x00, 0xFD}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00,
			0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0, 0x00, 0xB0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x50, 0xC3}},
	{REGFLAG_CMD, 18, {0xC3, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00,
			0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43, 0x00, 0x43}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x61, 0xC3}},
	{REGFLAG_CMD, 23, {0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xC0, 0xFE, 0x00, 0xFE,
			0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00,
			0xFE, 0x00, 0xFE, 0x00, 0xFE}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 1, {0x29}},

	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//fhd osync 120 params setting
//timing-switch cmd
struct LCM_setting_table fhd_timing_switch_cmd_oa120[] = {
};

//dsi-on command
struct LCM_setting_table fhd_dsi_on_cmd_oa120[] = {
	//DSC 10bit
};

//fhd OM 60 params setting
//timing-switch cmd
struct LCM_setting_table fhd_timing_switch_cmd_om60[] = {
};

//dsi-on command
struct LCM_setting_table fhd_dsi_on_cmd_om60[] = {
	//DSC 10bit
};

struct LCM_setting_table lcm_setbrightness_normal[] = {
	{REGFLAG_CMD, 2, {0x53, 0x20}},
	{REGFLAG_CMD, 3, {0x51, 0x00, 0x00}},
};

struct LCM_setting_table lcm_setbrightness_hbm[] = {
	{REGFLAG_CMD, 3, {0x51, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0x53, 0xE8}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

//HBM command
struct LCM_setting_table lcm_finger_HBM_on_setting[] = {

	{REGFLAG_CMD, 2, {0x53, 0xE0}},
	{REGFLAG_CMD, 3, {0x51, 0x0F, 0xFF}},
};

struct LCM_setting_table lcm_normal_HBM_on_setting[] = {
	/* ELVSS DIM OFF, DLY OFF*/
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0x51, 0x07, 0xFF}},
	{REGFLAG_DELAY, 20, {}},
	{REGFLAG_CMD, 3, {0xB0, 0x01, 0x49}},
	//{REGFLAG_CMD, 1, {0x49, 0x28}},
	{REGFLAG_CMD, 2, {0x53, 0xE0}},
	{REGFLAG_CMD, 3, {0x51, 0x08, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
};
struct LCM_setting_table lcm_normal_to_aod_sam[] = {
	//DSC 10bit
	{REGFLAG_CMD, 90,
		{0x9E, 0x11, 0x00, 0x00, 0xAB, 0x30, 0x80, 0x0C, 0x90, 0x05,
			0xA0, 0x00, 0x18, 0x02, 0xD0, 0x02, 0xD0, 0x02, 0x00,
			0x02, 0x86, 0x00, 0x20, 0x02, 0x83, 0x00, 0x0A, 0x00,
			0x0D, 0x04, 0x86, 0x03, 0x2E, 0x18, 0x00, 0x10, 0xF0,
			0x07, 0x10, 0x20, 0x00, 0x06, 0x0F, 0x0F, 0x33, 0x0E,
			0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
			0x79, 0x7B, 0x7D, 0x7E, 0x02, 0x02, 0x22, 0x00, 0x2A,
			0x40, 0x2A, 0xBE, 0x3A, 0xFC, 0x3A, 0xFA, 0x3A, 0xF8,
			0x3B, 0x38, 0x3B, 0x78, 0x3B, 0xB6, 0x4B, 0xB6, 0x4B,
			0xF4, 0x4B, 0xF4, 0x6C, 0x34, 0x84, 0x74, 0x00}},
	{REGFLAG_CMD, 2, {0x9D, 0x01}},
	{REGFLAG_CMD, 1, {0x11}},
	{REGFLAG_DELAY, 6, {}},
	/* TSP_SYNC1 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x22, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0xA1, 0xB1}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x3A, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x26, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TSP_SYNC3 Fixed Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x24, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x21}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x38, 0xB9}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2A, 0xB9}},
	{REGFLAG_CMD, 3, {0xB9, 0x00, 0x00}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* 120hz Transition */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x16, 0xF2}},
	{REGFLAG_CMD, 3, {0xF2, 0x1B, 0x50}},
	{REGFLAG_CMD, 3, {0xBD, 0x21, 0x02}},
	{REGFLAG_CMD, 2, {0x60, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x10, 0xBD}},
	{REGFLAG_CMD, 2, {0xBD, 0x10}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Common Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 3, {0xF2, 0x00, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* TE(Vsync) ON */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x35, 0x00}},
	{REGFLAG_CMD, 2, {0xB9, 0x02}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* CASET/PASET Setting */
	{REGFLAG_CMD, 5, {0x2A, 0x00, 0x00, 0x05, 0x9F}},
	{REGFLAG_CMD, 5, {0x2B, 0x00, 0x00, 0x0C, 0x8F}},
	/* Scaler Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0xC3, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Pre-charge time setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x2B, 0xF6}},
	{REGFLAG_CMD, 4, {0xF6, 0x60, 0x63, 0x69}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* HLPM Power Saving */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x46, 0xF4}},
	{REGFLAG_CMD, 2, {0xF4, 0x08}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* DCDC setting of AOD Sequence */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x18, 0xB1}},
	{REGFLAG_CMD, 2, {0xB1, 0x05}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* Brightness Control */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0D, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x01}},	 /* Dimming Setting */
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x0C, 0x63}},
	{REGFLAG_CMD, 2, {0x63, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0xF7, 0x0F}},
	/* ACL Mode */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x55, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* OPEC Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x56, 0x1F}},
	{REGFLAG_CMD, 17, {0x1F, 0x01, 0x17, 0x01, 0x18, 0x06, 0x88, 0x06, 0x89,
			0x0A, 0xE2, 0x0A, 0xE3, 0x11, 0xF5, 0x1B, 0xC0}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x6A, 0x1F}},
	{REGFLAG_CMD, 29, {0x1F, 0x01, 0x17, 0x03, 0x44, 0x04, 0x5A, 0x05, 0x71,
			0x06, 0x88, 0x07, 0x9E, 0x08, 0xB5, 0x09, 0xCB, 0x0A,
			0xE2, 0x0B, 0xF9, 0x0D, 0x0F, 0x0E, 0x26, 0x0F, 0x3C,
			0x10, 0x53}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x52, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x02}},
	{REGFLAG_CMD, 4, {0xB0, 0x00, 0x54, 0x1F}},
	{REGFLAG_CMD, 2, {0x1F, 0x00}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	/* AOD Mode ON Setting */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x53, 0x24}},
	{REGFLAG_CMD, 2, {0x49, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_DELAY, 20, {}},
	{REGFLAG_CMD, 1, {0x29}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};
struct LCM_setting_table lcm_aod_to_normal[] = {
	{REGFLAG_CMD, 1, {0x28}},
	{REGFLAG_DELAY, 20, {}},
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x53, 0x28}},
	{REGFLAG_CMD, 2, {0x49, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_DELAY, 20, {}},
	{REGFLAG_CMD, 1, {0x29}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}

};
struct LCM_setting_table lcm_aod_high_mode[] = {
	/* aod 50nit*/
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x53, 0x24}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

struct LCM_setting_table lcm_aod_low_mode[] = {
	/* aod 10nit*/
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x53, 0x27}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};
struct LCM_setting_table lcm_seed_mode0[] = {
	/* SEED CRC OFF*/
	{REGFLAG_CMD, 2, {0x1C, 0x00}},
	/* SEED CRC BYPASS */
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 2, {0x1D, 0x01}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};

struct LCM_setting_table lcm_seed_mode1[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x02, 0xB6, 0x1D}},
	{REGFLAG_CMD, 2, {0x1D, 0x25}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xA5, 0x1F}},
	{REGFLAG_CMD, 9, {0x1F, 0xE2, 0x00, 0x00, 0x00, 0x92, 0x2C, 0x6A, 0x80}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xAD, 0x1F}},
	{REGFLAG_CMD, 7, {0x1F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x90}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xB5, 0x1F}},
	{REGFLAG_CMD, 4, {0x1F, 0x49, 0x00, 0x10}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xBA, 0x1F}},
	{REGFLAG_CMD, 6, {0x1F, 0x05, 0xFF, 0x10, 0x00, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC1, 0x1F}},
	{REGFLAG_CMD, 5, {0x1F, 0x00, 0x00, 0x00, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC5, 0x1F}},
	{REGFLAG_CMD, 5, {0x1F, 0x03, 0xFF, 0x21, 0x3C}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};
struct LCM_setting_table lcm_seed_mode2[] = {
	{REGFLAG_CMD, 3, {0xF0, 0x5A, 0x5A}},
	{REGFLAG_CMD, 4, {0xB0, 0x02, 0xB6, 0x1D}},
	{REGFLAG_CMD, 2, {0x1D, 0x25}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xA5, 0x1F}},
	{REGFLAG_CMD, 9, {0x1F, 0xE2, 0x00, 0x00, 0x00, 0x92, 0x2C, 0x6A, 0x80}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xAD, 0x1F}},
	{REGFLAG_CMD, 7, {0x1F, 0x7D, 0x64, 0x7E, 0x65, 0xFF, 0x90}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xB5, 0x1F}},
	{REGFLAG_CMD, 4, {0x1F, 0x49, 0x00, 0x10}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xBA, 0x1F}},
	{REGFLAG_CMD, 6, {0x1F, 0x05, 0xFF, 0x10, 0x00, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC1, 0x1F}},
	{REGFLAG_CMD, 5, {0x1F, 0x00, 0x00, 0x00, 0x00}},
	{REGFLAG_CMD, 4, {0xB0, 0x01, 0xC5, 0x1F}},
	{REGFLAG_CMD, 5, {0x1F, 0x03, 0xFF, 0x21, 0x3C}},
	{REGFLAG_CMD, 3, {0xF0, 0xA5, 0xA5}},
	{REGFLAG_END_OF_TABLE, 0x00, {}}
};
#endif