148 lines
8.2 KiB
C
148 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Jianjiao Zeng <jianjiao.zeng@mediatek.com>
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*/
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#ifndef _DTS_IOMMU_PORT_MT6835_H_
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#define _DTS_IOMMU_PORT_MT6835_H_
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#include <dt-bindings/memory/mtk-memory-port.h>
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/* table id must be the same as mtk_iommu.h */
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#define MM_TAB (0)
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/* iova region definition */
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#define NORMAL_DOM (0)
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#define CAM_MDP_DOM (1)
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#define AIE_RESV_DOM (2)
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#define LK_RESV_DOM (3)
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#define VDEC_VENC_DOM (4)
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#define VDO_REGION1 (5)
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#define VDO_REGION2 (6)
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#define VDO_REGION3 (7)
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#define VDO_REGION4 (8)
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/* larb0 */
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#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 0)
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#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 1)
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#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 2)
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#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 3)
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#define M4U_PORT_L0_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 4)
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/* larb1 */
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#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 0)
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#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 1)
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#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 2)
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#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 3)
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#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 4)
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/* larb2 */
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#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 0)
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#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 1)
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#define M4U_PORT_L2_MDP_WROT2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 2)
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#define M4U_PORT_L2_MDP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 3)
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/* larb4 */
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#define M4U_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 0)
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#define M4U_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 2)
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#define M4U_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 3)
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#define M4U_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 4)
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#define M4U_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 5)
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#define M4U_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 6)
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#define M4U_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 7)
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#define M4U_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 8)
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#define M4U_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 9)
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/* larb7 */
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#define M4U_PORT_L7_VENC_RCPU MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 0)
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#define M4U_PORT_L7_VENC_REC MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 1)
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#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 2)
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#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 3)
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#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 4)
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#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 5)
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#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 6)
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#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 7)
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#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 8)
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#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 9)
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#define M4U_PORT_L7_JPGENC_C_RDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 10)
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#define M4U_PORT_L7_JPGENC_Q_TABLE MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 11)
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#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 12)
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/* larb9 */
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#define M4U_PORT_L9_IMGI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 0)
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#define M4U_PORT_L9_IMGBI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 1)
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#define M4U_PORT_L9_DMGI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 2)
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#define M4U_PORT_L9_UFDI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 3)
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#define M4U_PORT_L9_LCEI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 4)
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#define M4U_PORT_L9_SMTI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 5)
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#define M4U_PORT_L9_SMTO_D2 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 6)
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#define M4U_PORT_L9_SMTO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 7)
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#define M4U_PORT_L9_CRZO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 8)
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#define M4U_PORT_L9_IMG3O_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 9)
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#define M4U_PORT_L9_VIPI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 10)
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#define M4U_PORT_L9_SMTI_D5 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 11)
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#define M4U_PORT_L9_TIMGO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 12)
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/* larb13 */
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#define M4U_PORT_L13_CAMSV_TOP_1_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 6)
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#define M4U_PORT_L13_CAMSV_TOP_2_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 7)
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#define M4U_PORT_L13_CAMSV_TOP_3_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 8)
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#define M4U_PORT_L13_FAKE MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 11)
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/* larb16 */
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#define M4U_PORT_L16_IMGO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 0)
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#define M4U_PORT_L16_RRZO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 1)
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#define M4U_PORT_L16_CQI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 2)
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#define M4U_PORT_L16_BPCI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 3)
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#define M4U_PORT_L16_YUVO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 4)
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#define M4U_PORT_L16_UFDI_R2_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 5)
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#define M4U_PORT_L16_RAWI_R2_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 6)
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#define M4U_PORT_L16_RAWI_R3_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 7)
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#define M4U_PORT_L16_AAO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 8)
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#define M4U_PORT_L16_AFO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 9)
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#define M4U_PORT_L16_FLKO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 10)
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#define M4U_PORT_L16_LCESO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 11)
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#define M4U_PORT_L16_CRZO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 12)
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#define M4U_PORT_L16_LTMSO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 13)
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#define M4U_PORT_L16_RSSO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 14)
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#define M4U_PORT_L16_AAHO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 15)
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#define M4U_PORT_L16_LSCI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 16)
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/* larb17 */
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#define M4U_PORT_L17_IMGO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 0)
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#define M4U_PORT_L17_RRZO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 1)
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#define M4U_PORT_L17_CQI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 2)
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#define M4U_PORT_L17_BPCI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 3)
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#define M4U_PORT_L17_YUVO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 4)
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#define M4U_PORT_L17_UFDI_R2_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 5)
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#define M4U_PORT_L17_RAWI_R2_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 6)
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#define M4U_PORT_L17_RAWI_R3_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 7)
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#define M4U_PORT_L17_AAO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 8)
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#define M4U_PORT_L17_AFO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 9)
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#define M4U_PORT_L17_FLKO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 10)
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#define M4U_PORT_L17_LCESO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 11)
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#define M4U_PORT_L17_CRZO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 12)
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#define M4U_PORT_L17_LTMSO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 13)
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#define M4U_PORT_L17_RSSO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 14)
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#define M4U_PORT_L17_AAHO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 15)
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#define M4U_PORT_L17_LSCI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 16)
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/* larb20 */
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#define M4U_PORT_L20_FDVT_RDA MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 0)
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#define M4U_PORT_L20_FDVT_RDB MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 1)
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#define M4U_PORT_L20_FDVT_WRA MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 2)
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#define M4U_PORT_L20_FDVT_WRB MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 3)
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/* fake larb21 */
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#define M4U_LARB21_VIDEO_UP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 0)
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#define M4U_LARB21_GCE_DM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 1)
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#define M4U_LARB21_GCE_MM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 2)
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/* fake larb22 reserved */
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#define M4U_PORT_L22_VIDEO_UP_512MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION1, 22, 0)
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#define M4U_PORT_L22_VIDEO_UP_512MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION2, 22, 1)
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#define M4U_PORT_L22_VIDEO_UP_256MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION3, 22, 2)
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#define M4U_PORT_L22_VIDEO_UP_256MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION4, 22, 3)
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#endif
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