/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Jianjiao Zeng */ #ifndef _DTS_IOMMU_PORT_MT6835_H_ #define _DTS_IOMMU_PORT_MT6835_H_ #include /* table id must be the same as mtk_iommu.h */ #define MM_TAB (0) /* iova region definition */ #define NORMAL_DOM (0) #define CAM_MDP_DOM (1) #define AIE_RESV_DOM (2) #define LK_RESV_DOM (3) #define VDEC_VENC_DOM (4) #define VDO_REGION1 (5) #define VDO_REGION2 (6) #define VDO_REGION3 (7) #define VDO_REGION4 (8) /* larb0 */ #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 0) #define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 1) #define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 2) #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 3) #define M4U_PORT_L0_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 4) /* larb1 */ #define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 0) #define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 1) #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 2) #define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 3) #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 4) /* larb2 */ #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 0) #define M4U_PORT_L2_MDP_WROT0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 1) #define M4U_PORT_L2_MDP_WROT2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 2) #define M4U_PORT_L2_MDP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 3) /* larb4 */ #define M4U_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 0) #define M4U_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 2) #define M4U_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 3) #define M4U_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 4) #define M4U_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 5) #define M4U_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 6) #define M4U_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 7) #define M4U_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 8) #define M4U_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 4, 9) /* larb7 */ #define M4U_PORT_L7_VENC_RCPU MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 0) #define M4U_PORT_L7_VENC_REC MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 1) #define M4U_PORT_L7_VENC_BSDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 2) #define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 3) #define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 4) #define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 5) #define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 6) #define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 7) #define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 8) #define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 9) #define M4U_PORT_L7_JPGENC_C_RDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 10) #define M4U_PORT_L7_JPGENC_Q_TABLE MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 11) #define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_PORT_ID(MM_TAB, VDEC_VENC_DOM, 7, 12) /* larb9 */ #define M4U_PORT_L9_IMGI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 0) #define M4U_PORT_L9_IMGBI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 1) #define M4U_PORT_L9_DMGI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 2) #define M4U_PORT_L9_UFDI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 3) #define M4U_PORT_L9_LCEI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 4) #define M4U_PORT_L9_SMTI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 5) #define M4U_PORT_L9_SMTO_D2 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 6) #define M4U_PORT_L9_SMTO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 7) #define M4U_PORT_L9_CRZO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 8) #define M4U_PORT_L9_IMG3O_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 9) #define M4U_PORT_L9_VIPI_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 10) #define M4U_PORT_L9_SMTI_D5 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 11) #define M4U_PORT_L9_TIMGO_D1 MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 9, 12) /* larb13 */ #define M4U_PORT_L13_CAMSV_TOP_1_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 6) #define M4U_PORT_L13_CAMSV_TOP_2_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 7) #define M4U_PORT_L13_CAMSV_TOP_3_IMGO MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 8) #define M4U_PORT_L13_FAKE MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 13, 11) /* larb16 */ #define M4U_PORT_L16_IMGO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 0) #define M4U_PORT_L16_RRZO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 1) #define M4U_PORT_L16_CQI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 2) #define M4U_PORT_L16_BPCI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 3) #define M4U_PORT_L16_YUVO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 4) #define M4U_PORT_L16_UFDI_R2_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 5) #define M4U_PORT_L16_RAWI_R2_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 6) #define M4U_PORT_L16_RAWI_R3_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 7) #define M4U_PORT_L16_AAO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 8) #define M4U_PORT_L16_AFO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 9) #define M4U_PORT_L16_FLKO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 10) #define M4U_PORT_L16_LCESO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 11) #define M4U_PORT_L16_CRZO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 12) #define M4U_PORT_L16_LTMSO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 13) #define M4U_PORT_L16_RSSO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 14) #define M4U_PORT_L16_AAHO_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 15) #define M4U_PORT_L16_LSCI_R1_A MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 16, 16) /* larb17 */ #define M4U_PORT_L17_IMGO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 0) #define M4U_PORT_L17_RRZO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 1) #define M4U_PORT_L17_CQI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 2) #define M4U_PORT_L17_BPCI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 3) #define M4U_PORT_L17_YUVO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 4) #define M4U_PORT_L17_UFDI_R2_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 5) #define M4U_PORT_L17_RAWI_R2_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 6) #define M4U_PORT_L17_RAWI_R3_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 7) #define M4U_PORT_L17_AAO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 8) #define M4U_PORT_L17_AFO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 9) #define M4U_PORT_L17_FLKO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 10) #define M4U_PORT_L17_LCESO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 11) #define M4U_PORT_L17_CRZO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 12) #define M4U_PORT_L17_LTMSO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 13) #define M4U_PORT_L17_RSSO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 14) #define M4U_PORT_L17_AAHO_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 15) #define M4U_PORT_L17_LSCI_R1_B MTK_M4U_PORT_ID(MM_TAB, CAM_MDP_DOM, 17, 16) /* larb20 */ #define M4U_PORT_L20_FDVT_RDA MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 0) #define M4U_PORT_L20_FDVT_RDB MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 1) #define M4U_PORT_L20_FDVT_WRA MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 2) #define M4U_PORT_L20_FDVT_WRB MTK_M4U_PORT_ID(MM_TAB, AIE_RESV_DOM, 20, 3) /* fake larb21 */ #define M4U_LARB21_VIDEO_UP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 0) #define M4U_LARB21_GCE_DM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 1) #define M4U_LARB21_GCE_MM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 2) /* fake larb22 reserved */ #define M4U_PORT_L22_VIDEO_UP_512MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION1, 22, 0) #define M4U_PORT_L22_VIDEO_UP_512MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION2, 22, 1) #define M4U_PORT_L22_VIDEO_UP_256MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION3, 22, 2) #define M4U_PORT_L22_VIDEO_UP_256MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION4, 22, 3) #endif