1965 lines
78 KiB
Text
1965 lines
78 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Device Tree defines for LCM settings
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_lcm_settings.h"
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&pio {
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nt36672e_fhdp_dphy_vdo_jdi_120hz: nt36672e-fhdp-dphy-vdo-jdi-120hz {
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compatible = "mediatek,nt36672e_fhdp_dphy_vdo_jdi_120hz";
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lcm-version = <0>;
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lcm-params{
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compatible = "mediatek,lcm-params";
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lcm-params-name = "nt36672e-fhdp-dphy-vdo-jdi-120hz";
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lcm-params-types = <MTK_LCM_FUNC_DSI>;
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lcm-params-resolution = <1080 2400>;
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lcm-params-physical-width = <70>;
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lcm-params-physical-height = <152>;
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/* lk support */
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lcm-params-lk {
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compatible = "mediatek,lcm-params-lk";
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lcm-params-lk-ctrl;
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lcm-params-lk-lcm-if;
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lcm-params-lk-lcm-cmd-if;
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lcm-params-lk-io-select-mode;
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lcm-params-lk-lcm-x;
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lcm-params-lk-lcm-y;
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lcm-params-lk-virtual-resolution = <0 0>;
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lcm-params-lk-od-table-size;
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lcm-params-lk-od-table;
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};
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lcm-params-lk-round-corner {
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compatible = "mediatek,lcm-params-lk-round-corner";
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lcm-params-lk-rc-round-corner-en = <0>;
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lcm-params-lk-rc-is-notch;
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lcm-params-lk-rc-full-content = <0>;
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lcm-params-lk-rc-width;
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lcm-params-lk-rc-height;
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lcm-params-lk-rc-width-bot;
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lcm-params-lk-rc-height-bot;
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lcm-params-lk-rc-top-size;
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lcm-params-lk-rc-top-size-left;
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lcm-params-lk-rc-top-size-right;
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lcm-params-lk-rc-bottom-size;
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lcm-params-lk-rc-pattern-name;
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};
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lcm-params-dbi {
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compatible = "mediatek,lcm-params-dbi";
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/* future reserved for dbi interfaces */
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};
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lcm-params-dpi {
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compatible = "mediatek,lcm-params-dpi";
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/* future reserved for dpi interfaces */
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};
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lcm-params-dsi {
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compatible = "mediatek,lcm-params-dsi";
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lcm-params-dsi-density = <480>;
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lcm-params-dsi-lanes = <4>;
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lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
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lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
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lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_VIDEO>,
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<MTK_MIPI_DSI_MODE_VIDEO_SYNC_PULSE>,
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<MTK_MIPI_DSI_MODE_LPM>,
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<MTK_MIPI_DSI_MODE_EOT_PACKET>,
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<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
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lcm-params-dsi-mode-flags-doze-on;
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lcm-params-dsi-mode-flags-doze-off;
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lcm-params-dsi-need-fake-resolution;
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lcm-params-dsi-fake-resolution = <1080 2400>;
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lcm-gpio-list = <&pio 42 0>, /* gpio list*/
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<&pio 28 0>,
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<&pio 29 0>;
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pinctrl-names = "gpio1", "gpio2", "gpio3";
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pinctrl-0;
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pinctrl-1;
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pinctrl-2;
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status = "okay";
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lcm-params-dsi-default-mode = <0>;
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lcm-params-dsi-mode-count = <6>;
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lcm-params-dsi-mode-list =
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<0 1080 2400 60>,
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<1 1080 2400 90>,
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<2 1080 2400 120>,
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<3 1080 2400 30>,
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<4 1080 2400 24>,
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<5 1080 2400 10>;
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lcm-params-dsi-fps-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fps-0-1080-2400-60";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <60>;
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lcm-params-dsi-vertical-sync-active = <10>;
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lcm-params-dsi-vertical-backporch = <10>;
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lcm-params-dsi-vertical-frontporch = <2528>;
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lcm-params-dsi-vertical-active-line = <2400>;
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lcm-params-dsi-horizontal-sync-active = <12>;
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lcm-params-dsi-horizontal-backporch = <80>;
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lcm-params-dsi-horizontal-frontporch = <76>;
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lcm-params-dsi-horizontal-active-pixel = <1080>;
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lcm-params-dsi-pixel-clock = <370506>;
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lcm-params-dsi-hskew;
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lcm-params-dsi-vscan;
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/* mtk-panel-params */
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lcm-params-dsi-pll-clock = <551>;
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lcm-params-dsi-data-rate = <1102>;
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lcm-params-dsi-vfp-for-low-power = <4180>;
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lcm-params-dsi-ssc-enable = <1>;
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lcm-params-dsi-ssc-range;
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lcm-params-dsi-lcm-color-mode;
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lcm-params-dsi-min-luminance;
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lcm-params-dsi-average-luminance;
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lcm-params-dsi-max-luminance;
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lcm-params-dsi-round-corner-en = <0>;
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lcm-params-dsi-corner-pattern-height;
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lcm-params-dsi-corner-pattern-height-bot;
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lcm-params-dsi-corner-pattern-tp-size;
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lcm-params-dsi-corner-pattern-tp-size-left;
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lcm-params-dsi-corner-pattern-tp-size-right;
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lcm-params-dsi-corner-pattern-name;
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lcm-params-dsi-physical-width-um;
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lcm-params-dsi-physical-height-um;
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lcm-params-dsi-output-mode =
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<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
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lcm-params-dsi-lcm-cmd-if;
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lcm-params-dsi-hbm-en-time;
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lcm-params-dsi-hbm-dis-time;
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lcm-params-dsi-lcm-index;
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lcm-params-dsi-wait-sof-before-dec-vfp;
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lcm-params-dsi-doze-delay;
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lcm-params-dsi-lfr-enable = <0>;
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lcm-params-dsi-lfr-minimum-fps = <60>;
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lcm-params-dsi-msync2-enable;
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lcm-params-dsi-max-vfp-for-msync;
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/* lane swap */
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lcm-params-dsi-lane-swap-en = <1>;
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lcm-params-dsi-lane-swap0 =
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<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
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<LCM_LANE_CK LCM_LANE_0>;
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lcm-params-dsi-lane-swap1 =
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<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
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<LCM_LANE_CK LCM_LANE_0>;
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/* esd check table */
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lcm-params-dsi-cust-esd-check = <1>;
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lcm-params-dsi-esd-check-enable = <1>;
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lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
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lcm-params-dsi-lcm-esd-check-table1;
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lcm-params-dsi-lcm-esd-check-table2;
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/* Msync 3.0 */
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lcm-params-dsi-skip-vblank = <0>;
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/* fpga support */
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lcm-params-dsi-fpga-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fpga-params";
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lcm-params-dsi-lk-pll-div = <0 0>;
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lcm-params-dsi-lk-fbk-div = <1>;
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};
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/* lk support */
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lcm-params-dsi-lk-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-lk-params";
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lcm-params-dsi-lk-mode =
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<MTK_LK_SYNC_PULSE_VDO_MODE>;
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lcm-params-dsi-lk-switch-mode = <MTK_LK_CMD_MODE>;
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lcm-params-dsi-lk-switch-mode-enable = <0>;
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lcm-params-dsi-lk-dsi-wmem-conti;
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lcm-params-dsi-lk-dsi-rmem-conti;
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lcm-params-dsi-lk-vc-num;
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lcm-params-dsi-lk-data-format =
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<MTK_LCM_COLOR_ORDER_RGB>,
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<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
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<MTK_LCM_DSI_PADDING_ON_LSB>,
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<MTK_LCM_DSI_FORMAT_RGB888>;
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lcm-params-dsi-lk-intermediat-buffer-num;
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lcm-params-dsi-lk-ps =
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<MTK_LCM_PACKED_PS_24BIT_RGB888>;
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lcm-params-dsi-lk-word-count;
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lcm-params-dsi-lk-packet-size = <256>;
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lcm-params-dsi-lk-horizontal-blanking-pixel;
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lcm-params-dsi-lk-bllp;
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lcm-params-dsi-lk-line-byte;
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lcm-params-dsi-lk-horizontal-sync-active-byte;
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lcm-params-dsi-lk-horizontal-backporch-byte;
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lcm-params-dsi-lk-horizontal-frontporch-byte;
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lcm-params-dsi-lk-rgb-byte;
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lcm-params-dsi-lk-horizontal-sync-active-word-count;
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lcm-params-dsi-lk-horizontal-backporch-word-count;
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lcm-params-dsi-lk-horizontal-frontporch-word-count;
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lcm-params-dsi-lk-pll-select;
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lcm-params-dsi-lk-pll-div;
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lcm-params-dsi-lk-fbk-div;
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lcm-params-dsi-lk-fbk-sel;
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lcm-params-dsi-lk-rg = <0 0 0>;
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lcm-params-dsi-lk-dsi-clock;
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lcm-params-dsi-lk-ssc-disable = <0>;
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lcm-params-dsi-lk-ssc-range;
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lcm-params-dsi-lk-compatibility-for-nvk;
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lcm-params-dsi-lk-cont-clock;
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lcm-params-dsi-lk-ufoe-enable;
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lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
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lcm-params-dsi-lk-edp-panel;
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lcm-params-dsi-lk-lcm-int-te-monitor;
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lcm-params-dsi-lk-lcm-int-te-period;
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lcm-params-dsi-lk-lcm-ext-te-monitor;
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lcm-params-dsi-lk-lcm-ext-te-period;
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lcm-params-dsi-lk-noncont-clock;
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lcm-params-dsi-lk-noncont-clock-period;
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lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
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lcm-params-dsi-lk-dual-dsi-type;
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lcm-params-dsi-lk-mixmode-enable;
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lcm-params-dsi-lk-mixmode-mipi-clock;
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lcm-params-dsi-lk-pwm-fps;
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lcm-params-dsi-lk-pll-clock-lp;
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lcm-params-dsi-lk-ulps-sw-enable;
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lcm-params-dsi-lk-null-packet-en;
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lcm-params-dsi-lk-vact-fps = <120>;
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lcm-params-dsi-lk-send-frame-enable;
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lcm-params-dsi-lk-lfr-enable;
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lcm-params-dsi-lk-lfr-mode;
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lcm-params-dsi-lk-lfr-type;
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lcm-params-dsi-lk-lfr-skip-num;
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lcm-params-dsi-lk-ext-te-edge;
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lcm-params-dsi-lk-eint-disable;
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lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
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};
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lcm-params-dsi-dsc-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dsc-params";
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lcm-params-dsi-dsc-enable = <1>;
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lcm-params-dsi-dsc-enable-lk = <1>;
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lcm-params-dsi-dsc-ver = <17>;
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lcm-params-dsi-dsc-slice-mode = <1>;
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lcm-params-dsi-dsc-rgb-swap = <0>;
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lcm-params-dsi-dsc-cfg = <34>;
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lcm-params-dsi-dsc-rct-on = <1>;
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lcm-params-dsi-dsc-bit-per-channel = <8>;
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lcm-params-dsi-dsc-line-buf-depth = <9>;
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lcm-params-dsi-dsc-bp-enable = <1>;
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lcm-params-dsi-dsc-bit-per-pixel = <128>;
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lcm-params-dsi-dsc-pic-height = <2400>;
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lcm-params-dsi-dsc-pic-width = <1080>;
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lcm-params-dsi-dsc-slice-height = <8>;
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lcm-params-dsi-dsc-slice-width = <540>;
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lcm-params-dsi-dsc-chunk-size = <540>;
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lcm-params-dsi-dsc-xmit-delay = <170>;
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lcm-params-dsi-dsc-dec-delay = <526>;
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lcm-params-dsi-dsc-scale-value = <32>;
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lcm-params-dsi-dsc-increment-interval = <43>;
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lcm-params-dsi-dsc-decrement-interval = <7>;
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lcm-params-dsi-dsc-line-bpg-offset = <12>;
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lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
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lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
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lcm-params-dsi-dsc-initial-offset = <6144>;
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lcm-params-dsi-dsc-final-offset = <7072>;
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lcm-params-dsi-dsc-flatness-minqp = <3>;
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lcm-params-dsi-dsc-flatness-maxqp = <12>;
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lcm-params-dsi-dsc-rc-model-size = <8192>;
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lcm-params-dsi-dsc-rc-edge-factor = <6>;
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lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
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lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
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lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
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lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
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};
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lcm-params-dsi-phy-timcon-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-phy-timcon";
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lcm-params-dsi-phy-timcon-hs-trail;
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lcm-params-dsi-phy-timcon-hs-prpr;
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lcm-params-dsi-phy-timcon-hs-zero;
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lcm-params-dsi-phy-timcon-lpx;
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lcm-params-dsi-phy-timcon-ta-get;
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lcm-params-dsi-phy-timcon-ta-sure;
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lcm-params-dsi-phy-timcon-ta-go;
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lcm-params-dsi-phy-timcon-da-hs-exit;
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lcm-params-dsi-phy-timcon-clk-trail;
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lcm-params-dsi-phy-timcon-cont-det;
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lcm-params-dsi-phy-timcon-da-hs-sync;
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lcm-params-dsi-phy-timcon-clk-zero;
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lcm-params-dsi-phy-timcon-clk-prpr;
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lcm-params-dsi-phy-timcon-clk-exit;
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lcm-params-dsi-phy-timcon-clk-post;
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/* lk support */
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lcm-params-dsi-phy-timcon-lk-hs-trail;
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lcm-params-dsi-phy-timcon-lk-hs-zero;
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lcm-params-dsi-phy-timcon-lk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-lpx;
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lcm-params-dsi-phy-timcon-lk-ta-sack;
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lcm-params-dsi-phy-timcon-lk-ta-get;
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lcm-params-dsi-phy-timcon-lk-ta-sure;
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lcm-params-dsi-phy-timcon-lk-ta-go;
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lcm-params-dsi-phy-timcon-lk-clk-trail;
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lcm-params-dsi-phy-timcon-lk-clk-zero;
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lcm-params-dsi-phy-timcon-lk-lpx-wait;
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lcm-params-dsi-phy-timcon-lk-cont-det;
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lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-clk-hs-post;
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lcm-params-dsi-phy-timcon-lk-da-hs-exit;
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lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
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};
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lcm-params-dsi-dyn-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn";
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lcm-params-dsi-dyn-switch-en = <1>;
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lcm-params-dsi-dyn-pll-clk = <552>;
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lcm-params-dsi-dyn-data-rate;
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lcm-params-dsi-dyn-vsa;
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lcm-params-dsi-dyn-vbp;
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lcm-params-dsi-dyn-vfp;
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lcm-params-dsi-dyn-vfp-lp-dyn;
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lcm-params-dsi-dyn-vac;
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lcm-params-dsi-dyn-hsa;
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lcm-params-dsi-dyn-hbp;
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lcm-params-dsi-dyn-hfp;
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lcm-params-dsi-dyn-hac;
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lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
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};
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lcm-params-dsi-dyn-fps-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn-fps";
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lcm-params-dsi-dyn-fps-switch-en = <0>;
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lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
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lcm-params-dsi-dyn-fps-data-rate;
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lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
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[00 02 FF 25];
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lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
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[00 02 FB 01];
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lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
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[00 02 18 21];
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lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
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[00 02 FF 10];
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lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
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[00 02 FB 01];
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lcm-params-dsi-dyn-fps-dfps-cmd-table5;
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lcm-params-dsi-dyn-fps-dfps-cmd-table6;
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lcm-params-dsi-dyn-fps-dfps-cmd-table7;
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lcm-params-dsi-dyn-fps-dfps-cmd-table8;
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lcm-params-dsi-dyn-fps-dfps-cmd-table9;
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lcm-params-dsi-dyn-fps-dfps-cmd-table10;
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lcm-params-dsi-dyn-fps-dfps-cmd-table11;
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lcm-params-dsi-dyn-fps-dfps-cmd-table12;
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lcm-params-dsi-dyn-fps-dfps-cmd-table13;
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lcm-params-dsi-dyn-fps-dfps-cmd-table14;
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lcm-params-dsi-dyn-fps-dfps-cmd-table15;
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lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-1-1080-2400-90 {
|
|
compatible = "mediatek,lcm-dsi-fps-1-1080-2400-90";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <90>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <878>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <370431>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <551>;
|
|
lcm-params-dsi-data-rate = <1102>;
|
|
lcm-params-dsi-vfp-for-low-power = <2528>;
|
|
lcm-params-dsi-ssc-enable = <1>;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <0>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en = <1>;
|
|
lcm-params-dsi-lane-swap0 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
lcm-params-dsi-lane-swap1 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <0>;
|
|
|
|
lcm-params-dsi-dsc-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <552>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 FF 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 20];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 FF 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-2-1080-2400-120 {
|
|
compatible = "mediatek,lcm-dsi-fps-2-1080-2400-120";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <120>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <60>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <370506>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <551>;
|
|
lcm-params-dsi-data-rate = <1102>;
|
|
lcm-params-dsi-vfp-for-low-power = <2528>;
|
|
lcm-params-dsi-ssc-enable = <1>;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <0>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en = <1>;
|
|
lcm-params-dsi-lane-swap0 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
lcm-params-dsi-lane-swap1 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <0>;
|
|
|
|
lcm-params-dsi-dsc-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <552>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 FF 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 22];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 FF 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-3-1080-2400-30 {
|
|
compatible = "mediatek,lcm-dsi-fps-3-1080-2400-30";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <1>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <30>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <60>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <92626>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <551>;
|
|
lcm-params-dsi-data-rate = <1102>;
|
|
lcm-params-dsi-vfp-for-low-power = <2528>;
|
|
lcm-params-dsi-ssc-enable = <1>;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <0>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en = <1>;
|
|
lcm-params-dsi-lane-swap0 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
lcm-params-dsi-lane-swap1 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <4>;
|
|
|
|
lcm-params-dsi-dsc-params-3-1080-2400-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-3-1080-2400-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-3-1080-2400-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <552>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-3-1080-2400-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 FF 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 22];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 FF 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-4-1080-2400-24 {
|
|
compatible = "mediatek,lcm-dsi-fps-4-1080-2400-24";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <1>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <24>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <60>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <74101>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <551>;
|
|
lcm-params-dsi-data-rate = <1102>;
|
|
lcm-params-dsi-vfp-for-low-power = <2528>;
|
|
lcm-params-dsi-ssc-enable = <1>;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <0>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en = <1>;
|
|
lcm-params-dsi-lane-swap0 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
lcm-params-dsi-lane-swap1 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <5>;
|
|
|
|
lcm-params-dsi-dsc-params-4-1080-2400-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-4-1080-2400-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-4-1080-2400-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <552>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-4-1080-2400-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 FF 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 22];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 FF 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-5-1080-2400-10 {
|
|
compatible = "mediatek,lcm-dsi-fps-5-1080-2400-10";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <1>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <10>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <60>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <30875>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <551>;
|
|
lcm-params-dsi-data-rate = <1102>;
|
|
lcm-params-dsi-vfp-for-low-power = <2528>;
|
|
lcm-params-dsi-ssc-enable = <1>;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <0>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en = <1>;
|
|
lcm-params-dsi-lane-swap0 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
lcm-params-dsi-lane-swap1 =
|
|
<LCM_LANE_0 LCM_LANE_1 LCM_LANE_3 LCM_LANE_2>,
|
|
<LCM_LANE_CK LCM_LANE_0>;
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <12>;
|
|
|
|
lcm-params-dsi-dsc-params-5-1080-2400-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-5-1080-2400-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-5-1080-2400-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <552>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-5-1080-2400-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 FF 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 22];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 FF 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 FB 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
dbi-flag-length = <0>;
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
dpi-flag-length = <0>;
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
|
|
dsi-flag-length = <1>;
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C0 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[C1 89 28 00 08 00 AA 02 0E 00],
|
|
[2B 00 07 0D B7 0C B7],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 00 C2 1B A0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E9 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 01 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 06 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 07 38],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1B 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2F 83],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 69 91],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 95 D1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 96 D1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F2 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F3 64],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F4 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F5 64],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F6 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F7 64],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F8 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F9 64],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 89 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8A 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8D 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8E 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8F 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 91 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 00 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 04 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 05 2d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 06 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 07 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 08 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 09 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 11 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 12 95],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 15 68],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 16 0B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 30 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 31 F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 32 EB],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 33 E5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 34 DD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 DA],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 36 D5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 37 D0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 38 CE],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 39 CD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3A CD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3B CD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3D CB],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3F CB],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 40 C6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 41 BF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 45 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 46 F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 47 E8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 48 CE],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 49 BC],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4A B8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4B B5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4C B0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4D A8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4E A0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4F 9B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 50 98],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 51 98],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 52 88],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 7F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 58 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 59 F6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5A ED],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5B E6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5C DF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5D D8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5E D3],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5F CE],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 60 C9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 61 C4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 62 C1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 63 BE],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 64 BB],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 65 B8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 66 B6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 67 B5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 24],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 01 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 03 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 05 1D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 08 2F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 09 2E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0A 2D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0B 2C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 11 17],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 12 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 13 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 15 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 16 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 17 18],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1B 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1D 1D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 20 2F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 21 2E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 22 2D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 23 2C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 29 17],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2A 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2B 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2F 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 30 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 31 18],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 32 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 34 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 36 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 37 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4D 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4E 45],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4F 45],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 45],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 71 30],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 79 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7A 82],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7B 94],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7D 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 80 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 81 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 82 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 84 31],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 85 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 86 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 87 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 90 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 92 31],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 93 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 94 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 95 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9C F4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A0 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A2 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A3 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A4 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A5 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C6 C0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C9 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 D9 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E9 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 19 E4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 21 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 66 D8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 68 50],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 69 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6B 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6D 0D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6E 48],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 72 41],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 73 4A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 74 D0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 77 62],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 79 7F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7D 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7E 1D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 80 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 84 0D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 CF 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 D6 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 D7 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 EF 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F0 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 26],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 15 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 81 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 83 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 84 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 85 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 86 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 87 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 88 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8A 1A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8B 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8C 24],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8E 42],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8F 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 90 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 91 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9A 81],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9B 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9C 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9E 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 27],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 01 60],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 20 81],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 21 E7],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 25 82],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 26 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6E 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 70 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 71 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 72 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 75 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 76 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 77 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7D 09],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7E 5F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 80 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 82 09],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 83 5F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 88 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 89 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A5 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A6 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A7 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B6 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E3 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E4 DA],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E5 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E6 6D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E9 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 EA 2F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 EB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 EC 98],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 2A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 00 91],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 03 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 07 52],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0A 70],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0D 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0E 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 11 F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 15 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 16 B6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 19 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1A 8A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1B 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1D 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1E 4F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1F 4F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 20 4F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 28 EC],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 29 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2A 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2D 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2F 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 30 4A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 33 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 34 EE],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 30],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 36 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 37 E9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 38 34],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 39 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3A 4A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 46 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 47 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4A F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4E 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4F 9B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 52 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 6F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 56 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 57 7E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 58 7E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 59 7E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 60 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 61 C7],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 62 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 63 F3],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 64 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 65 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 66 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 67 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 68 8A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6A 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6B C9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6C 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6D E3],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6E C6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6F 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 70 E1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 71 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7A 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7B 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7D 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7F 2C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 83 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 84 12],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 87 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 88 E6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 89 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8B 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8C 3A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8D 3C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8E 3A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 95 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 96 FD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 97 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 98 32],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 99 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9A 08],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9B 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9C 4C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D B1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9F 75],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A0 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A2 42],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A3 6F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A4 F9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A5 47],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A6 6A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A7 4C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 2C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 01 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 02 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 03 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 04 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 05 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0D 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 0E 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 16 1B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 17 4B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 4B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 19 4B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2A 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4D 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4E 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4F 2E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 55 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 56 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 58 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 59 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 61 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 62 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6A 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6B 34],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6C 34],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6D 34],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7E 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9E 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B0 00 00 00 1F 00 49 00 6B 00],
|
|
[85 00 9C 00 B1 00 C4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B1 00 D1 01 07 01 30 01 6E 01],
|
|
[9E 01 E5 02 1E 02 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B2 02 56 02 96 02 BF 02 F4 03],
|
|
[16 03 41 03 51 03 5F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[B3 03 6E 03 82 03 98 03 AC 03],
|
|
[CC 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B4 00 00 00 1E 00 49 00 69 00],
|
|
[84 00 9B 00 AF 00 C1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B5 00 D2 01 07 01 30 01 6E 01],
|
|
[9D 01 E5 02 1F 02 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B6 02 57 02 96 02 BF 02 F3 03],
|
|
[16 03 3F 03 4F 03 5D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[B7 03 6D 03 81 03 98 03 AC 03],
|
|
[CC 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B8 00 00 00 20 00 48 00 6A 00],
|
|
[86 00 9F 00 B5 00 C6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B9 00 D8 01 0D 01 36 01 73 01],
|
|
[A1 01 E8 02 21 02 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[BA 02 58 02 98 02 C1 02 F7 03],
|
|
[1B 03 41 03 54 03 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[BB 03 6E 03 82 03 98 03 AC 03],
|
|
[D0 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B0 00 00 00 1F 00 49 00 6B 00],
|
|
[85 00 9C 00 B1 00 C4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B1 00 D1 01 07 01 30 01 6E 01],
|
|
[9E 01 E5 02 1E 02 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B2 02 56 02 96 02 BF 02 F4 03],
|
|
[16 03 41 03 51 03 5F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[B3 03 6E 03 82 03 98 03 AC 03],
|
|
[CC 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B4 00 00 00 1E 00 49 00 69 00],
|
|
[84 00 9B 00 AF 00 C1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B5 00 D2 01 07 01 30 01 6E 01],
|
|
[9D 01 E5 02 1F 02 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B6 02 57 02 96 02 BF 02 F3 03],
|
|
[16 03 3F 03 4F 03 5D],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[B7 03 6D 03 81 03 98 03 AC 03],
|
|
[CC 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B8 00 00 00 20 00 48 00 6A 00],
|
|
[86 00 9F 00 B5 00 C6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[B9 00 D8 01 0D 01 36 01 73 01],
|
|
[A1 01 E8 02 21 02 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00],
|
|
[BA 02 58 02 98 02 C1 02 F7 03],
|
|
[1B 03 41 03 54 03 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00],
|
|
[BB 03 6E 03 82 03 98 03 AC 03],
|
|
[D0 03 D8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 2B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B7 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B8 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C0 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF E0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 82],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1C 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 33 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF D0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF C0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9C 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 51 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 55 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 11],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 07 00],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
|
|
[02 51 FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 10],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table =
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
lcm-update-table;
|
|
|
|
set-backlight-mask = <0xff>;
|
|
set-backlight-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 07 00],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
|
|
[02 51 FF],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0xff>;
|
|
set-aod-light-table;
|
|
|
|
ata-id-value-data = [00 80 00];
|
|
ata-check-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_CMD 04 00 00 03 04],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
compare-id-value-data = [6E];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 20],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 3B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table;
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table;
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
fps-switch-0-1080-2400-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1080-2400-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2400-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
fps-switch-0-1080-2400-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1080-2400-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2400-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|