// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause /* * Device Tree defines for LCM settings * Copyright (c) 2021 MediaTek Inc. */ #include "mtk_lcm_settings.h" &pio { nt36672e_fhdp_dphy_vdo_jdi_120hz: nt36672e-fhdp-dphy-vdo-jdi-120hz { compatible = "mediatek,nt36672e_fhdp_dphy_vdo_jdi_120hz"; lcm-version = <0>; lcm-params{ compatible = "mediatek,lcm-params"; lcm-params-name = "nt36672e-fhdp-dphy-vdo-jdi-120hz"; lcm-params-types = ; lcm-params-resolution = <1080 2400>; lcm-params-physical-width = <70>; lcm-params-physical-height = <152>; /* lk support */ lcm-params-lk { compatible = "mediatek,lcm-params-lk"; lcm-params-lk-ctrl; lcm-params-lk-lcm-if; lcm-params-lk-lcm-cmd-if; lcm-params-lk-io-select-mode; lcm-params-lk-lcm-x; lcm-params-lk-lcm-y; lcm-params-lk-virtual-resolution = <0 0>; lcm-params-lk-od-table-size; lcm-params-lk-od-table; }; lcm-params-lk-round-corner { compatible = "mediatek,lcm-params-lk-round-corner"; lcm-params-lk-rc-round-corner-en = <0>; lcm-params-lk-rc-is-notch; lcm-params-lk-rc-full-content = <0>; lcm-params-lk-rc-width; lcm-params-lk-rc-height; lcm-params-lk-rc-width-bot; lcm-params-lk-rc-height-bot; lcm-params-lk-rc-top-size; lcm-params-lk-rc-top-size-left; lcm-params-lk-rc-top-size-right; lcm-params-lk-rc-bottom-size; lcm-params-lk-rc-pattern-name; }; lcm-params-dbi { compatible = "mediatek,lcm-params-dbi"; /* future reserved for dbi interfaces */ }; lcm-params-dpi { compatible = "mediatek,lcm-params-dpi"; /* future reserved for dpi interfaces */ }; lcm-params-dsi { compatible = "mediatek,lcm-params-dsi"; lcm-params-dsi-density = <480>; lcm-params-dsi-lanes = <4>; lcm-params-dsi-format = ; lcm-params-dsi-phy-type = ; lcm-params-dsi-mode-flags = , , , , ; lcm-params-dsi-mode-flags-doze-on; lcm-params-dsi-mode-flags-doze-off; lcm-params-dsi-need-fake-resolution; lcm-params-dsi-fake-resolution = <1080 2400>; lcm-gpio-list = <&pio 42 0>, /* gpio list*/ <&pio 28 0>, <&pio 29 0>; pinctrl-names = "gpio1", "gpio2", "gpio3"; pinctrl-0; pinctrl-1; pinctrl-2; status = "okay"; lcm-params-dsi-default-mode = <0>; lcm-params-dsi-mode-count = <6>; lcm-params-dsi-mode-list = <0 1080 2400 60>, <1 1080 2400 90>, <2 1080 2400 120>, <3 1080 2400 30>, <4 1080 2400 24>, <5 1080 2400 10>; lcm-params-dsi-fps-0-1080-2400-60 { compatible = "mediatek,lcm-dsi-fps-0-1080-2400-60"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <0>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <60>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <2528>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <370506>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <4180>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <0>; /* fpga support */ lcm-params-dsi-fpga-params-0-1080-2400-60 { compatible = "mediatek,lcm-dsi-fpga-params"; lcm-params-dsi-lk-pll-div = <0 0>; lcm-params-dsi-lk-fbk-div = <1>; }; /* lk support */ lcm-params-dsi-lk-params-0-1080-2400-60 { compatible = "mediatek,lcm-dsi-lk-params"; lcm-params-dsi-lk-mode = ; lcm-params-dsi-lk-switch-mode = ; lcm-params-dsi-lk-switch-mode-enable = <0>; lcm-params-dsi-lk-dsi-wmem-conti; lcm-params-dsi-lk-dsi-rmem-conti; lcm-params-dsi-lk-vc-num; lcm-params-dsi-lk-data-format = , , , ; lcm-params-dsi-lk-intermediat-buffer-num; lcm-params-dsi-lk-ps = ; lcm-params-dsi-lk-word-count; lcm-params-dsi-lk-packet-size = <256>; lcm-params-dsi-lk-horizontal-blanking-pixel; lcm-params-dsi-lk-bllp; lcm-params-dsi-lk-line-byte; lcm-params-dsi-lk-horizontal-sync-active-byte; lcm-params-dsi-lk-horizontal-backporch-byte; lcm-params-dsi-lk-horizontal-frontporch-byte; lcm-params-dsi-lk-rgb-byte; lcm-params-dsi-lk-horizontal-sync-active-word-count; lcm-params-dsi-lk-horizontal-backporch-word-count; lcm-params-dsi-lk-horizontal-frontporch-word-count; lcm-params-dsi-lk-pll-select; lcm-params-dsi-lk-pll-div; lcm-params-dsi-lk-fbk-div; lcm-params-dsi-lk-fbk-sel; lcm-params-dsi-lk-rg = <0 0 0>; lcm-params-dsi-lk-dsi-clock; lcm-params-dsi-lk-ssc-disable = <0>; lcm-params-dsi-lk-ssc-range; lcm-params-dsi-lk-compatibility-for-nvk; lcm-params-dsi-lk-cont-clock; lcm-params-dsi-lk-ufoe-enable; lcm-params-dsi-lk-ufoe-params = <0 0 0 0>; lcm-params-dsi-lk-edp-panel; lcm-params-dsi-lk-lcm-int-te-monitor; lcm-params-dsi-lk-lcm-int-te-period; lcm-params-dsi-lk-lcm-ext-te-monitor; lcm-params-dsi-lk-lcm-ext-te-period; lcm-params-dsi-lk-noncont-clock; lcm-params-dsi-lk-noncont-clock-period; lcm-params-dsi-lk-clk-lp-per-line-enable = <0>; lcm-params-dsi-lk-dual-dsi-type; lcm-params-dsi-lk-mixmode-enable; lcm-params-dsi-lk-mixmode-mipi-clock; lcm-params-dsi-lk-pwm-fps; lcm-params-dsi-lk-pll-clock-lp; lcm-params-dsi-lk-ulps-sw-enable; lcm-params-dsi-lk-null-packet-en; lcm-params-dsi-lk-vact-fps = <120>; lcm-params-dsi-lk-send-frame-enable; lcm-params-dsi-lk-lfr-enable; lcm-params-dsi-lk-lfr-mode; lcm-params-dsi-lk-lfr-type; lcm-params-dsi-lk-lfr-skip-num; lcm-params-dsi-lk-ext-te-edge; lcm-params-dsi-lk-eint-disable; lcm-params-dsi-lk-phy-sel = <0 0 0 0>; }; lcm-params-dsi-dsc-params-0-1080-2400-60 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <1>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-0-1080-2400-60 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; /* lk support */ lcm-params-dsi-phy-timcon-lk-hs-trail; lcm-params-dsi-phy-timcon-lk-hs-zero; lcm-params-dsi-phy-timcon-lk-hs-prpr; lcm-params-dsi-phy-timcon-lk-lpx; lcm-params-dsi-phy-timcon-lk-ta-sack; lcm-params-dsi-phy-timcon-lk-ta-get; lcm-params-dsi-phy-timcon-lk-ta-sure; lcm-params-dsi-phy-timcon-lk-ta-go; lcm-params-dsi-phy-timcon-lk-clk-trail; lcm-params-dsi-phy-timcon-lk-clk-zero; lcm-params-dsi-phy-timcon-lk-lpx-wait; lcm-params-dsi-phy-timcon-lk-cont-det; lcm-params-dsi-phy-timcon-lk-clk-hs-prpr; lcm-params-dsi-phy-timcon-lk-clk-hs-post; lcm-params-dsi-phy-timcon-lk-da-hs-exit; lcm-params-dsi-phy-timcon-lk-clk-hs-exit; }; lcm-params-dsi-dyn-params-0-1080-2400-60 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-0-1080-2400-60 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 21]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; lcm-params-dsi-fps-1-1080-2400-90 { compatible = "mediatek,lcm-dsi-fps-1-1080-2400-90"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <0>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <90>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <878>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <370431>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <2528>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <0>; lcm-params-dsi-dsc-params-1-1080-2400-90 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <0>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-1-1080-2400-90 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; }; lcm-params-dsi-dyn-params-1-1080-2400-90 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-1-1080-2400-90 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 20]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; lcm-params-dsi-fps-2-1080-2400-120 { compatible = "mediatek,lcm-dsi-fps-2-1080-2400-120"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <0>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <120>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <60>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <370506>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <2528>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <0>; lcm-params-dsi-dsc-params-2-1080-2400-120 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <0>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-2-1080-2400-120 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; }; lcm-params-dsi-dyn-params-2-1080-2400-120 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-2-1080-2400-120 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 22]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; lcm-params-dsi-fps-3-1080-2400-30 { compatible = "mediatek,lcm-dsi-fps-3-1080-2400-30"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <1>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <30>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <60>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <92626>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <2528>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <4>; lcm-params-dsi-dsc-params-3-1080-2400-30 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <0>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-3-1080-2400-30 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; /* lk support */ lcm-params-dsi-phy-timcon-lk-hs-trail; lcm-params-dsi-phy-timcon-lk-hs-zero; lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>; lcm-params-dsi-phy-timcon-lk-lpx; lcm-params-dsi-phy-timcon-lk-ta-sack; lcm-params-dsi-phy-timcon-lk-ta-get; lcm-params-dsi-phy-timcon-lk-ta-sure; lcm-params-dsi-phy-timcon-lk-ta-go; lcm-params-dsi-phy-timcon-lk-clk-trail; lcm-params-dsi-phy-timcon-lk-clk-zero; lcm-params-dsi-phy-timcon-lk-lpx-wait; lcm-params-dsi-phy-timcon-lk-cont-det; lcm-params-dsi-phy-timcon-lk-clk-hs-prpr; lcm-params-dsi-phy-timcon-lk-clk-hs-post; lcm-params-dsi-phy-timcon-lk-da-hs-exit; lcm-params-dsi-phy-timcon-lk-clk-hs-exit; }; lcm-params-dsi-dyn-params-3-1080-2400-30 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-3-1080-2400-30 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 22]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; lcm-params-dsi-fps-4-1080-2400-24 { compatible = "mediatek,lcm-dsi-fps-4-1080-2400-24"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <1>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <24>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <60>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <74101>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <2528>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <5>; lcm-params-dsi-dsc-params-4-1080-2400-24 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <0>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-4-1080-2400-24 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; /* lk support */ lcm-params-dsi-phy-timcon-lk-hs-trail; lcm-params-dsi-phy-timcon-lk-hs-zero; lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>; lcm-params-dsi-phy-timcon-lk-lpx; lcm-params-dsi-phy-timcon-lk-ta-sack; lcm-params-dsi-phy-timcon-lk-ta-get; lcm-params-dsi-phy-timcon-lk-ta-sure; lcm-params-dsi-phy-timcon-lk-ta-go; lcm-params-dsi-phy-timcon-lk-clk-trail; lcm-params-dsi-phy-timcon-lk-clk-zero; lcm-params-dsi-phy-timcon-lk-lpx-wait; lcm-params-dsi-phy-timcon-lk-cont-det; lcm-params-dsi-phy-timcon-lk-clk-hs-prpr; lcm-params-dsi-phy-timcon-lk-clk-hs-post; lcm-params-dsi-phy-timcon-lk-da-hs-exit; lcm-params-dsi-phy-timcon-lk-clk-hs-exit; }; lcm-params-dsi-dyn-params-4-1080-2400-24 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-4-1080-2400-24 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 22]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; lcm-params-dsi-fps-5-1080-2400-10 { compatible = "mediatek,lcm-dsi-fps-5-1080-2400-10"; lcm-params-dsi-voltage; lcm-params-dsi-fake = <1>; /* drm-display-mode */ lcm-params-dsi-vrefresh = <10>; lcm-params-dsi-vertical-sync-active = <10>; lcm-params-dsi-vertical-backporch = <10>; lcm-params-dsi-vertical-frontporch = <60>; lcm-params-dsi-vertical-active-line = <2400>; lcm-params-dsi-horizontal-sync-active = <12>; lcm-params-dsi-horizontal-backporch = <80>; lcm-params-dsi-horizontal-frontporch = <76>; lcm-params-dsi-horizontal-active-pixel = <1080>; lcm-params-dsi-pixel-clock = <30875>; lcm-params-dsi-hskew; lcm-params-dsi-vscan; /* mtk-panel-params */ lcm-params-dsi-pll-clock = <551>; lcm-params-dsi-data-rate = <1102>; lcm-params-dsi-vfp-for-low-power = <2528>; lcm-params-dsi-ssc-enable = <1>; lcm-params-dsi-ssc-range; lcm-params-dsi-lcm-color-mode; lcm-params-dsi-min-luminance; lcm-params-dsi-average-luminance; lcm-params-dsi-max-luminance; lcm-params-dsi-round-corner-en = <0>; lcm-params-dsi-corner-pattern-height; lcm-params-dsi-corner-pattern-height-bot; lcm-params-dsi-corner-pattern-tp-size; lcm-params-dsi-corner-pattern-tp-size-left; lcm-params-dsi-corner-pattern-tp-size-right; lcm-params-dsi-corner-pattern-name; lcm-params-dsi-physical-width-um; lcm-params-dsi-physical-height-um; lcm-params-dsi-output-mode = ; lcm-params-dsi-lcm-cmd-if; lcm-params-dsi-hbm-en-time; lcm-params-dsi-hbm-dis-time; lcm-params-dsi-lcm-index; lcm-params-dsi-wait-sof-before-dec-vfp; lcm-params-dsi-doze-delay; lcm-params-dsi-lfr-enable = <0>; lcm-params-dsi-lfr-minimum-fps = <60>; lcm-params-dsi-msync2-enable; lcm-params-dsi-max-vfp-for-msync; /* lane swap */ lcm-params-dsi-lane-swap-en = <1>; lcm-params-dsi-lane-swap0 = , ; lcm-params-dsi-lane-swap1 = , ; /* esd check table */ lcm-params-dsi-cust-esd-check = <1>; lcm-params-dsi-esd-check-enable = <1>; lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C]; lcm-params-dsi-lcm-esd-check-table1; lcm-params-dsi-lcm-esd-check-table2; /* Msync 3.0 */ lcm-params-dsi-skip-vblank = <12>; lcm-params-dsi-dsc-params-5-1080-2400-10 { compatible = "mediatek,lcm-params-dsi-dsc-params"; lcm-params-dsi-dsc-enable = <1>; lcm-params-dsi-dsc-enable-lk = <0>; lcm-params-dsi-dsc-ver = <17>; lcm-params-dsi-dsc-slice-mode = <1>; lcm-params-dsi-dsc-rgb-swap = <0>; lcm-params-dsi-dsc-cfg = <34>; lcm-params-dsi-dsc-rct-on = <1>; lcm-params-dsi-dsc-bit-per-channel = <8>; lcm-params-dsi-dsc-line-buf-depth = <9>; lcm-params-dsi-dsc-bp-enable = <1>; lcm-params-dsi-dsc-bit-per-pixel = <128>; lcm-params-dsi-dsc-pic-height = <2400>; lcm-params-dsi-dsc-pic-width = <1080>; lcm-params-dsi-dsc-slice-height = <8>; lcm-params-dsi-dsc-slice-width = <540>; lcm-params-dsi-dsc-chunk-size = <540>; lcm-params-dsi-dsc-xmit-delay = <170>; lcm-params-dsi-dsc-dec-delay = <526>; lcm-params-dsi-dsc-scale-value = <32>; lcm-params-dsi-dsc-increment-interval = <43>; lcm-params-dsi-dsc-decrement-interval = <7>; lcm-params-dsi-dsc-line-bpg-offset = <12>; lcm-params-dsi-dsc-nfl-bpg-offset = <3511>; lcm-params-dsi-dsc-slice-bpg-offset = <3255>; lcm-params-dsi-dsc-initial-offset = <6144>; lcm-params-dsi-dsc-final-offset = <7072>; lcm-params-dsi-dsc-flatness-minqp = <3>; lcm-params-dsi-dsc-flatness-maxqp = <12>; lcm-params-dsi-dsc-rc-model-size = <8192>; lcm-params-dsi-dsc-rc-edge-factor = <6>; lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>; lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>; lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>; lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>; }; lcm-params-dsi-phy-timcon-params-5-1080-2400-10 { compatible = "mediatek,lcm-params-dsi-phy-timcon"; lcm-params-dsi-phy-timcon-hs-trail; lcm-params-dsi-phy-timcon-hs-prpr; lcm-params-dsi-phy-timcon-hs-zero; lcm-params-dsi-phy-timcon-lpx; lcm-params-dsi-phy-timcon-ta-get; lcm-params-dsi-phy-timcon-ta-sure; lcm-params-dsi-phy-timcon-ta-go; lcm-params-dsi-phy-timcon-da-hs-exit; lcm-params-dsi-phy-timcon-clk-trail; lcm-params-dsi-phy-timcon-cont-det; lcm-params-dsi-phy-timcon-da-hs-sync; lcm-params-dsi-phy-timcon-clk-zero; lcm-params-dsi-phy-timcon-clk-prpr; lcm-params-dsi-phy-timcon-clk-exit; lcm-params-dsi-phy-timcon-clk-post; /* lk support */ lcm-params-dsi-phy-timcon-lk-hs-trail; lcm-params-dsi-phy-timcon-lk-hs-zero; lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>; lcm-params-dsi-phy-timcon-lk-lpx; lcm-params-dsi-phy-timcon-lk-ta-sack; lcm-params-dsi-phy-timcon-lk-ta-get; lcm-params-dsi-phy-timcon-lk-ta-sure; lcm-params-dsi-phy-timcon-lk-ta-go; lcm-params-dsi-phy-timcon-lk-clk-trail; lcm-params-dsi-phy-timcon-lk-clk-zero; lcm-params-dsi-phy-timcon-lk-lpx-wait; lcm-params-dsi-phy-timcon-lk-cont-det; lcm-params-dsi-phy-timcon-lk-clk-hs-prpr; lcm-params-dsi-phy-timcon-lk-clk-hs-post; lcm-params-dsi-phy-timcon-lk-da-hs-exit; lcm-params-dsi-phy-timcon-lk-clk-hs-exit; }; lcm-params-dsi-dyn-params-5-1080-2400-10 { compatible = "mediatek,lcm-params-dsi-dyn"; lcm-params-dsi-dyn-switch-en = <1>; lcm-params-dsi-dyn-pll-clk = <552>; lcm-params-dsi-dyn-data-rate; lcm-params-dsi-dyn-vsa; lcm-params-dsi-dyn-vbp; lcm-params-dsi-dyn-vfp; lcm-params-dsi-dyn-vfp-lp-dyn; lcm-params-dsi-dyn-vac; lcm-params-dsi-dyn-hsa; lcm-params-dsi-dyn-hbp; lcm-params-dsi-dyn-hfp; lcm-params-dsi-dyn-hac; lcm-params-dsi-dyn-max-vfp-for-msync-dyn; }; lcm-params-dsi-dyn-fps-params-5-1080-2400-10 { compatible = "mediatek,lcm-params-dsi-dyn-fps"; lcm-params-dsi-dyn-fps-switch-en = <0>; lcm-params-dsi-dyn-fps-vact-timing-fps = <120>; lcm-params-dsi-dyn-fps-data-rate; lcm-params-dsi-dyn-fps-dfps-cmd-table0 = [00 02 FF 25]; lcm-params-dsi-dyn-fps-dfps-cmd-table1 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table2 = [00 02 18 22]; lcm-params-dsi-dyn-fps-dfps-cmd-table3 = [00 02 FF 10]; lcm-params-dsi-dyn-fps-dfps-cmd-table4 = [00 02 FB 01]; lcm-params-dsi-dyn-fps-dfps-cmd-table5; lcm-params-dsi-dyn-fps-dfps-cmd-table6; lcm-params-dsi-dyn-fps-dfps-cmd-table7; lcm-params-dsi-dyn-fps-dfps-cmd-table8; lcm-params-dsi-dyn-fps-dfps-cmd-table9; lcm-params-dsi-dyn-fps-dfps-cmd-table10; lcm-params-dsi-dyn-fps-dfps-cmd-table11; lcm-params-dsi-dyn-fps-dfps-cmd-table12; lcm-params-dsi-dyn-fps-dfps-cmd-table13; lcm-params-dsi-dyn-fps-dfps-cmd-table14; lcm-params-dsi-dyn-fps-dfps-cmd-table15; lcm-params-dsi-dyn-fps-dfps-cmd-table16; lcm-params-dsi-dyn-fps-dfps-cmd-table17; lcm-params-dsi-dyn-fps-dfps-cmd-table18; lcm-params-dsi-dyn-fps-dfps-cmd-table19; }; }; }; }; lcm-ops { compatible = "mediatek,lcm-ops"; lcm-ops-dbi { compatible = "mediatek,lcm-ops-dbi"; /* future reserved for dbi interfaces*/ dbi-flag-length = <0>; }; lcm-ops-dpi { compatible = "mediatek,lcm-ops-dpi"; /* future reserved for dpi interfaces*/ dpi-flag-length = <0>; }; lcm-ops-dsi { compatible = "mediatek,lcm-ops-dsi"; dsi-flag-length = <1>; prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f], [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14], [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B0 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C0 03], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [C1 89 28 00 08 00 AA 02 0E 00], [2B 00 07 0D B7 0C B7], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 00 C2 1B A0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 E9 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 01 66], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 06 40], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 07 38], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 66], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1B 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 2F 83], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 69 91], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 95 D1], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 96 D1], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F2 65], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F3 64], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F4 65], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F5 64], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F6 65], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F7 64], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F8 65], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 F9 64], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 89 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8A 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8D 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8E 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 8F 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 91 15], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 23], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 00 80], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 04 05], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 05 2d], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 06 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 07 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 08 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 09 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 11 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 12 95], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 15 68], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 16 0B], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 A0 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 30 FF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 31 F0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 32 EB], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 33 E5], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 34 DD], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 DA], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 36 D5], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 37 D0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 38 CE], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 39 CD], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3A CD], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3B CD], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3D CB], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 3F CB], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 40 C6], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 41 BF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 45 FF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 46 F0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 47 E8], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 48 CE], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 49 BC], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4A B8], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4B B5], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4C B0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4D A8], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4E A0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 4F 9B], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 50 98], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 51 98], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 52 88], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 80], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 7F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 58 FF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 59 F6], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5A ED], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5B E6], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5C DF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5D D8], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5E D3], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5F CE], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 60 C9], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 61 C4], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 62 C1], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 63 BE], 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[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 02], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 55 02], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 56 0E], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 58 0E], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 59 0E], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 61 1F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 62 1F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6A 14], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6B 34], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6C 34], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 6D 34], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 7E 03], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 0F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9E 03], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9F 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B0 00 00 00 1F 00 49 00 6B 00], [85 00 9C 00 B1 00 C4], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B1 00 D1 01 07 01 30 01 6E 01], [9E 01 E5 02 1E 02 1F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B2 02 56 02 96 02 BF 02 F4 03], [16 03 41 03 51 03 5F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [B3 03 6E 03 82 03 98 03 AC 03], [CC 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B4 00 00 00 1E 00 49 00 69 00], [84 00 9B 00 AF 00 C1], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B5 00 D2 01 07 01 30 01 6E 01], [9D 01 E5 02 1F 02 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B6 02 57 02 96 02 BF 02 F3 03], [16 03 3F 03 4F 03 5D], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [B7 03 6D 03 81 03 98 03 AC 03], [CC 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B8 00 00 00 20 00 48 00 6A 00], [86 00 9F 00 B5 00 C6], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B9 00 D8 01 0D 01 36 01 73 01], [A1 01 E8 02 21 02 22], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [BA 02 58 02 98 02 C1 02 F7 03], [1B 03 41 03 54 03 66], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [BB 03 6E 03 82 03 98 03 AC 03], [D0 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 21], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B0 00 00 00 1F 00 49 00 6B 00], [85 00 9C 00 B1 00 C4], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B1 00 D1 01 07 01 30 01 6E 01], [9E 01 E5 02 1E 02 1F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B2 02 56 02 96 02 BF 02 F4 03], [16 03 41 03 51 03 5F], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [B3 03 6E 03 82 03 98 03 AC 03], [CC 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B4 00 00 00 1E 00 49 00 69 00], [84 00 9B 00 AF 00 C1], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B5 00 D2 01 07 01 30 01 6E 01], [9D 01 E5 02 1F 02 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B6 02 57 02 96 02 BF 02 F3 03], [16 03 3F 03 4F 03 5D], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [B7 03 6D 03 81 03 98 03 AC 03], [CC 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B8 00 00 00 20 00 48 00 6A 00], [86 00 9F 00 B5 00 C6], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [B9 00 D8 01 0D 01 36 01 73 01], [A1 01 E8 02 21 02 22], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 12 00], [BA 02 58 02 98 02 C1 02 F7 03], [1B 03 41 03 54 03 66], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 10 00], [BB 03 6E 03 82 03 98 03 AC 03], [D0 03 D8 00 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 2B], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B7 06], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 B8 03], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 C0 03], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF E0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 82], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF F0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 5A 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 1C 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 33 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF D0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 22], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 54 02], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF C0], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9C 11], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 9D 11], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FF 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 FB 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 35 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 51 FF], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 53 0C], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 55 00], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 11], [MTK_LCM_PHASE_TYPE_HEX_START 02], [MTK_LCM_PHASE_HEX_LK], [MTK_LCM_PHASE_HEX_KERNEL], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 29], [MTK_LCM_PHASE_TYPE_HEX_END 02], [MTK_LCM_PHASE_HEX_LK], [MTK_LCM_PHASE_HEX_KERNEL], [MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 07 00], [MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01], [02 51 FF], [MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL], [MTK_LCM_TYPE_HEX_END]; unprepare-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 28], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 10], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8], [MTK_LCM_TYPE_HEX_END]; set-display-on-table = [MTK_LCM_PHASE_TYPE_HEX_START 02], [MTK_LCM_PHASE_HEX_LK], [MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY], [MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 78], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 29], [MTK_LCM_PHASE_TYPE_HEX_END 02], [MTK_LCM_PHASE_HEX_LK], [MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY], [MTK_LCM_TYPE_HEX_END]; lcm-update-table; set-backlight-mask = <0xff>; set-backlight-cmdq-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 07 00], [MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01], [02 51 FF], [MTK_LCM_TYPE_HEX_END]; set-aod-light-mask = <0xff>; set-aod-light-table; ata-id-value-data = [00 80 00]; ata-check-table = [MTK_LCM_CMD_TYPE_HEX_READ_CMD 04 00 00 03 04], [MTK_LCM_TYPE_HEX_END]; compare-id-value-data = [6E]; compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a], [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a], [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01], [MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 20], [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01], [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00], [MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00], [MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 3B], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10], [MTK_LCM_TYPE_HEX_END]; doze-enable-start-table; doze-enable-table; doze-disable-table; doze-area-table; doze-post-disp-on-table; hbm-set-cmdq-switch-id; hbm-set-cmdq-switch-on; hbm-set-cmdq-switch-off; hbm-set-cmdq-table; /* fps switch cmd for high frame rate feature */ lcm-ops-dsi-fps-switch-after-poweron { compatible = "mediatek,lcm-ops-dsi-fps-switch-after-poweron"; fps-switch-0-1080-2400-60-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 21], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; fps-switch-1-1080-2400-90-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; fps-switch-2-1080-2400-120-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 22], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; }; lcm-ops-dsi-fps-switch-before-powerdown { compatible = "mediatek,lcm-ops-dsi-fps-switch-before-powerdown"; fps-switch-0-1080-2400-60-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 21], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; fps-switch-1-1080-2400-90-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 20], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; fps-switch-2-1080-2400-120-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 25], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 18 22], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 ff 10], [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 00 fb 01], [MTK_LCM_TYPE_HEX_END]; }; }; }; }; };