98 lines
4.4 KiB
C
Executable file
98 lines
4.4 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0
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* aw87xxx_pid_59_3x9_reg.h
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*
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* Copyright (c) 2021 AWINIC Technology CO., LTD
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*
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* Author: Barry <zhaozhongbo@awinic.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __AW87XXX_PID_59_3X9_REG_H__
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#define __AW87XXX_PID_59_3X9_REG_H__
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#define AW87XXX_PID_59_3X9_REG_CHIPID (0x00)
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#define AW87XXX_PID_59_3X9_REG_SYSCTRL (0x01)
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#define AW87XXX_PID_59_3X9_REG_MDCRTL (0x02)
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#define AW87XXX_PID_59_3X9_REG_CPOVP (0x03)
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#define AW87XXX_PID_59_3X9_REG_CPP (0x04)
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#define AW87XXX_PID_59_3X9_REG_PAG (0x05)
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#define AW87XXX_PID_59_3X9_REG_AGC3PO (0x06)
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#define AW87XXX_PID_59_3X9_REG_AGC3PA (0x07)
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#define AW87XXX_PID_59_3X9_REG_AGC2PO (0x08)
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#define AW87XXX_PID_59_3X9_REG_AGC2PA (0x09)
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#define AW87XXX_PID_59_3X9_REG_AGC1PA (0x0A)
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#define AW87XXX_PID_59_3X9_REG_SYSST (0x59)
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#define AW87XXX_PID_59_3X9_REG_SYSINT (0x60)
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#define AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL (0x61)
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#define AW87XXX_PID_59_3X9_REG_DFT_MDCTRL (0x62)
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#define AW87XXX_PID_59_3X9_REG_DFT_CPOVP2 (0x63)
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#define AW87XXX_PID_59_3X9_REG_DFT_AGCPA (0x64)
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#define AW87XXX_PID_59_3X9_REG_DFT_POFR (0x65)
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#define AW87XXX_PID_59_3X9_REG_DFT_OC (0x66)
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#define AW87XXX_PID_59_3X9_REG_DFT_OTA (0x67)
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#define AW87XXX_PID_59_3X9_REG_DFT_REF (0x68)
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#define AW87XXX_PID_59_3X9_REG_DFT_LDO (0x69)
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#define AW87XXX_PID_59_3X9_REG_ENCR (0x70)
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#define AW87XXX_PID_59_3X9_ENCR_DEFAULT (0x00)
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/********************************************
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* soft control info
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* If you need to update this file, add this information manually
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*******************************************/
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unsigned char aw87xxx_pid_59_3x9_softrst_access[2] = {0x00, 0xaa};
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/********************************************
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* Register Access
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*******************************************/
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#define AW87XXX_PID_59_3X9_REG_MAX (0x71)
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#define REG_NONE_ACCESS (0)
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#define REG_RD_ACCESS (1 << 0)
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#define REG_WR_ACCESS (1 << 1)
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const unsigned char aw87xxx_pid_59_3x9_reg_access[AW87XXX_PID_59_3X9_REG_MAX] = {
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[AW87XXX_PID_59_3X9_REG_CHIPID] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_3X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_MDCRTL] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_CPOVP] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_CPP] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_PAG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_AGC3PO] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_AGC3PA] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_AGC2PO] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_AGC2PA] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_AGC1PA] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_SYSST] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_3X9_REG_SYSINT] = (REG_RD_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_MDCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_CPOVP2] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_AGCPA] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_POFR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_OC] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_OTA] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_REF] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_DFT_LDO] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_59_3X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS),
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};
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/* SPK_MODE bit 2 (MDCRTL 0x02) */
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#define AW87XXX_PID_59_3X9_SPK_MODE_START_BIT (2)
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#define AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN (1)
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#define AW87XXX_PID_59_3X9_SPK_MODE_MASK \
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(~(((1<<AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN)-1) << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT))
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#define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE (0)
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#define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE_VALUE \
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(AW87XXX_PID_59_3X9_SPK_MODE_DISABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT)
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#define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE (1)
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#define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE_VALUE \
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(AW87XXX_PID_59_3X9_SPK_MODE_ENABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT)
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#endif
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