610 lines
22 KiB
Text
610 lines
22 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
/*
|
|
* Device Tree defines for LCM settings
|
|
* Copyright (c) 2021 MediaTek Inc.
|
|
*/
|
|
|
|
#include "mtk_lcm_settings.h"
|
|
|
|
&pio {
|
|
ana6705_wqhd_dphy_cmd_samsung_120hz: ana6705-wqhd-dphy-cmd-samsung-120hz {
|
|
compatible = "mediatek,ana6705_wqhd_dphy_cmd_samsung_120hz";
|
|
lcm-version = <0>;
|
|
|
|
lcm-params{
|
|
compatible = "mediatek,lcm-params";
|
|
lcm-params-name = "ana6705-wqhd-dphy-cmd-samsung-120hz";
|
|
lcm-params-types = <MTK_LCM_FUNC_DSI>;
|
|
lcm-params-resolution = <1440 3216>;
|
|
lcm-params-physical-width = <67>;
|
|
lcm-params-physical-height = <149>;
|
|
|
|
/* lk support */
|
|
lcm-params-lk {
|
|
compatible = "mediatek,lcm-params-lk";
|
|
lcm-params-lk-ctrl;
|
|
lcm-params-lk-lcm-if;
|
|
lcm-params-lk-lcm-cmd-if;
|
|
lcm-params-lk-io-select-mode;
|
|
lcm-params-lk-lcm-x;
|
|
lcm-params-lk-lcm-y;
|
|
lcm-params-lk-virtual-resolution = <0 0>;
|
|
lcm-params-lk-od-table-size;
|
|
lcm-params-lk-od-table;
|
|
};
|
|
|
|
lcm-params-lk-round-corner {
|
|
compatible = "mediatek,lcm-params-lk-round-corner";
|
|
lcm-params-lk-rc-round-corner-en = <0>;
|
|
lcm-params-lk-rc-is-notch;
|
|
lcm-params-lk-rc-full-content = <0>;
|
|
lcm-params-lk-rc-width;
|
|
lcm-params-lk-rc-height;
|
|
lcm-params-lk-rc-width-bot;
|
|
lcm-params-lk-rc-height-bot;
|
|
lcm-params-lk-rc-top-size;
|
|
lcm-params-lk-rc-top-size-left;
|
|
lcm-params-lk-rc-top-size-right;
|
|
lcm-params-lk-rc-bottom-size;
|
|
lcm-params-lk-rc-pattern-name;
|
|
};
|
|
|
|
lcm-params-dbi {
|
|
compatible = "mediatek,lcm-params-dbi";
|
|
/* future reserved for dbi interfaces */
|
|
};
|
|
|
|
lcm-params-dpi {
|
|
compatible = "mediatek,lcm-params-dpi";
|
|
/* future reserved for dpi interfaces */
|
|
};
|
|
|
|
lcm-params-dsi {
|
|
compatible = "mediatek,lcm-params-dsi";
|
|
lcm-params-dsi-density = <560>;
|
|
lcm-params-dsi-lanes = <4>;
|
|
lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
|
|
lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
|
|
lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_LPM>,
|
|
<MTK_MIPI_DSI_MODE_EOT_PACKET>,
|
|
<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
|
|
lcm-params-dsi-mode-flags-doze-on;
|
|
lcm-params-dsi-mode-flags-doze-off;
|
|
|
|
lcm-params-dsi-need-fake-resolution;
|
|
lcm-params-dsi-fake-resolution = <1440 3216>;
|
|
|
|
lcm-gpio-list = <&pio 42 0>, /* gpio list*/
|
|
<&pio 28 0>,
|
|
<&pio 29 0>;
|
|
pinctrl-names = "gpio1", "gpio2", "gpio3";
|
|
pinctrl-0;
|
|
pinctrl-1;
|
|
pinctrl-2;
|
|
status = "okay";
|
|
|
|
lcm-params-dsi-default-mode = <0>;
|
|
lcm-params-dsi-mode-count = <1>;
|
|
lcm-params-dsi-mode-list =
|
|
<0 1440 3216 120>;
|
|
|
|
lcm-params-dsi-fps-0-1440-3216-120 {
|
|
compatible = "mediatek,lcm-dsi-fps-0-1440-3216-120";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <120>;
|
|
lcm-params-dsi-vertical-sync-active = <8>;
|
|
lcm-params-dsi-vertical-backporch = <8>;
|
|
lcm-params-dsi-vertical-frontporch = <8>;
|
|
lcm-params-dsi-vertical-active-line = <3216>;
|
|
lcm-params-dsi-horizontal-sync-active = <10>;
|
|
lcm-params-dsi-horizontal-backporch = <20>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <307152>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-lk-pll-clock = <718>;
|
|
lcm-params-dsi-lk-data-rate = <1436>;
|
|
lcm-params-dsi-pll-clock = <834>;
|
|
lcm-params-dsi-data-rate = <1668>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode = <MTK_LCM_PANEL_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <1>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9f];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* fpga support */
|
|
lcm-params-dsi-fpga-params-0-1440-3216-120 {
|
|
compatible = "mediatek,lcm-dsi-fpga-params";
|
|
|
|
lcm-params-dsi-lk-pll-div = <0 0>;
|
|
lcm-params-dsi-lk-fbk-div = <1>;
|
|
};
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-lk-params-0-1440-3216-120 {
|
|
compatible = "mediatek,lcm-dsi-lk-params";
|
|
lcm-params-dsi-lk-mode = <MTK_LK_CMD_MODE>;
|
|
lcm-params-dsi-lk-switch-mode;
|
|
lcm-params-dsi-lk-switch-mode-enable = <0>;
|
|
lcm-params-dsi-lk-dsi-wmem-conti;
|
|
lcm-params-dsi-lk-dsi-rmem-conti;
|
|
lcm-params-dsi-lk-vc-num;
|
|
lcm-params-dsi-lk-data-format =
|
|
<MTK_LCM_COLOR_ORDER_RGB>,
|
|
<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
|
|
<MTK_LCM_DSI_PADDING_ON_LSB>,
|
|
<MTK_LCM_DSI_FORMAT_RGB888>;
|
|
lcm-params-dsi-lk-intermediat-buffer-num;
|
|
lcm-params-dsi-lk-ps =
|
|
<MTK_LCM_PACKED_PS_24BIT_RGB888>;
|
|
lcm-params-dsi-lk-word-count;
|
|
lcm-params-dsi-lk-packet-size = <256>;
|
|
|
|
lcm-params-dsi-lk-horizontal-blanking-pixel;
|
|
lcm-params-dsi-lk-bllp;
|
|
lcm-params-dsi-lk-line-byte;
|
|
lcm-params-dsi-lk-horizontal-sync-active-byte;
|
|
lcm-params-dsi-lk-horizontal-backporch-byte;
|
|
lcm-params-dsi-lk-horizontal-frontporch-byte;
|
|
lcm-params-dsi-lk-rgb-byte;
|
|
lcm-params-dsi-lk-horizontal-sync-active-word-count;
|
|
lcm-params-dsi-lk-horizontal-backporch-word-count;
|
|
lcm-params-dsi-lk-horizontal-frontporch-word-count;
|
|
lcm-params-dsi-lk-pll-select;
|
|
lcm-params-dsi-lk-pll-div;
|
|
lcm-params-dsi-lk-fbk-div;
|
|
lcm-params-dsi-lk-fbk-sel;
|
|
lcm-params-dsi-lk-rg = <0 0 0>;
|
|
lcm-params-dsi-lk-dsi-clock;
|
|
lcm-params-dsi-lk-ssc-disable = <1>;
|
|
lcm-params-dsi-lk-ssc-range;
|
|
lcm-params-dsi-lk-compatibility-for-nvk;
|
|
lcm-params-dsi-lk-cont-clock;
|
|
lcm-params-dsi-lk-ufoe-enable;
|
|
lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
|
|
lcm-params-dsi-lk-edp-panel;
|
|
lcm-params-dsi-lk-lcm-int-te-monitor;
|
|
lcm-params-dsi-lk-lcm-int-te-period;
|
|
lcm-params-dsi-lk-lcm-ext-te-monitor;
|
|
lcm-params-dsi-lk-lcm-ext-te-period;
|
|
lcm-params-dsi-lk-noncont-clock;
|
|
lcm-params-dsi-lk-noncont-clock-period;
|
|
lcm-params-dsi-lk-clk-lp-per-line-enable;
|
|
lcm-params-dsi-lk-dual-dsi-type;
|
|
lcm-params-dsi-lk-mixmode-enable;
|
|
lcm-params-dsi-lk-mixmode-mipi-clock;
|
|
lcm-params-dsi-lk-pwm-fps;
|
|
lcm-params-dsi-lk-pll-clock-lp;
|
|
lcm-params-dsi-lk-ulps-sw-enable;
|
|
lcm-params-dsi-lk-null-packet-en;
|
|
lcm-params-dsi-lk-vact-fps;
|
|
lcm-params-dsi-lk-send-frame-enable;
|
|
lcm-params-dsi-lk-lfr-enable;
|
|
lcm-params-dsi-lk-lfr-mode;
|
|
lcm-params-dsi-lk-lfr-type;
|
|
lcm-params-dsi-lk-lfr-skip-num;
|
|
lcm-params-dsi-lk-ext-te-edge;
|
|
lcm-params-dsi-lk-eint-disable;
|
|
lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
|
|
};
|
|
|
|
lcm-params-dsi-dsc-params-0-1440-3216-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <1>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3216>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <24>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <643>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <1158>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <814>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-0-1440-3216-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-0-1440-3216-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <0>;
|
|
lcm-params-dsi-dyn-pll-clk;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-0-1440-3216-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 5a 9E],
|
|
[11 00 00 AB 30 80 0C 90 05],
|
|
[A0 00 18 02 D0 02 D0 02 00],
|
|
[02 86 00 20 02 83 00 0A 00],
|
|
[0D 04 86 03 2E 18 00 10 F0],
|
|
[07 10 20 00 06 0F 0F 33 0E],
|
|
[1C 2A 38 46 54 62 69 70 77],
|
|
[79 7B 7D 7E 02 02 22 00 2A],
|
|
[40 2A BE 3A FC 3A FA 3A F8],
|
|
[3B 38 3B 78 3B B6 4B B6 4B],
|
|
[F4 4B F4 6C 34 84 74 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9D 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 22 B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 B9 A1 B1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 3A B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B9 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 26 B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 B9 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 24 B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B9 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 38 B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B9 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 2A B9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 B9 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 16 F2],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F2 1B 50],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 BD 21 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 60 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 10 BD],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 BD 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F2 00 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B9 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2A 00 00 05 9F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2B 00 00 0C 8F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C3 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 2B F6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 F6 60 63 69],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 46 F4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F4 08],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 18 B1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B1 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 B0 00 0D 63],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 63 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 0C 63],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 63 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 0F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 55 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 5A 5A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 56 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[1F 01 17 01 18 06 88 06 89 0A],
|
|
[E2 0A E3 11 F5 1B C0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 6A 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 1d],
|
|
[1F 01 17 03 44 04 5A 05 71 06],
|
|
[88 07 9E 08 B5 09 CB 0A E2 0B],
|
|
[F9 0D 0F 0E 26 0F 3C 10 53],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 52 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1F 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 B0 00 54 1F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F0 A5 A5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02 MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 51 03 ff],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02 MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 10],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table =
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
lcm-update-table = [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2a is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2a],
|
|
/*x0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_MSB_BIT 03 01 08 00],
|
|
/*x0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_LSB_BIT 03 01 10 00],
|
|
/*x1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_MSB_BIT 03 01 18 00],
|
|
/*x0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2b is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2b],
|
|
/*y0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_MSB_BIT 03 01 08 00],
|
|
/*y0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_LSB_BIT 03 01 10 00],
|
|
/*y1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_MSB_BIT 03 01 18 00],
|
|
/*y0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 2c 39 09],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM_UNFORCE 00],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-backlight-mask = <0x7ff>;
|
|
set-backlight-cmdq-table =
|
|
/* runtime input count, data id*/
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 07 ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0xff>;
|
|
set-aod-light-table;
|
|
|
|
ata-id-value-data = [00 80 00];
|
|
ata-check-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_CMD 03 00 03 04],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
compare-id-value-data = [c5 a7];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 da],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[f0 5a 5a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02],
|
|
[53 24],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[f0 a5 a5],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 50],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[f0 5a 5a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02],
|
|
[53 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[f0 a5 a5],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
gpio-test-table = [MTK_LCM_GPIO_TYPE_HEX_MODE 02 01 02],
|
|
[MTK_LCM_GPIO_TYPE_HEX_DIR_OUTPUT 02 01 01],
|
|
[MTK_LCM_GPIO_TYPE_HEX_OUT 02 01 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
fps-switch-0-1440-3216-120-table;
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
fps-switch-0-1440-3216-120-table;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|