1328 lines
61 KiB
C
1328 lines
61 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*
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*/
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#ifndef _DT_BINDINGS_GCE_MT6985_H
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#define _DT_BINDINGS_GCE_MT6985_H
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/* assign timeout 0 also means default */
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#define CMDQ_NO_TIMEOUT 0xffffffff
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#define CMDQ_TIMEOUT_DEFAULT 1000
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/* GCE thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_1 1
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#define CMDQ_THR_PRIO_2 2
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#define CMDQ_THR_PRIO_3 3
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#define CMDQ_THR_PRIO_4 4
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#define CMDQ_THR_PRIO_5 5
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#define CMDQ_THR_PRIO_6 6
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#define CMDQ_THR_PRIO_HIGHEST 7
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/* CPR count in 32bit register */
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#define GCE_CPR_COUNT 1312
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/* GCE subsys table */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1502XXXX 4
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#define SUBSYS_1880XXXX 5
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#define SUBSYS_1881XXXX 6
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#define SUBSYS_1882XXXX 7
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#define SUBSYS_1883XXXX 8
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#define SUBSYS_1884XXXX 9
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#define SUBSYS_1000XXXX 10
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#define SUBSYS_1001XXXX 11
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#define SUBSYS_1002XXXX 12
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#define SUBSYS_1003XXXX 13
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#define SUBSYS_1004XXXX 14
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#define SUBSYS_1005XXXX 15
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#define SUBSYS_1020XXXX 16
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#define SUBSYS_1028XXXX 17
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#define SUBSYS_1700XXXX 18
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#define SUBSYS_1701XXXX 19
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#define SUBSYS_1702XXXX 20
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#define SUBSYS_1703XXXX 21
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#define SUBSYS_1800XXXX 22
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#define SUBSYS_1801XXXX 23
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#define SUBSYS_1802XXXX 24
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#define SUBSYS_1804XXXX 25
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#define SUBSYS_1805XXXX 26
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#define SUBSYS_1808XXXX 27
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#define SUBSYS_180aXXXX 28
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#define SUBSYS_180bXXXX 29
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#define SUBSYS_NO_SUPPORT 99
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/* GCE General Purpose Register (GPR) support
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* Leave note for scenario usage here
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*/
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/* GCE: write mask */
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#define GCE_GPR_R00 0x00
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#define GCE_GPR_R01 0x01
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/* MDP: P1: JPEG dest */
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#define GCE_GPR_R02 0x02
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#define GCE_GPR_R03 0x03
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/* MDP: PQ color */
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#define GCE_GPR_R04 0x04
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/* MDP: 2D sharpness */
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#define GCE_GPR_R05 0x05
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/* DISP: poll esd */
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#define GCE_GPR_R06 0x06
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#define GCE_GPR_R07 0x07
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/* MDP: P4: 2D sharpness dst */
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#define GCE_GPR_R08 0x08
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#define GCE_GPR_R09 0x09
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/* VCU: poll with timeout for GPR timer */
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#define GCE_GPR_R10 0x0A
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#define GCE_GPR_R11 0x0B
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/* CMDQ: debug */
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#define GCE_GPR_R12 0x0C
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#define GCE_GPR_R13 0x0D
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/* CMDQ: P7: debug */
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#define GCE_GPR_R14 0x0E
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#define GCE_GPR_R15 0x0F
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/* GCE-D hardware events */
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#define CMDQ_EVENT_OVLSYS_DISP_OVL0_2L_SOF 0
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#define CMDQ_EVENT_OVLSYS_DISP_OVL1_2L_SOF 1
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#define CMDQ_EVENT_OVLSYS_DISP_OVL2_2L_SOF 2
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#define CMDQ_EVENT_OVLSYS_DISP_OVL3_2L_SOF 3
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#define CMDQ_EVENT_OVLSYS_DISP_RSZ1_SOF 4
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#define CMDQ_EVENT_OVLSYS_DISP_MDP_RSZ0_SOF 5
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA0_SOF 6
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#define CMDQ_EVENT_OVLSYS_DISP_UFBC_WDMA0_SOF 7
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#define CMDQ_EVENT_OVLSYS_ISOINT_B 8
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#define CMDQ_EVENT_OVLSYS_DISP_DLI_ASYNC0_SOF 9
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#define CMDQ_EVENT_OVLSYS_DISP_DLI_ASYNC1_SOF 10
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#define CMDQ_EVENT_OVLSYS_DISP_DLI_ASYNC2_SOF 11
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC0_SOF 12
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC1_SOF 13
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC2_SOF 14
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC3_SOF 15
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC4_SOF 16
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC5_SOF 17
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#define CMDQ_EVENT_OVLSYS_DISP_DLO_ASYNC6_SOF 18
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#define CMDQ_EVENT_OVLSYS_INLINEROT0_SOF 19
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#define CMDQ_EVENT_OVLSYS_DISP_Y2R0_SOF 20
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#define CMDQ_EVENT_OVLSYS_DISP_Y2R1_SOF 21
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA2_FRAME_DONE 22
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA0_FRAME_DONE 23
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#define CMDQ_EVENT_OVLSYS_DISP_UFBC_WDMA0_FRAME_DONE 24
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#define CMDQ_EVENT_OVLSYS_DISP_RSZ1_FRAME_DONE 25
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#define CMDQ_EVENT_OVLSYS_DISP_OVL3_2L_FRAME_DONE 26
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#define CMDQ_EVENT_OVLSYS_DISP_OVL2_2L_FRAME_DONE 27
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#define CMDQ_EVENT_OVLSYS_DISP_OVL1_2L_FRAME_DONE 28
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#define CMDQ_EVENT_OVLSYS_DISP_OVL0_2L_FRAME_DONE 29
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#define CMDQ_EVENT_OVLSYS_DISP_MDP_RSZ0_FRAME_DONE 30
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_0 31
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_1 32
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_2 33
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_3 34
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_4 35
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_5 36
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_6 37
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_7 38
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_8 39
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_9 40
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_10 41
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_11 42
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_12 43
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_13 44
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_14 45
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#define CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_15 46
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 47
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 48
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 49
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#define CMDQ_EVENT_OVLSYS_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 50
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#define CMDQ_EVENT_OVLSYS_DISP_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 51
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#define CMDQ_EVENT_OVLSYS_DISP_OVL3_2L_RST_DONE_ENG_EVENT 52
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#define CMDQ_EVENT_OVLSYS_DISP_OVL2_2L_RST_DONE_ENG_EVENT 53
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#define CMDQ_EVENT_OVLSYS_DISP_OVL1_2L_RST_DONE_ENG_EVENT 54
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#define CMDQ_EVENT_OVLSYS_DISP_OVL0_2L_RST_DONE_ENG_EVENT 55
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_0 56
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_1 57
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_2 58
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_3 59
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_4 60
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_5 61
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_6 62
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#define CMDQ_EVENT_OVLSYS_BUF_UNDERRUN_ENG_EVENT_7 63
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL0_2L_SOF 64
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL1_2L_SOF 65
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL2_2L_SOF 66
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL3_2L_SOF 67
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#define CMDQ_EVENT_OVLSYS1_DISP_RSZ1_SOF 68
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#define CMDQ_EVENT_OVLSYS1_DISP_MDP_RSZ0_SOF 69
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA0_SOF 70
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#define CMDQ_EVENT_OVLSYS1_DISP_UFBC_WDMA0_SOF 71
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#define CMDQ_EVENT_OVLSYS1_ISOINT_B 72
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#define CMDQ_EVENT_OVLSYS1_DISP_DLI_ASYNC0_SOF 73
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#define CMDQ_EVENT_OVLSYS1_DISP_DLI_ASYNC1_SOF 74
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#define CMDQ_EVENT_OVLSYS1_DISP_DLI_ASYNC2_SOF 75
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC0_SOF 76
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC1_SOF 77
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC2_SOF 78
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC3_SOF 79
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC4_SOF 80
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC5_SOF 81
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#define CMDQ_EVENT_OVLSYS1_DISP_DLO_ASYNC6_SOF 82
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#define CMDQ_EVENT_OVLSYS1_INLINEROT0_SOF 83
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#define CMDQ_EVENT_OVLSYS1_DISP_Y2R0_SOF 84
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#define CMDQ_EVENT_OVLSYS1_DISP_Y2R1_SOF 85
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA2_FRAME_DONE 86
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA0_FRAME_DONE 87
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#define CMDQ_EVENT_OVLSYS1_DISP_UFBC_WDMA0_FRAME_DONE 88
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#define CMDQ_EVENT_OVLSYS1_DISP_RSZ1_FRAME_DONE 89
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL3_2L_FRAME_DONE 90
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL2_2L_FRAME_DONE 91
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL1_2L_FRAME_DONE 92
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL0_2L_FRAME_DONE 93
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#define CMDQ_EVENT_OVLSYS1_DISP_MDP_RSZ0_FRAME_DONE 94
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_0 95
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_1 96
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_2 97
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_3 98
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_4 99
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_5 100
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_6 101
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_7 102
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_8 103
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_9 104
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_10 105
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_11 106
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_12 107
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_13 108
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_14 109
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#define CMDQ_EVENT_OVLSYS1_STREAM_DONE_ENG_EVENT_15 110
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 111
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 112
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 113
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#define CMDQ_EVENT_OVLSYS1_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 114
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#define CMDQ_EVENT_OVLSYS1_DISP_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 115
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL3_2L_RST_DONE_ENG_EVENT 116
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL2_2L_RST_DONE_ENG_EVENT 117
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL1_2L_RST_DONE_ENG_EVENT 118
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#define CMDQ_EVENT_OVLSYS1_DISP_OVL0_2L_RST_DONE_ENG_EVENT 119
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_0 120
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_1 121
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_2 122
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_3 123
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_4 124
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_5 125
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_6 126
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#define CMDQ_EVENT_OVLSYS1_BUF_UNDERRUN_ENG_EVENT_7 127
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA0_SOF 128
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA1_SOF 129
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT0_SOF 130
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT1_SOF 131
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA2_SOF 132
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA3_SOF 133
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#define CMDQ_EVENT_MMLSYS1_MDP_DLI_ASYNC0_SOF 134
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#define CMDQ_EVENT_MMLSYS1_MDP_DLI_ASYNC1_SOF 135
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#define CMDQ_EVENT_MMLSYS1_MDP_DLO_ASYNC0_SOF 136
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#define CMDQ_EVENT_MMLSYS1_MDP_DLO_ASYNC1_SOF 137
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT2_SOF 138
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT3_SOF 139
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#define CMDQ_EVENT_MMLSYS1_MDP_DLI_ASYNC3_SOF 140
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#define CMDQ_EVENT_MMLSYS1_MDP_DLO_ASYNC2_SOF 141
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#define CMDQ_EVENT_MMLSYS1_MDP_DLO_ASYNC3_SOF 142
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT3_FRAME_DONE 143
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT2_FRAME_DONE 144
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT1_FRAME_DONE 145
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT0_FRAME_DONE 146
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#define CMDQ_EVENT_MMLSYS1_MDP_TDSHP1_FRAME_DONE 147
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#define CMDQ_EVENT_MMLSYS1_MDP_TDSHP0_FRAME_DONE 148
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#define CMDQ_EVENT_MMLSYS1_MDP_RSZ3_FRAME_DONE 149
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#define CMDQ_EVENT_MMLSYS1_MDP_RSZ2_FRAME_DONE 150
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#define CMDQ_EVENT_MMLSYS1_MDP_RSZ1_FRAME_DONE 151
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#define CMDQ_EVENT_MMLSYS1_MDP_RSZ0_FRAME_DONE 152
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA3_FRAME_DONE 153
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA2_FRAME_DONE 154
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA1_FRAME_DONE 155
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA0_FRAME_DONE 156
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#define CMDQ_EVENT_MMLSYS1_MDP_HDR1_FRAME_DONE 157
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#define CMDQ_EVENT_MMLSYS1_MDP_HDR0_FRAME_DONE 158
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#define CMDQ_EVENT_MMLSYS1_MDP_COLOR1_FRAME_DONE 159
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#define CMDQ_EVENT_MMLSYS1_MDP_COLOR0_FRAME_DONE 160
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#define CMDQ_EVENT_MMLSYS1_MDP_BIRSZ1_FRAME_DONE 161
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#define CMDQ_EVENT_MMLSYS1_MDP_BIRSZ0_FRAME_DONE 162
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#define CMDQ_EVENT_MMLSYS1_MDP_AAL1_FRAME_DONE 163
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#define CMDQ_EVENT_MMLSYS1_MDP_AAL0_FRAME_DONE 164
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_0 165
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_1 166
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_2 167
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_3 168
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_4 169
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_5 170
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_6 171
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_7 172
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_8 173
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_9 174
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_10 175
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_11 176
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_12 177
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_13 178
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_14 179
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#define CMDQ_EVENT_MMLSYS1_STREAM_DONE_ENG_EVENT_15 180
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT3_SW_RST_DONE_ENG_EVENT 181
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 182
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 183
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#define CMDQ_EVENT_MMLSYS1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 184
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 185
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 186
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 187
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#define CMDQ_EVENT_MMLSYS1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 188
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#define CMDQ_EVENT_MMLSYS1_BUF_UNDERRUN_ENG_EVENT_0 189
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#define CMDQ_EVENT_MMLSYS1_BUF_UNDERRUN_ENG_EVENT_1 190
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#define CMDQ_EVENT_MMLSYS1_BUF_UNDERRUN_ENG_EVENT_2 191
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_SOF 192
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_SOF 193
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#define CMDQ_EVENT_MMLSYS_MDP_WROT0_SOF 194
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#define CMDQ_EVENT_MMLSYS_MDP_WROT1_SOF 195
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_SOF 196
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_SOF 197
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#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC0_SOF 198
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#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC1_SOF 199
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#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC0_SOF 200
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#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC1_SOF 201
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#define CMDQ_EVENT_MMLSYS_MDP_WROT2_SOF 202
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#define CMDQ_EVENT_MMLSYS_MDP_WROT3_SOF 203
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#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC3_SOF 204
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#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC2_SOF 205
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#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC3_SOF 206
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#define CMDQ_EVENT_MMLSYS_MDP_WROT3_FRAME_DONE 207
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#define CMDQ_EVENT_MMLSYS_MDP_WROT2_FRAME_DONE 208
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#define CMDQ_EVENT_MMLSYS_MDP_WROT1_FRAME_DONE 209
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#define CMDQ_EVENT_MMLSYS_MDP_WROT0_FRAME_DONE 210
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#define CMDQ_EVENT_MMLSYS_MDP_TDSHP1_FRAME_DONE 211
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#define CMDQ_EVENT_MMLSYS_MDP_TDSHP0_FRAME_DONE 212
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#define CMDQ_EVENT_MMLSYS_MDP_RSZ3_FRAME_DONE 213
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#define CMDQ_EVENT_MMLSYS_MDP_RSZ2_FRAME_DONE 214
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#define CMDQ_EVENT_MMLSYS_MDP_RSZ1_FRAME_DONE 215
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#define CMDQ_EVENT_MMLSYS_MDP_RSZ0_FRAME_DONE 216
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_FRAME_DONE 217
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_FRAME_DONE 218
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_FRAME_DONE 219
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_FRAME_DONE 220
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#define CMDQ_EVENT_MMLSYS_MDP_HDR1_FRAME_DONE 221
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#define CMDQ_EVENT_MMLSYS_MDP_HDR0_FRAME_DONE 222
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#define CMDQ_EVENT_MMLSYS_MDP_COLOR1_FRAME_DONE 223
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#define CMDQ_EVENT_MMLSYS_MDP_COLOR0_FRAME_DONE 224
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#define CMDQ_EVENT_MMLSYS_MDP_BIRSZ1_FRAME_DONE 225
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#define CMDQ_EVENT_MMLSYS_MDP_BIRSZ0_FRAME_DONE 226
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#define CMDQ_EVENT_MMLSYS_MDP_AAL1_FRAME_DONE 227
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#define CMDQ_EVENT_MMLSYS_MDP_AAL0_FRAME_DONE 228
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_0 229
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_1 230
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_2 231
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_3 232
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_4 233
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_5 234
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_6 235
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_7 236
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_8 237
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_9 238
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_10 239
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_11 240
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_12 241
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_13 242
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_14 243
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#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_15 244
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#define CMDQ_EVENT_MMLSYS_MDP_WROT3_SW_RST_DONE_ENG_EVENT 245
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#define CMDQ_EVENT_MMLSYS_MDP_WROT2_SW_RST_DONE_ENG_EVENT 246
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#define CMDQ_EVENT_MMLSYS_MDP_WROT1_SW_RST_DONE_ENG_EVENT 247
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#define CMDQ_EVENT_MMLSYS_MDP_WROT0_SW_RST_DONE_ENG_EVENT 248
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 249
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 250
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 251
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#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 252
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#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_0 253
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#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_1 254
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#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_2 255
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#define CMDQ_EVENT_DISPSYS_DISP_AAL0_SOF 256
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#define CMDQ_EVENT_DISPSYS_DISP_C3D0_SOF 257
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#define CMDQ_EVENT_DISPSYS_DISP_CCORR0_SOF 258
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#define CMDQ_EVENT_DISPSYS_DISP_CCORR1_SOF 259
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#define CMDQ_EVENT_DISPSYS_DISP_CHIST0_SOF 260
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#define CMDQ_EVENT_DISPSYS_DISP_CHIST1_SOF 261
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#define CMDQ_EVENT_DISPSYS_DISP_COLOR0_SOF 262
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#define CMDQ_EVENT_DISPSYS_DISP_DITHER0_SOF 263
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#define CMDQ_EVENT_DISPSYS_DISP_DITHER1_SOF 264
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC0_SOF 265
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC1_SOF 266
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC2_SOF 267
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC3_SOF 268
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC4_SOF 269
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#define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC5_SOF 270
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#define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC0_SOF 271
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#define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC1_SOF 272
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_SOF 273
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#define CMDQ_EVENT_DISPSYS_DSC_WRAP0_CORE0_SOF 274
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#define CMDQ_EVENT_DISPSYS_DSC_WRAP0_CORE1_SOF 275
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF 276
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#define CMDQ_EVENT_DISPSYS_DISP_OCIP_SUBSYS_SRAM_ISOINT_B 277
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#define CMDQ_EVENT_DISPSYS_DISP_MDP_AAL0_SOF 278
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#define CMDQ_EVENT_DISPSYS_DISP_MDP_RDMA0_SOF 279
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE0_SOF 280
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE1_SOF 281
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#define CMDQ_EVENT_DISPSYS_DISP_ODDMR0_SOF 282
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#define CMDQ_EVENT_DISPSYS_DISP_POSTALIGN0_SOF 283
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#define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_SOF 284
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#define CMDQ_EVENT_DISPSYS_DISP_PWM0_SOF 285
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#define CMDQ_EVENT_DISPSYS_DISP_RELAY0_SOF 286
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#define CMDQ_EVENT_DISPSYS_DISP_RSZ0_SOF 287
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#define CMDQ_EVENT_DISPSYS_DISP_SPR0_SOF 288
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#define CMDQ_EVENT_DISPSYS_DISP_TDSHP0_SOF 289
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#define CMDQ_EVENT_DISPSYS_DISP_TDSHP1_SOF 290
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#define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA1_SOF 291
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#define CMDQ_EVENT_DISPSYS_DISP_VDCM0_SOF 292
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#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_SOF 293
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_0 294
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_1 295
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_2 296
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_3 297
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_4 298
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_5 299
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#define CMDQ_EVENT_DISPSYS_PMSR_MOD_FRAME_DONE_6 300
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#define CMDQ_EVENT_DISPSYS_LCM_FRAME_DONE_0 301
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#define CMDQ_EVENT_DISPSYS_LCM_FRAME_DONE_1 302
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#define CMDQ_EVENT_DISPSYS_LCM_FRAME_DONE_2 303
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#define CMDQ_EVENT_DISPSYS_LCM_FRAME_DONE_3 304
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#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE 305
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#define CMDQ_EVENT_DISPSYS_DISP_VDCM0_FRAME_DONE 306
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#define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA1_FRAME_DONE 307
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#define CMDQ_EVENT_DISPSYS_DISP_TDSHP1_FRAME_DONE 308
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#define CMDQ_EVENT_DISPSYS_DISP_TDSHP0_FRAME_DONE 309
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#define CMDQ_EVENT_DISPSYS_DISP_SPR0_FRAME_DONE 310
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#define CMDQ_EVENT_DISPSYS_DISP_RSZ0_FRAME_DONE 311
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#define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_FRAME_DONE 312
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#define CMDQ_EVENT_DISPSYS_DISP_ODDMR0_FRAME_DONE 313
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE1_FRAME_DONE 314
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE0_FRAME_DONE 315
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#define CMDQ_EVENT_DISPSYS_DISP_MDP_RDMA0_FRAME_DONE 316
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#define CMDQ_EVENT_DISPSYS_DISP_MDP_AAL0_FRAME_DONE 317
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#define CMDQ_EVENT_DISPSYS_DISP_GAMMA0_FRAME_DONE 318
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_FRAME_DONE 319
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#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE1_FRAME_DONE 320
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#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE 321
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_FRAME_DONE 322
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#define CMDQ_EVENT_DISPSYS_DISP_DITHER1_FRAME_DONE 323
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#define CMDQ_EVENT_DISPSYS_DISP_DITHER0_FRAME_DONE 324
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#define CMDQ_EVENT_DISPSYS_DISP_COLOR0_FRAME_DONE 325
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#define CMDQ_EVENT_DISPSYS_DISP_CHIST1_FRAME_DONE 326
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#define CMDQ_EVENT_DISPSYS_DISP_CHIST0_FRAME_DONE 327
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#define CMDQ_EVENT_DISPSYS_DISP_CCORR1_FRAME_DONE 328
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#define CMDQ_EVENT_DISPSYS_DISP_CCORR0_FRAME_DONE 329
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#define CMDQ_EVENT_DISPSYS_DISP_C3D0_FRAME_DONE 330
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#define CMDQ_EVENT_DISPSYS_DISP_AAL0_FRAME_DONE 331
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_0 332
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_1 333
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_2 334
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_3 335
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_4 336
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_5 337
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_6 338
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_7 339
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_8 340
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_9 341
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_10 342
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_11 343
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_12 344
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_13 345
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_14 346
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#define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_15 347
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#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 348
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#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 349
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#define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA1_UFBC_TARGET_LINE_END_ENG_EVENT 350
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#define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_RST_DONE_ENG_EVENT 351
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE1_ENG_EVENT 352
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#define CMDQ_EVENT_DISPSYS_DISP_MERGE0_ENG_EVENT 353
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#define CMDQ_EVENT_DISPSYS_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 354
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_TE_ENG_EVENT 355
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_TARGET_LINE_ENG_EVENT 356
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_IRQ_ENG_EVENT 357
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#define CMDQ_EVENT_DISPSYS_DISP_DSI0_DONE_ENG_EVENT 358
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 359
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 360
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_VDE_START_ENG_EVENT 361
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_VDE_END_ENG_EVENT 362
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#define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 363
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_0 364
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_1 365
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_2 366
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_3 367
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_4 368
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_5 369
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_6 370
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#define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_7 371
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#define CMDQ_EVENT_DISP_EVENT_116 372
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#define CMDQ_EVENT_DISP_EVENT_117 373
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#define CMDQ_EVENT_DISP_EVENT_118 374
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#define CMDQ_EVENT_DISP_EVENT_119 375
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#define CMDQ_EVENT_DISP_EVENT_120 376
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#define CMDQ_EVENT_DISP_EVENT_121 377
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#define CMDQ_EVENT_DISP_EVENT_122 378
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#define CMDQ_EVENT_DISP_EVENT_123 379
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#define CMDQ_EVENT_DISP_EVENT_124 380
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#define CMDQ_EVENT_DISP_EVENT_125 381
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#define CMDQ_EVENT_DISP_EVENT_126 382
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#define CMDQ_EVENT_DISP_EVENT_127 383
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#define CMDQ_EVENT_DISPSYS1_DISP_AAL0_SOF 384
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#define CMDQ_EVENT_DISPSYS1_DISP_C3D0_SOF 385
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#define CMDQ_EVENT_DISPSYS1_DISP_CCORR0_SOF 386
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#define CMDQ_EVENT_DISPSYS1_DISP_CCORR1_SOF 387
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#define CMDQ_EVENT_DISPSYS1_DISP_CHIST0_SOF 388
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#define CMDQ_EVENT_DISPSYS1_DISP_CHIST1_SOF 389
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#define CMDQ_EVENT_DISPSYS1_DISP_COLOR0_SOF 390
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#define CMDQ_EVENT_DISPSYS1_DISP_DITHER0_SOF 391
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#define CMDQ_EVENT_DISPSYS1_DISP_DITHER1_SOF 392
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC0_SOF 393
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC1_SOF 394
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC2_SOF 395
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC3_SOF 396
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC4_SOF 397
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#define CMDQ_EVENT_DISPSYS1_DISP_DLI_ASYNC5_SOF 398
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#define CMDQ_EVENT_DISPSYS1_DISP_DLO_ASYNC0_SOF 399
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#define CMDQ_EVENT_DISPSYS1_DISP_DLO_ASYNC1_SOF 400
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#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_SOF 401
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#define CMDQ_EVENT_DISPSYS1_DSC_WRAP0_CORE0_SOF 402
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#define CMDQ_EVENT_DISPSYS1_DSC_WRAP0_CORE1_SOF 403
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#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_SOF 404
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#define CMDQ_EVENT_DISPSYS1_OCIP_SUBSYS_SRAM_ISOINT_B 405
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#define CMDQ_EVENT_DISPSYS1_DISP_MDP_AAL0_SOF 406
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#define CMDQ_EVENT_DISPSYS1_DISP_MDP_RDMA0_SOF 407
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#define CMDQ_EVENT_DISPSYS1_DISP_MERGE0_SOF 408
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#define CMDQ_EVENT_DISPSYS1_DISP_MERGE1_SOF 409
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#define CMDQ_EVENT_DISPSYS1_DISP_ODDMR0_SOF 410
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#define CMDQ_EVENT_DISPSYS1_DISP_POSTALIGN0_SOF 411
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|
#define CMDQ_EVENT_DISPSYS1_DISP_POSTMASK0_SOF 412
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|
#define CMDQ_EVENT_DISPSYS1_DISP_PWM0_SOF 413
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|
#define CMDQ_EVENT_DISPSYS1_DISP_RELAY0_SOF 414
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|
#define CMDQ_EVENT_DISPSYS1_DISP_RSZ0_SOF 415
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|
#define CMDQ_EVENT_DISPSYS1_DISP_SPR0_SOF 416
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#define CMDQ_EVENT_DISPSYS1_DISP_TDSHP0_SOF 417
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|
#define CMDQ_EVENT_DISPSYS1_DISP_TDSHP1_SOF 418
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|
#define CMDQ_EVENT_DISPSYS1_DISP_UFBC_WDMA1_SOF 419
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#define CMDQ_EVENT_DISPSYS1_DISP_VDCM0_SOF 420
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|
#define CMDQ_EVENT_DISPSYS1_DISP_WDMA1_SOF 421
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_0 422
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_1 423
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_2 424
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_3 425
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_4 426
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_5 427
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|
#define CMDQ_EVENT_DISPSYS1_PMSR_MOD_FRAME_DONE_6 428
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|
#define CMDQ_EVENT_DISPSYS1_LCM_FRAME_DONE_0 429
|
|
#define CMDQ_EVENT_DISPSYS1_LCM_FRAME_DONE_1 430
|
|
#define CMDQ_EVENT_DISPSYS1_LCM_FRAME_DONE_2 431
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|
#define CMDQ_EVENT_DISPSYS1_LCM_FRAME_DONE_3 432
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|
#define CMDQ_EVENT_DISPSYS1_DISP_WDMA1_FRAME_DONE 433
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|
#define CMDQ_EVENT_DISPSYS1_DISP_VDCM0_FRAME_DONE 434
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_UFBC_WDMA1_FRAME_DONE 435
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_TDSHP1_FRAME_DONE 436
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|
#define CMDQ_EVENT_DISPSYS1_DISP_TDSHP0_FRAME_DONE 437
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_SPR0_FRAME_DONE 438
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_RSZ0_FRAME_DONE 439
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_POSTMASK0_FRAME_DONE 440
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_ODDMR0_FRAME_DONE 441
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|
#define CMDQ_EVENT_DISPSYS1_DISP_MERGE1_FRAME_DONE 442
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|
#define CMDQ_EVENT_DISPSYS1_DISP_MERGE0_FRAME_DONE 443
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_MDP_RDMA0_FRAME_DONE 444
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_MDP_AAL0_FRAME_DONE 445
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_GAMMA0_FRAME_DONE 446
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_FRAME_DONE 447
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DSC_WRAP0_CORE1_FRAME_DONE 448
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DSC_WRAP0_CORE0_FRAME_DONE 449
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_FRAME_DONE 450
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DITHER1_FRAME_DONE 451
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_DITHER0_FRAME_DONE 452
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_COLOR0_FRAME_DONE 453
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_CHIST1_FRAME_DONE 454
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_CHIST0_FRAME_DONE 455
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_CCORR1_FRAME_DONE 456
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_CCORR0_FRAME_DONE 457
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_C3D0_FRAME_DONE 458
|
|
#define CMDQ_EVENT_DISPSYS1_DISP_AAL0_FRAME_DONE 459
|
|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_0 460
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_1 461
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_2 462
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_3 463
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_4 464
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_5 465
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_6 466
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_7 467
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_8 468
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_9 469
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_10 470
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_11 471
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#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_12 472
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_13 473
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_14 474
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|
#define CMDQ_EVENT_DISPSYS1_STREAM_DONE_ENG_EVENT_15 475
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|
#define CMDQ_EVENT_DISPSYS1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 476
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|
#define CMDQ_EVENT_DISPSYS1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 477
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|
#define CMDQ_EVENT_DISPSYS1_DISP_UFBC_WDMA1_UFBC_TARGET_LINE_END_ENG_EVENT 478
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|
#define CMDQ_EVENT_DISPSYS1_DISP_POSTMASK0_RST_DONE_ENG_EVENT 479
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|
#define CMDQ_EVENT_DISPSYS1_DISP_MERGE1_ENG_EVENT 480
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|
#define CMDQ_EVENT_DISPSYS1_DISP_MERGE0_ENG_EVENT 481
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|
#define CMDQ_EVENT_DISPSYS1_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 482
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_TE_ENG_EVENT 483
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_TARGET_LINE_ENG_EVENT 484
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#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_IRQ_ENG_EVENT 485
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DSI0_DONE_ENG_EVENT 486
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#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 487
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 488
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_VDE_START_ENG_EVENT 489
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_VDE_END_ENG_EVENT 490
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|
#define CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 491
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_0 492
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_1 493
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#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_2 494
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_3 495
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#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_4 496
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_5 497
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_6 498
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|
#define CMDQ_EVENT_DISPSYS1_BUF_UNDERRUN_ENG_EVENT_7 499
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|
#define CMDQ_EVENT_DISP1_EVENT_116 500
|
|
#define CMDQ_EVENT_DISP1_EVENT_117 501
|
|
#define CMDQ_EVENT_DISP1_EVENT_118 502
|
|
#define CMDQ_EVENT_DISP1_EVENT_119 503
|
|
#define CMDQ_EVENT_DISP1_EVENT_120 504
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|
#define CMDQ_EVENT_DISP1_EVENT_121 505
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|
#define CMDQ_EVENT_DISP1_EVENT_122 506
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|
#define CMDQ_EVENT_DISP1_EVENT_123 507
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|
#define CMDQ_EVENT_DISP1_EVENT_124 508
|
|
#define CMDQ_EVENT_DISP1_EVENT_125 509
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|
#define CMDQ_EVENT_DISP1_EVENT_126 510
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|
#define CMDQ_EVENT_DISP1_EVENT_127 511
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|
#define CMDQ_EVENT_GCE_EVENT_DSI0_TE_I 898
|
|
#define CMDQ_EVENT_GCE_EVENT_DSI1_TE_I 899
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|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP1_SRAM_SLEEP_ACK 900
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP1_SRAM_ACK 901
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP1_PWR_ACK_S 902
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP1_PWR_ACK 903
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|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP0_SRAM_SLEEP_ACK 904
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP0_SRAM_ACK 905
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP0_PWR_ACK_S 906
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_DISP0_PWR_ACK 907
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|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL1_SRAM_SLEEP_ACK 908
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL1_SRAM_ACK 909
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|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL1_PWR_ACK_S 910
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL1_PWR_ACK 911
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL0_SRAM_SLEEP_ACK 912
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL0_SRAM_ACK 913
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL0_PWR_ACK_S 914
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_OVL0_PWR_ACK 915
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|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML1_SRAM_SLEEP_ACK 916
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML1_SRAM_ACK 917
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML1_PWR_ACK_S 918
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML1_PWR_ACK 919
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML0_SRAM_SLEEP_ACK 920
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML0_SRAM_ACK 921
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML0_PWR_ACK_S 922
|
|
#define CMDQ_EVENT_DISPSYS_QUICK_ON_OFF_GCE_EVENT_MML0_PWR_ACK 923
|
|
#define CMDQ_EVENT_DPTX_DPTX_EVENT_0 922
|
|
#define CMDQ_EVENT_DPTX_DPTX_EVENT_1 923
|
|
|
|
/* GCE-M hardware events */
|
|
#define CMDQ_EVENT_VDEC1_LINE_COUNT_THRESHOLD_INTERRUPT 0
|
|
#define CMDQ_EVENT_VDEC1_VDEC_INT 1
|
|
#define CMDQ_EVENT_VDEC1_VDEC_PAUSE 2
|
|
#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERROR 3
|
|
#define CMDQ_EVENT_VDEC1_MC_BUSY_OVERFLOW_OR_MDEC_TIMEOUT 4
|
|
#define CMDQ_EVENT_VDEC1_DRAM_NOT_REQ_AND_ALL_CNT_0_AND_BITS_PROC_NOP_1_AND_BITS_PROC_NOP_2 5
|
|
#define CMDQ_EVENT_VDEC1_INI_FETCH_RDY 6
|
|
#define CMDQ_EVENT_VDEC1_PROCESS_FLAG 7
|
|
#define CMDQ_EVENT_VDEC1_SEARCH_START_CODE_DONE 8
|
|
#define CMDQ_EVENT_VDEC1_REF_REORDER_DONE 9
|
|
#define CMDQ_EVENT_VDEC1_WP_TBLE_DONE 10
|
|
#define CMDQ_EVENT_VDEC1_RESET_PIC_NUM_REGS 11
|
|
|
|
#define CMDQ_EVENT_VDEC1_GCE_CNT_OP_THRESHOLD 15
|
|
#define CMDQ_EVENT_VDEC1_MDP0_RDMA_SW_RST_DONE_ENG_EVENT 16
|
|
#define CMDQ_EVENT_VDEC1_MDP0_RDMA_TILE_DONE 17
|
|
#define CMDQ_EVENT_VDEC1_MDP0_WDMA_SW_RST_DONE_ENG_EVENT 18
|
|
#define CMDQ_EVENT_VDEC1_MDP0_WDMA_TILE_DONE 19
|
|
#define CMDQ_EVENT_VDEC1_MDP1_RDMA_SW_RST_DONE_ENG_EVENT 20
|
|
#define CMDQ_EVENT_VDEC1_MDP1_RDMA_TILE_DONE 21
|
|
#define CMDQ_EVENT_VDEC1_MDP1_WDMA_SW_RST_DONE_ENG_EVENT 22
|
|
#define CMDQ_EVENT_VDEC1_MDP1_WDMA_TILE_DONE 23
|
|
|
|
#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE 129
|
|
#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE 130
|
|
#define CMDQ_EVENT_VENC3_JPGENC_DONE 131
|
|
#define CMDQ_EVENT_VENC3_VENC_MB_DONE 132
|
|
#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE 133
|
|
#define CMDQ_EVENT_VENC3_JPGDEC_DONE 134
|
|
#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE 135
|
|
#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE 136
|
|
#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE 137
|
|
#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE 138
|
|
#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE 139
|
|
#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE 140
|
|
#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE 141
|
|
#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE 142
|
|
|
|
#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE 161
|
|
#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE 162
|
|
#define CMDQ_EVENT_VENC2_JPGENC_DONE 163
|
|
#define CMDQ_EVENT_VENC2_VENC_MB_DONE 164
|
|
#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE 165
|
|
#define CMDQ_EVENT_VENC2_JPGDEC_DONE 166
|
|
#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE 167
|
|
#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE 168
|
|
#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE 169
|
|
#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE 170
|
|
#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE 171
|
|
#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE 172
|
|
#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE 173
|
|
#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE 174
|
|
|
|
#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE 193
|
|
#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE 194
|
|
#define CMDQ_EVENT_VENC1_JPGENC_DONE 195
|
|
#define CMDQ_EVENT_VENC1_VENC_MB_DONE 196
|
|
#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE 197
|
|
#define CMDQ_EVENT_VENC1_JPGDEC_DONE 198
|
|
#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE 199
|
|
#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE 200
|
|
#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE 201
|
|
#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE 202
|
|
#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE 203
|
|
#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE 204
|
|
#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE 205
|
|
#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE 206
|
|
|
|
#define CMDQ_EVENT_VDEC2_LINE_COUNT_THRESHOLD_INTERRUPT 224
|
|
#define CMDQ_EVENT_VDEC2_VDEC_INT 225
|
|
#define CMDQ_EVENT_VDEC2_VDEC_PAUSE 226
|
|
#define CMDQ_EVENT_VDEC2_VDEC_DEC_ERROR 227
|
|
#define CMDQ_EVENT_VDEC2_MC_BUSY_OVERFLOW_OR_MDEC_TIMEOUT 228
|
|
#define CMDQ_EVENT_VDEC2_DRAM_NOT_REQ_AND_ALL_CNT_0_AND_BITS_PROC_NOP_1_AND_BITS_PROC_NOP_2 229
|
|
#define CMDQ_EVENT_VDEC2_INI_FETCH_RDY 230
|
|
#define CMDQ_EVENT_VDEC2_PROCESS_FLAG 231
|
|
#define CMDQ_EVENT_VDEC2_SEARCH_START_CODE_DONE 232
|
|
#define CMDQ_EVENT_VDEC2_REF_REORDER_DONE 233
|
|
#define CMDQ_EVENT_VDEC2_WP_TBLE_DONE 234
|
|
#define CMDQ_EVENT_VDEC2_RESET_PIC_NUM_REGS 235
|
|
|
|
#define CMDQ_EVENT_VDEC2_GCE_CNT_OP_THRESHOLD 239
|
|
|
|
#define CMDQ_EVENT_IMG_IMG_SOF 256
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 257
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_1 258
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_2 259
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_3 260
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_4 261
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_5 262
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_6 263
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_7 264
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_8 265
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_9 266
|
|
#define CMDQ_EVENT_IMG_TRAW0_DIP_DMA_ERR_EVENT 267
|
|
#define CMDQ_EVENT_IMG_TRAW0_DIP_RESERVED 268
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 269
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_1 270
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_2 271
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_3 272
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_4 273
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_5 274
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_6 275
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_7 276
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_8 277
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_9 278
|
|
#define CMDQ_EVENT_IMG_TRAW1_DIP_DMA_ERR_EVENT 279
|
|
#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 280
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_0 281
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_1 282
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_2 283
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_3 284
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_4 285
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_5 286
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_6 287
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_7 288
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_8 289
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_9 290
|
|
#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 291
|
|
#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 292
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_0 293
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_1 294
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_2 295
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 296
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 297
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_0 298
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_1 299
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_2 300
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_3 301
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_4 302
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_5 303
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_6 304
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_7 305
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_8 306
|
|
#define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_9 307
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_0 308
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_1 309
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_2 310
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_3 311
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_4 312
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_5 313
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_6 314
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_7 315
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_8 316
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_9 317
|
|
#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 318
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_0 319
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_1 320
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_2 321
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 322
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 323
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_0 324
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_1 325
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_2 326
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_3 327
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_4 328
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_5 329
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_6 330
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_7 331
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_8 332
|
|
#define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_9 333
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_0 334
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_1 335
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_2 336
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_3 337
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_4 338
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_5 339
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_6 340
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_7 341
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_8 342
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_9 343
|
|
#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 344
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_0 345
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_1 346
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_2 347
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 348
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 349
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_0 350
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_1 351
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_2 352
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_3 353
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_4 354
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_5 355
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_6 356
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_7 357
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_8 358
|
|
#define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_9 359
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_0 360
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_1 361
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_2 362
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_3 363
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_4 364
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_5 365
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_6 366
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_7 367
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_8 368
|
|
#define CMDQ_EVENT_IMG_XTRAW_RESERVED_9 369
|
|
#define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT_RESERVED 370
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_0 371
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_1 372
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_2 373
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 374
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 375
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 376
|
|
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE 385
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE 386
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE 387
|
|
#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_0 388
|
|
#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_1 389
|
|
#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_2 390
|
|
#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE_3 391
|
|
#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_0 392
|
|
#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_1 393
|
|
#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_2 394
|
|
#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE_3 395
|
|
#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_0 396
|
|
#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_1 397
|
|
#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_2 398
|
|
#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE_3 399
|
|
#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_0 400
|
|
#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_1 401
|
|
#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_2 402
|
|
#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE_3 403
|
|
#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_0 404
|
|
#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_1 405
|
|
#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_2 406
|
|
#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE_3 407
|
|
#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_0 408
|
|
#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_1 409
|
|
#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_2 410
|
|
#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE_3 411
|
|
#define CMDQ_EVENT_CAM_MRAW_0_SW_PASS1_DONE 412
|
|
#define CMDQ_EVENT_CAM_MRAW_1_SW_PASS1_DONE 413
|
|
#define CMDQ_EVENT_CAM_MRAW_2_SW_PASS1_DONE 414
|
|
#define CMDQ_EVENT_CAM_MRAW_3_SW_PASS1_DONE 415
|
|
#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE 416
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM0_FIFO_FULL 417
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM1_FIFO_FULL 418
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM2_FIFO_FULL 419
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM3_FIFO_FULL 420
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM4_FIFO_FULL 421
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM5_FIFO_FULL 422
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM6_FIFO_FULL 423
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM7_FIFO_FULL 424
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM8_FIFO_FULL 425
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM9_FIFO_FULL 426
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM10_FIFO_FULL 427
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM11_FIFO_FULL 428
|
|
#define CMDQ_EVENT_CAM_SENINF_CAM12_FIFO_FULL 429
|
|
|
|
#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF 431
|
|
#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF 432
|
|
#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF 433
|
|
#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF 434
|
|
#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1 435
|
|
#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1 436
|
|
#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT 437
|
|
#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT 438
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 439
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT2 440
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT3 441
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT4 442
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 443
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT2 444
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT3 445
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT4 446
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 447
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT2 448
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT3 449
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT4 450
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 451
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 452
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 453
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 454
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 455
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 456
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 457
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 458
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 459
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 460
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 461
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 462
|
|
#define CMDQ_EVENT_CAM_RAW_SEL_SOF_SUBA 463
|
|
#define CMDQ_EVENT_CAM_RAW_SEL_SOF_SUBB 464
|
|
#define CMDQ_EVENT_CAM_RAW_SEL_SOF_SUBC 465
|
|
#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP 466
|
|
#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 467
|
|
#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 468
|
|
#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 469
|
|
|
|
#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE 471
|
|
#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE 472
|
|
|
|
#define CMDQ_EVENT_GCE_EVENT_SMI_EVENT_0 898
|
|
#define CMDQ_EVENT_GCE_EVENT_SMI_EVENT_1 899
|
|
#define CMDQ_EVENT_GCE_EVENT_SMI_EVENT_2 900
|
|
#define CMDQ_MAX_HW_EVENT 512
|
|
/* end of hw event and begin of sw token */
|
|
|
|
|
|
/* CMDQ sw tokens
|
|
* Following definitions are gce sw token which may use by clients
|
|
* event operation API.
|
|
* Note that token 512 to 639 may set secure
|
|
*/
|
|
|
|
/* begin of GCE-D sw token */
|
|
/* MML sw tokens */
|
|
#define CMDQ_SYNC_TOKEN_MML_BUFA 630
|
|
#define CMDQ_SYNC_TOKEN_MML_BUFB 631
|
|
#define CMDQ_SYNC_TOKEN_MML_BUF_NEXT 632
|
|
#define CMDQ_SYNC_TOKEN_MML_IR_MML_READY 633
|
|
#define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY 634
|
|
#define CMDQ_SYNC_TOKEN_MML_MML_STOP 635
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE0 636
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE1 637
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE1_NEXT 638
|
|
|
|
/* Config thread notify trigger thread */
|
|
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
|
|
/* Trigger thread notify config thread */
|
|
#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
|
|
/* Block Trigger thread until the ESD check finishes. */
|
|
#define CMDQ_SYNC_TOKEN_ESD_EOF 642
|
|
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
|
|
/* check CABC setup finish */
|
|
#define CMDQ_SYNC_TOKEN_CABC_EOF 644
|
|
|
|
/*VFP period token for Msync*/
|
|
#define CMDQ_SYNC_TOKEN_VFP_PERIOD 645
|
|
/* SW sync token for dual display */
|
|
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694
|
|
#define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695
|
|
#define CMDQ_SYNC_TOKEN_ESD_EOF_1 696
|
|
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697
|
|
#define CMDQ_SYNC_TOKEN_CABC_EOF_1 698
|
|
|
|
/* GPR access tokens (for HW register backup)
|
|
* There are 15 32-bit GPR, 3 GPR form a set
|
|
* (64-bit for address, 32-bit for value)
|
|
* MUST NOT CHANGE, these tokens sync with MDP
|
|
*/
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
|
|
|
|
#define CMDQ_SYNC_TOKEN_TE_0 705
|
|
#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0 706
|
|
#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON 707
|
|
#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE 708
|
|
|
|
/* Resource lock event to control resource in GCE thread */
|
|
#define CMDQ_SYNC_RESOURCE_WROT0 710
|
|
#define CMDQ_SYNC_RESOURCE_WROT1 711
|
|
|
|
/* HW TRACE sw token */
|
|
#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712
|
|
#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713
|
|
|
|
/* SW sync token for dual display */
|
|
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714
|
|
#define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715
|
|
#define CMDQ_SYNC_TOKEN_ESD_EOF_3 716
|
|
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717
|
|
#define CMDQ_SYNC_TOKEN_CABC_EOF_3 718
|
|
/* end of GCE-D sw token */
|
|
|
|
/* begin of GCE-M sw token */
|
|
/* IMGSYS_POOL */
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 514
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 515
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 516
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 517
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 518
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 519
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 520
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 521
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 522
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 523
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 524
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 525
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 526
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 527
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 528
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 529
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 530
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 531
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 532
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 533
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 534
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 535
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 536
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 537
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 538
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 539
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 540
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 541
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 542
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 543
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 544
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 545
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 546
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 547
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 548
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 549
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 550
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 551
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 552
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 553
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 554
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 555
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 556
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 557
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 558
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 559
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 560
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 561
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 562
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 563
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 564
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 565
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 566
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 567
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 568
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 569
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 570
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 571
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 572
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 573
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_61 574
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_62 575
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_63 576
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_64 577
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_65 578
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_66 579
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_67 580
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_68 581
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_69 582
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_70 583
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_71 584
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_72 585
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_73 586
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_74 587
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_75 588
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_76 589
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_77 590
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_78 591
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_79 592
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_80 593
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_81 594
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_82 595
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_83 596
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_84 597
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_85 598
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_86 599
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_87 600
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_88 601
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_89 602
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_90 603
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_91 604
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_92 605
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_93 606
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_94 607
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_95 608
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_96 609
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_97 610
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_98 611
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_99 612
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_100 613
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_101 614
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_102 615
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_103 616
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_104 617
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_105 618
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_106 619
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_107 620
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_108 621
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_109 622
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_110 623
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_111 624
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_112 625
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_113 626
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_114 627
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_115 628
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_116 629
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_117 630
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_118 631
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_119 632
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_120 633
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_121 634
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_122 635
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_123 636
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_124 637
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_125 638
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_126 639
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_127 640
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_128 641
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_129 642
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_130 643
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_131 644
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_132 645
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_133 646
|
|
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_134 694
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_135 695
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_136 696
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_137 697
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_138 698
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_139 699
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_140 700
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_141 701
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_142 702
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_143 703
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_144 704
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_145 705
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_146 706
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_147 707
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_148 708
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_149 709
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_150 710
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_151 711
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_152 714
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_153 715
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_154 716
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_155 717
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_156 718
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_157 719
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_158 720
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_159 721
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_160 722
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_161 723
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_162 724
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_163 725
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_164 726
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_165 727
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_166 728
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_167 729
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_168 730
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_169 731
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_170 732
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_171 733
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_172 734
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_173 735
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_174 736
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_175 737
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_176 738
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_177 739
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_178 740
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_179 741
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_180 742
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_181 743
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_182 744
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_183 745
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_184 746
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_185 747
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_186 748
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_187 749
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_188 750
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_189 751
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_190 752
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_191 753
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_192 754
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_193 755
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_194 756
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_195 757
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_196 758
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_197 759
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_198 760
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_199 761
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_200 762
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_201 763
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_202 764
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_203 765
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_204 766
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_205 767
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_206 784
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_207 785
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_208 786
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_209 787
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_210 788
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_211 789
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_212 790
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_213 791
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_214 792
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_215 793
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_216 794
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_217 795
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_218 796
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_219 797
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_220 798
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_221 799
|
|
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_222 833
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_223 834
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_224 835
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_225 836
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_226 837
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_227 838
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_228 839
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_229 840
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_230 841
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_231 842
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_232 843
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_233 844
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_234 845
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_235 846
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_236 847
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_237 848
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_238 849
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_239 850
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_240 851
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_241 852
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_242 853
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_243 854
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_244 855
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_245 856
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_246 857
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_247 858
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_248 859
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_249 860
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_250 861
|
|
|
|
/* ISP sw token */
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 665
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 666
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 667
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 668
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 669
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 670
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 671
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 672
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 673
|
|
#define CMDQ_SYNC_TOKEN_IPESYS_ME 674
|
|
#define CMDQ_SYNC_TOKEN_APUSYS_APU 675
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 676
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 677
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 678
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 679
|
|
/* end of GCE-M sw token */
|
|
|
|
/* begin of common sw token */
|
|
|
|
/* Notify normal CMDQ there are some secure task done
|
|
* MUST NOT CHANGE, this token sync with secure world
|
|
*/
|
|
#define CMDQ_SYNC_SECURE_THR_EOF 647
|
|
|
|
/* CMDQ use sw token */
|
|
#define CMDQ_SYNC_TOKEN_USER_0 649
|
|
#define CMDQ_SYNC_TOKEN_USER_1 650
|
|
#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
|
|
#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
|
|
|
|
/* TZMP sw token */
|
|
#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 653
|
|
#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 654
|
|
#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 655
|
|
#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 656
|
|
#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 657
|
|
#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 658
|
|
#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 659
|
|
#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 660
|
|
|
|
/* PREBUILT sw token */
|
|
#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 682
|
|
#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 685
|
|
#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 688
|
|
#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 691
|
|
#define CMDQ_SYNC_TOKEN_DISP_VA_START 692
|
|
#define CMDQ_SYNC_TOKEN_DISP_VA_END 693
|
|
|
|
/* event for gpr timer, used in sleep and poll with timeout */
|
|
#define CMDQ_TOKEN_GPR_TIMER_R0 994
|
|
#define CMDQ_TOKEN_GPR_TIMER_R1 995
|
|
#define CMDQ_TOKEN_GPR_TIMER_R2 996
|
|
#define CMDQ_TOKEN_GPR_TIMER_R3 997
|
|
#define CMDQ_TOKEN_GPR_TIMER_R4 998
|
|
#define CMDQ_TOKEN_GPR_TIMER_R5 999
|
|
#define CMDQ_TOKEN_GPR_TIMER_R6 1000
|
|
#define CMDQ_TOKEN_GPR_TIMER_R7 1001
|
|
#define CMDQ_TOKEN_GPR_TIMER_R8 1002
|
|
#define CMDQ_TOKEN_GPR_TIMER_R9 1003
|
|
#define CMDQ_TOKEN_GPR_TIMER_R10 1004
|
|
#define CMDQ_TOKEN_GPR_TIMER_R11 1005
|
|
#define CMDQ_TOKEN_GPR_TIMER_R12 1006
|
|
#define CMDQ_TOKEN_GPR_TIMER_R13 1007
|
|
#define CMDQ_TOKEN_GPR_TIMER_R14 1008
|
|
#define CMDQ_TOKEN_GPR_TIMER_R15 1009
|
|
|
|
#define CMDQ_EVENT_MAX 0x3FF
|
|
/* end of common sw token */
|
|
/* CMDQ sw tokens END */
|
|
|
|
#endif
|