933 lines
40 KiB
C
933 lines
40 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*
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*/
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#ifndef _DT_BINDINGS_GCE_MT6886_H
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#define _DT_BINDINGS_GCE_MT6886_H
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/* assign timeout 0 also means default */
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#define CMDQ_NO_TIMEOUT 0xffffffff
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#define CMDQ_TIMEOUT_DEFAULT 1000
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/* GCE thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_1 1
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#define CMDQ_THR_PRIO_2 2
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#define CMDQ_THR_PRIO_3 3
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#define CMDQ_THR_PRIO_4 4
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#define CMDQ_THR_PRIO_5 5
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#define CMDQ_THR_PRIO_6 6
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#define CMDQ_THR_PRIO_HIGHEST 7
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/* CPR count in 32bit register */
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#define GCE_CPR_COUNT 1312
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/* GCE subsys table */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1502XXXX 4
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#define SUBSYS_1880XXXX 5
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#define SUBSYS_1881XXXX 6
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#define SUBSYS_1882XXXX 7
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#define SUBSYS_1883XXXX 8
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#define SUBSYS_1884XXXX 9
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#define SUBSYS_1000XXXX 10
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#define SUBSYS_1001XXXX 11
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#define SUBSYS_1002XXXX 12
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#define SUBSYS_1003XXXX 13
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#define SUBSYS_1004XXXX 14
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#define SUBSYS_1005XXXX 15
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#define SUBSYS_1020XXXX 16
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#define SUBSYS_1028XXXX 17
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#define SUBSYS_1700XXXX 18
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#define SUBSYS_1701XXXX 19
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#define SUBSYS_1702XXXX 20
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#define SUBSYS_1703XXXX 21
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#define SUBSYS_1800XXXX 22
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#define SUBSYS_1801XXXX 23
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#define SUBSYS_1802XXXX 24
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#define SUBSYS_1804XXXX 25
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#define SUBSYS_1805XXXX 26
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#define SUBSYS_1808XXXX 27
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#define SUBSYS_180aXXXX 28
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#define SUBSYS_180bXXXX 29
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#define SUBSYS_NO_SUPPORT 99
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/* GCE General Purpose Register (GPR) support
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* Leave note for scenario usage here
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*/
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/* GCE: write mask */
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#define GCE_GPR_R00 0x00
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#define GCE_GPR_R01 0x01
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/* MDP: P1: JPEG dest */
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#define GCE_GPR_R02 0x02
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#define GCE_GPR_R03 0x03
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/* MDP: PQ color */
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#define GCE_GPR_R04 0x04
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/* MDP: 2D sharpness */
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#define GCE_GPR_R05 0x05
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/* DISP: poll esd */
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#define GCE_GPR_R06 0x06
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#define GCE_GPR_R07 0x07
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/* MDP: P4: 2D sharpness dst */
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#define GCE_GPR_R08 0x08
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#define GCE_GPR_R09 0x09
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/* VCU: poll with timeout for GPR timer */
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#define GCE_GPR_R10 0x0A
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#define GCE_GPR_R11 0x0B
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/* CMDQ: debug */
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#define GCE_GPR_R12 0x0C
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#define GCE_GPR_R13 0x0D
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/* CMDQ: P7: debug */
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#define GCE_GPR_R14 0x0E
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#define GCE_GPR_R15 0x0F
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/* GCE-D hardware events */
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_SOF 64
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SOF 65
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#define CMDQ_EVENT_MDPSYS0_MDP_TDSHP0_SOF 66
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#define CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_SOF 67
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#define CMDQ_EVENT_MDPSYS0_MDP_COLOR0_SOF 68
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#define CMDQ_EVENT_MDPSYS0_MDP_COLOR1_SOF 69
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT0_SOF 70
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT1_SOF 71
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#define CMDQ_EVENT_MDPSYS0_MDP_FG0_SOF 72
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#define CMDQ_EVENT_MDPSYS0_MDP_FG1_SOF 73
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#define CMDQ_EVENT_MDPSYS0_MDP_DLI_ASYNC0_SOF 74
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#define CMDQ_EVENT_MDPSYS0_MDP_DLI_ASYNC1_SOF 75
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#define CMDQ_EVENT_MDPSYS0_MDP_DLO_ASYNC0_SOF 76
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#define CMDQ_EVENT_MDPSYS0_MDP_DLO_ASYNC1_SOF 77
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ2_SOF 78
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ3_SOF 79
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT2_SOF 80
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT3_SOF 81
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT3_FRAME_DONE 82
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT2_FRAME_DONE 83
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT1_FRAME_DONE 84
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT0_FRAME_DONE 85
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#define CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_FRAME_DONE 86
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#define CMDQ_EVENT_MDPSYS0_MDP_TDSHP0_FRAME_DONE 87
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ3_FRAME_DONE 88
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ2_FRAME_DONE 89
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ1_FRAME_DONE 90
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#define CMDQ_EVENT_MDPSYS0_MDP_RSZ0_FRAME_DONE 91
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_FRAME_DONE 92
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_FRAME_DONE 93
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#define CMDQ_EVENT_MDPSYS0_MDP_HDR1_FRAME_DONE 94
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#define CMDQ_EVENT_MDPSYS0_MDP_HDR0_FRAME_DONE 95
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#define CMDQ_EVENT_MDPSYS0_MDP_FG1_FRAME_DONE 96
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#define CMDQ_EVENT_MDPSYS0_MDP_FG0_FRAME_DONE 97
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#define CMDQ_EVENT_MDPSYS0_MDP_COLOR1_FRAME_DONE 98
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#define CMDQ_EVENT_MDPSYS0_MDP_COLOR0_FRAME_DONE 99
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#define CMDQ_EVENT_MDPSYS0_MDP_AAL1_FRAME_DONE 100
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#define CMDQ_EVENT_MDPSYS0_MDP_AAL0_FRAME_DONE 101
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_0 102
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_1 103
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_2 104
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_3 105
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_4 106
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_5 107
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_6 108
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_7 109
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_8 110
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_9 111
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_10 112
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_11 113
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_12 114
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_13 115
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_14 116
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#define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_15 117
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT3_SW_RST_DONE_ENG_EVENT 118
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 119
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 120
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#define CMDQ_EVENT_MDPSYS0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 121
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 122
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#define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 123
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#define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_0 124
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#define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_1 125
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#define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_2 126
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#define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_3 127
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_SOF 256
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_SOF 257
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_SOF 258
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#define CMDQ_EVENT_MMSYS_DISP_RSZ0_SOF 259
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#define CMDQ_EVENT_MMSYS_DISP_RDMA0_SOF 260
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#define CMDQ_EVENT_MMSYS_DISP_TDSHP0_SOF 261
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#define CMDQ_EVENT_MMSYS_DISP_C3D0_SOF 262
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#define CMDQ_EVENT_MMSYS_DISP_COLOR0_SOF 263
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#define CMDQ_EVENT_MMSYS_DISP_CCORR0_SOF 264
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#define CMDQ_EVENT_MMSYS_DISP_CCORR1_SOF 265
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#define CMDQ_EVENT_MMSYS_DISP_MDP_AAL0_SOF 266
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#define CMDQ_EVENT_MMSYS_DISP_AAL0_SOF 267
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#define CMDQ_EVENT_MMSYS_DISP_GAMMA0_SOF 268
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#define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_SOF 269
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#define CMDQ_EVENT_MMSYS_DISP_DITHER0_SOF 270
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#define CMDQ_EVENT_MMSYS_DISP_CHIST0_SOF 271
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#define CMDQ_EVENT_MMSYS_DISP_CHIST1_SOF 272
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#define CMDQ_EVENT_MMSYS_DISP_CM0_SOF 273
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#define CMDQ_EVENT_MMSYS_DISP_SPR0_SOF 274
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#define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE0_SOF 275
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#define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE1_SOF 276
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#define CMDQ_EVENT_MMSYS_DISP_MERGE0_SOF 277
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#define CMDQ_EVENT_MMSYS_DISP_DSI0_SOF 278
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#define CMDQ_EVENT_MMSYS_DISP_WDMA0_SOF 279
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#define CMDQ_EVENT_MMSYS_DISP_UFBC_WDMA0_SOF 280
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_NWCG_SOF 281
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_SOF 282
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#define CMDQ_EVENT_MMSYS_DISP_RDMA1_SOF 283
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#define CMDQ_EVENT_MMSYS_DISP_DP_INTF0_SOF 284
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#define CMDQ_EVENT_MMSYS_DISP_DPI0_SOF 285
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#define CMDQ_EVENT_MMSYS_DISP_WDMA1_SOF 286
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#define CMDQ_EVENT_MMSYS_DISP_Y2R0_SOF 287
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#define CMDQ_EVENT_MMSYS_INLINEROT0_SOF 288
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#define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC0_SOF 289
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#define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC1_SOF 290
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#define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC2_SOF 291
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#define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC3_SOF 292
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#define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC0_SOF 293
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#define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC1_SOF 294
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#define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC2_SOF 295
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#define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC3_SOF 296
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#define CMDQ_EVENT_MMSYS_DISP_PWM0_SOF 297
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_0 301
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_1 302
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_2 303
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_3 304
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_4 305
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_5 306
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_6 307
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_7 308
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_8 309
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_9 310
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_10 311
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#define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_11 312
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#define CMDQ_EVENT_MMSYS_DSI0_FRAME_DONE 313
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#define CMDQ_EVENT_MMSYS_DP_INTF0_FRAME_DONE 314
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#define CMDQ_EVENT_MMSYS_DISP_WDMA1_FRAME_DONE 315
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#define CMDQ_EVENT_MMSYS_DISP_WDMA0_FRAME_DONE 316
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#define CMDQ_EVENT_MMSYS_DISP_UFBC_WDMA0_FRAME_DONE 317
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#define CMDQ_EVENT_MMSYS_DISP_TDSHP0_FRAME_DONE 318
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#define CMDQ_EVENT_MMSYS_DISP_SPR0_FRAME_DONE 319
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#define CMDQ_EVENT_MMSYS_DISP_RSZ0_FRAME_DONE 320
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#define CMDQ_EVENT_MMSYS_DISP_RDMA1_FRAME_DONE 321
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#define CMDQ_EVENT_MMSYS_DISP_RDMA0_FRAME_DONE 322
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#define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_FRAME_DONE 323
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_FRAME_DONE 324
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_FRAME_DONE 325
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_FRAME_DONE 326
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_NWCG_FRAME_DONE 327
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_FRAME_DONE 328
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#define CMDQ_EVENT_MMSYS_DISP_MERGE0_FRAME_DONE 329
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#define CMDQ_EVENT_MMSYS_DISP_MDP_AAL0_FRAME_DONE 330
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#define CMDQ_EVENT_MMSYS_DISP_GAMMA0_FRAME_DONE 331
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#define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE1_FRAME_DONE 332
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#define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE 333
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#define CMDQ_EVENT_MMSYS_DISP_DPI0_FRAME_DONE 334
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#define CMDQ_EVENT_MMSYS_DISP_DITHER0_FRAME_DONE 335
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#define CMDQ_EVENT_MMSYS_DISP_COLOR0_FRAME_DONE 336
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#define CMDQ_EVENT_MMSYS_DISP_CM0_FRAME_DONE 337
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#define CMDQ_EVENT_MMSYS_DISP_CHIST1_FRAME_DONE 338
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#define CMDQ_EVENT_MMSYS_DISP_CHIST0_FRAME_DONE 339
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#define CMDQ_EVENT_MMSYS_DISP_CCORR1_FRAME_DONE 340
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#define CMDQ_EVENT_MMSYS_DISP_CCORR0_FRAME_DONE 341
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_0 342
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_1 343
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_2 344
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_3 345
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_4 346
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_5 347
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_6 348
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_7 349
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_8 350
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_9 351
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_10 352
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_11 353
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_12 354
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_13 355
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_14 356
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#define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_15 357
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#define CMDQ_EVENT_MMSYS_DSI0_TE_ENG_EVENT 358
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#define CMDQ_EVENT_MMSYS_DSI0_TARGET_LINE_ENG_EVENT 359
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#define CMDQ_EVENT_MMSYS_DSI0_IRQ_ENG_EVENT 360
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#define CMDQ_EVENT_MMSYS_DSI0_DONE_ENG_EVENT 361
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#define CMDQ_EVENT_MMSYS_DP_VSYNC_START_ENG_EVENT 362
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#define CMDQ_EVENT_MMSYS_DP_VSYNC_END_ENG_EVENT 363
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#define CMDQ_EVENT_MMSYS_DP_VDE_START_ENG_EVENT 364
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#define CMDQ_EVENT_MMSYS_DP_VDE_END_ENG_EVENT 365
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#define CMDQ_EVENT_MMSYS_DP_TARGET_LINE_ENG_EVENT 366
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#define CMDQ_EVENT_MMSYS_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 367
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#define CMDQ_EVENT_MMSYS_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 368
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#define CMDQ_EVENT_MMSYS_DISP_RDMA1_TARGET_LINE_ENG_EVENT 369
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#define CMDQ_EVENT_MMSYS_DISP_RDMA0_TARGET_LINE_ENG_EVENT 370
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#define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_RST_DONE_ENG_EVENT 371
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_RST_DONE_ENG_EVENT 372
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#define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_RST_DONE_ENG_EVENT 373
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_RST_DONE_ENG_EVENT 374
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#define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_RST_DONE_ENG_EVENT 375
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_0 376
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_1 377
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_2 378
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_3 379
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_4 380
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_5 381
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_6 382
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#define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_7 383
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#define CMDQ_EVENT_GCE_EVENT_DSI0_TE_I 898
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#define CMDQ_EVENT_GCE_EVENT_DSI1_TE_I 899
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/* GCE-M hardware events */
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#define CMDQ_EVENT_VENC1_EVENT_0 32
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#define CMDQ_EVENT_VENC1_EVENT_1 33
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#define CMDQ_EVENT_VENC1_EVENT_2 34
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#define CMDQ_EVENT_VENC1_EVENT_3 35
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#define CMDQ_EVENT_VENC1_EVENT_4 36
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#define CMDQ_EVENT_VENC1_EVENT_5 37
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#define CMDQ_EVENT_VENC1_EVENT_6 38
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#define CMDQ_EVENT_VENC1_EVENT_7 39
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#define CMDQ_EVENT_VENC1_EVENT_8 40
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#define CMDQ_EVENT_VENC1_EVENT_9 41
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#define CMDQ_EVENT_VENC1_EVENT_10 42
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#define CMDQ_EVENT_VENC1_EVENT_11 43
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#define CMDQ_EVENT_VENC1_EVENT_12 44
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#define CMDQ_EVENT_VENC1_EVENT_13 45
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#define CMDQ_EVENT_VENC1_EVENT_14 46
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#define CMDQ_EVENT_VENC1_EVENT_15 47
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#define CMDQ_EVENT_VENC1_EVENT_16 48
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#define CMDQ_EVENT_VDEC1_EVENT_0 96
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#define CMDQ_EVENT_VDEC1_EVENT_1 97
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#define CMDQ_EVENT_VDEC1_EVENT_2 98
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#define CMDQ_EVENT_VDEC1_EVENT_3 99
|
|
#define CMDQ_EVENT_VDEC1_EVENT_4 100
|
|
#define CMDQ_EVENT_VDEC1_EVENT_5 101
|
|
#define CMDQ_EVENT_VDEC1_EVENT_6 102
|
|
#define CMDQ_EVENT_VDEC1_EVENT_7 103
|
|
#define CMDQ_EVENT_VDEC1_EVENT_8 104
|
|
#define CMDQ_EVENT_VDEC1_EVENT_9 105
|
|
#define CMDQ_EVENT_VDEC1_EVENT_10 106
|
|
#define CMDQ_EVENT_VDEC1_EVENT_11 107
|
|
#define CMDQ_EVENT_VDEC1_EVENT_12 108
|
|
#define CMDQ_EVENT_VDEC1_EVENT_13 109
|
|
#define CMDQ_EVENT_VDEC1_EVENT_14 110
|
|
#define CMDQ_EVENT_VDEC1_EVENT_15 111
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP0_RDMA_SW_RST_DONE_ENG_EVENT 112
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP0_RDMA_TILE_DONE 113
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP0_WDMA_SW_RST_DONE_ENG_EVENT 114
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP0_WDMA_TILE_DONE 115
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP1_RDMA_SW_RST_DONE_ENG_EVENT 116
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP1_RDMA_TILE_DONE 117
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP1_WDMA_SW_RST_DONE_ENG_EVENT 118
|
|
#define CMDQ_EVENT_VDEC_FMT_MDP1_WDMA_TILE_DONE 119
|
|
|
|
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 129
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_1 130
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_2 131
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_3 132
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_4 133
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_5 134
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_6 135
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_7 136
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_8 137
|
|
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_9 138
|
|
#define CMDQ_EVENT_IMG_TRAW0_DIP_DMA_ERR_EVENT 139
|
|
#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0 140
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 141
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_1 142
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_2 143
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_3 144
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_4 145
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_5 146
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_6 147
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_7 148
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_8 149
|
|
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_9 150
|
|
#define CMDQ_EVENT_IMG_TRAW1_DIP_DMA_ERR_EVENT 151
|
|
#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 152
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_0 153
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_1 154
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_2 155
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_3 156
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_4 157
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_5 158
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_6 159
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_7 160
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_8 161
|
|
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_9 162
|
|
#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 163
|
|
#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 164
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_0 165
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_1 166
|
|
#define CMDQ_EVENT_IMG_DIP_DUMMY_2 167
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 168
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 169
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_0 170
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_1 171
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_2 172
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_3 173
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_4 174
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_5 175
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_6 176
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_7 177
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_8 178
|
|
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_9 179
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_0 180
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_1 181
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_2 182
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_3 183
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_4 184
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_5 185
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_6 186
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_7 187
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_8 188
|
|
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_9 189
|
|
#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 190
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_0 191
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_1 192
|
|
#define CMDQ_EVENT_IMG_WPE0_DUMMY_2 193
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 194
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 195
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_0 196
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_1 197
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_2 198
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_3 199
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_4 200
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_5 201
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_6 202
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_7 203
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_8 204
|
|
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_9 205
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_0 206
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_1 207
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_2 208
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_3 209
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_4 210
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_5 211
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_6 212
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_7 213
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_8 214
|
|
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_9 215
|
|
#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 216
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_0 217
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_1 218
|
|
#define CMDQ_EVENT_IMG_WPE1_DUMMY_2 219
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 220
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 221
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_0 222
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_1 223
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_2 224
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_3 225
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_4 226
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_5 227
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_6 228
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_7 229
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_8 230
|
|
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_9 231
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_0 232
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_1 233
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_2 234
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_3 235
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_4 236
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_5 237
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_6 238
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_7 239
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_8 240
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_CQ_THR_DONE_TRAW0_9 241
|
|
#define CMDQ_EVENT_IMG_RESERVE_XTRAW_DMA_ERR_EVENT 242
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_0 243
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_1 244
|
|
#define CMDQ_EVENT_IMG_WPE2_DUMMY_2 245
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 246
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 247
|
|
#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 248
|
|
|
|
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_SW_PASS1_DONE 385
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_SW_PASS1_DONE 386
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_SW_PASS1_DONE 387
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_A_SW_PASS1_DONE_0 388
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_A_SW_PASS1_DONE_1 389
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_A_SW_PASS1_DONE_2 390
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_A_SW_PASS1_DONE_3 391
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_B_SW_PASS1_DONE_0 392
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_B_SW_PASS1_DONE_1 393
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_B_SW_PASS1_DONE_2 394
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_B_SW_PASS1_DONE_3 395
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_C_SW_PASS1_DONE_0 396
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_C_SW_PASS1_DONE_1 397
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_C_SW_PASS1_DONE_2 398
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_C_SW_PASS1_DONE_3 399
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_D_SW_PASS1_DONE_0 400
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_D_SW_PASS1_DONE_1 401
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_D_SW_PASS1_DONE_2 402
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_D_SW_PASS1_DONE_3 403
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_E_SW_PASS1_DONE_0 404
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_E_SW_PASS1_DONE_1 405
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_E_SW_PASS1_DONE_2 406
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_E_SW_PASS1_DONE_3 407
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_F_SW_PASS1_DONE_0 408
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_F_SW_PASS1_DONE_1 409
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_F_SW_PASS1_DONE_2 410
|
|
#define CMDQ_EVENT_CAMSYS_CAMSV_F_SW_PASS1_DONE_3 411
|
|
#define CMDQ_EVENT_CAMSYS_MRAW_0_SW_PASS1_DONE 412
|
|
#define CMDQ_EVENT_CAMSYS_MRAW_1_SW_PASS1_DONE 413
|
|
#define CMDQ_EVENT_CAMSYS_MRAW_2_SW_PASS1_DONE 414
|
|
#define CMDQ_EVENT_CAMSYS_MRAW_3_SW_PASS1_DONE 415
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM0_FIFO_FULL 416
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM1_FIFO_FULL 417
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM2_FIFO_FULL 418
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM3_FIFO_FULL 419
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM4_FIFO_FULL 420
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM5_FIFO_FULL 421
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM6_FIFO_FULL 422
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM7_FIFO_FULL 423
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM8_FIFO_FULL 424
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM9_FIFO_FULL 425
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM10_FIFO_FULL 426
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM11_FIFO_FULL 427
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM12_FIFO_FULL 428
|
|
#define CMDQ_EVENT_CAMSYS_SENINF_CAM13_FIFO_FULL 429
|
|
#define CMDQ_EVENT_CAMSYS_TG_MRAW0_OUT_SOF 430
|
|
#define CMDQ_EVENT_CAMSYS_TG_MRAW1_OUT_SOF 431
|
|
#define CMDQ_EVENT_CAMSYS_TG_MRAW2_OUT_SOF 432
|
|
#define CMDQ_EVENT_CAMSYS_TG_MRAW3_OUT_SOF 433
|
|
#define CMDQ_EVENT_CAMSYS_PDA0_IRQO_EVENT_DONE_D1 434
|
|
#define CMDQ_EVENT_CAMSYS_PDA1_IRQO_EVENT_DONE_D1 435
|
|
#define CMDQ_EVENT_CAMSYS_DPE_DVP_CMQ_EVENT 436
|
|
#define CMDQ_EVENT_CAMSYS_DPE_DVS_CMQ_EVENT 437
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT1 438
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT2 439
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT3 440
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT4 441
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT1 442
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT2 443
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT3 444
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT4 445
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT1 446
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT2 447
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT3 448
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT4 449
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 450
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 451
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 452
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 453
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 454
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 455
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 456
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 457
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 458
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 459
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 460
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 461
|
|
#define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBA 462
|
|
#define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBB 463
|
|
#define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBC 464
|
|
#define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_UISP 465
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 466
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 467
|
|
#define CMDQ_EVENT_CAMSYS_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 468
|
|
#define CMDQ_EVENT_CAMSYS_DHZE_CMQ_EVENT 469
|
|
#define CMDQ_EVENT_CAMSYS_ADL_WR_FRAME_DONE 470
|
|
#define CMDQ_EVENT_CAMSYS_ADL_RD_FRAME_DONE 471
|
|
#define CMDQ_EVENT_CAMSYS_RESERVED 472
|
|
|
|
#define CMDQ_EVENT_GCE_EVENT_0 898
|
|
#define CMDQ_EVENT_GCE_EVENT_1 899
|
|
#define CMDQ_MAX_HW_EVENT 512
|
|
/* end of hw event and begin of sw token */
|
|
|
|
|
|
/* CMDQ sw tokens
|
|
* Following definitions are gce sw token which may use by clients
|
|
* event operation API.
|
|
* Note that token 512 to 639 may set secure
|
|
*/
|
|
|
|
/* begin of GCE-D sw token */
|
|
/* MML sw tokens */
|
|
#define CMDQ_SYNC_TOKEN_MML_BUFA 630
|
|
#define CMDQ_SYNC_TOKEN_MML_BUFB 631
|
|
#define CMDQ_SYNC_TOKEN_MML_BUF_NEXT 632
|
|
#define CMDQ_SYNC_TOKEN_MML_IR_MML_READY 633
|
|
#define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY 634
|
|
#define CMDQ_SYNC_TOKEN_MML_MML_STOP 635
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE0 636
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE1 637
|
|
#define CMDQ_SYNC_TOKEN_MML_PIPE1_NEXT 638
|
|
|
|
/* Config thread notify trigger thread */
|
|
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
|
|
/* Trigger thread notify config thread */
|
|
#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
|
|
/* Block Trigger thread until the ESD check finishes. */
|
|
#define CMDQ_SYNC_TOKEN_ESD_EOF 642
|
|
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
|
|
/* check CABC setup finish */
|
|
#define CMDQ_SYNC_TOKEN_CABC_EOF 644
|
|
|
|
/*VFP period token for Msync*/
|
|
#define CMDQ_SYNC_TOKEN_VFP_PERIOD 645
|
|
|
|
/* GPR access tokens (for HW register backup)
|
|
* There are 15 32-bit GPR, 3 GPR form a set
|
|
* (64-bit for address, 32-bit for value)
|
|
* MUST NOT CHANGE, these tokens sync with MDP
|
|
*/
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
|
|
|
|
/* Resource lock event to control resource in GCE thread */
|
|
#define CMDQ_SYNC_RESOURCE_WROT0 710
|
|
#define CMDQ_SYNC_RESOURCE_WROT1 711
|
|
|
|
/* HW TRACE sw token */
|
|
#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712
|
|
#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713
|
|
/* end of GCE-D sw token */
|
|
|
|
/* begin of GCE-M sw token */
|
|
/* IMGSYS_POOL */
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 514
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 515
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 516
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 517
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 518
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 519
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 520
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 521
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 522
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 523
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 524
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 525
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 526
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 527
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 528
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 529
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 530
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 531
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 532
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 533
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 534
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 535
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 536
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 537
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 538
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 539
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 540
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 541
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 542
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 543
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 544
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 545
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 546
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 547
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 548
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 549
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 550
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 551
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 552
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 553
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 554
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 555
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 556
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 557
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 558
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 559
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 560
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 561
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 562
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 563
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 564
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 565
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 566
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 567
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 568
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 569
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 570
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 571
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 572
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 573
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_61 574
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_62 575
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_63 576
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_64 577
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_65 578
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_66 579
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_67 580
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_68 581
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_69 582
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_70 583
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_71 584
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_72 585
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_73 586
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_74 587
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_75 588
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_76 589
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_77 590
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_78 591
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_79 592
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_80 593
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_81 594
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_82 595
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_83 596
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_84 597
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_85 598
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_86 599
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_87 600
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_88 601
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_89 602
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_90 603
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_91 604
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_92 605
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_93 606
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_94 607
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_95 608
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_96 609
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_97 610
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_98 611
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_99 612
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_100 613
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_101 614
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_102 615
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_103 616
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_104 617
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_105 618
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_106 619
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_107 620
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_108 621
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_109 622
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_110 623
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_111 624
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_112 625
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_113 626
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_114 627
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_115 628
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_116 629
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_117 630
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_118 631
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_119 632
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_120 633
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_121 634
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_122 635
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_123 636
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_124 637
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_125 638
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_126 639
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_127 640
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_128 641
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_129 642
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_130 643
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_131 644
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_132 645
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_133 646
|
|
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_134 694
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_135 695
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_136 696
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_137 697
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_138 698
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_139 699
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_140 700
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_141 701
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_142 702
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_143 703
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_144 704
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_145 705
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_146 706
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_147 707
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_148 708
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_149 709
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_150 710
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_151 711
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_152 714
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_153 715
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_154 716
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_155 717
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_156 718
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_157 719
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_158 720
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_159 721
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_160 722
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_161 723
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_162 724
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_163 725
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_164 726
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_165 727
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_166 728
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_167 729
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_168 730
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_169 731
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_170 732
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_171 733
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_172 734
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_173 735
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_174 736
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_175 737
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_176 738
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_177 739
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_178 740
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_179 741
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_180 742
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_181 743
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_182 744
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_183 745
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_184 746
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_185 747
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_186 748
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_187 749
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_188 750
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_189 751
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_190 752
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_191 753
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_192 754
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_193 755
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_194 756
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_195 757
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_196 758
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_197 759
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_198 760
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_199 761
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_200 762
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_201 763
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_202 764
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_203 765
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_204 766
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_205 767
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_206 784
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_207 785
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_208 786
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_209 787
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_210 788
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_211 789
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_212 790
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_213 791
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_214 792
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_215 793
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_216 794
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_217 795
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_218 796
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_219 797
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_220 798
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_221 799
|
|
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_222 833
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_223 834
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_224 835
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_225 836
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_226 837
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_227 838
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_228 839
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_229 840
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_230 841
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_231 842
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_232 843
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_233 844
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_234 845
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_235 846
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_236 847
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_237 848
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_238 849
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_239 850
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_240 851
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_241 852
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_242 853
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_243 854
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_244 855
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_245 856
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_246 857
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_247 858
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_248 859
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_249 860
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_250 861
|
|
|
|
/* ISP sw token */
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 665
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 666
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 667
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 668
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 669
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 670
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 671
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 672
|
|
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 673
|
|
#define CMDQ_SYNC_TOKEN_IPESYS_ME 674
|
|
#define CMDQ_SYNC_TOKEN_APUSYS_APU 675
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#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 676
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#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 677
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#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 678
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#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 679
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/* end of GCE-M sw token */
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/* begin of common sw token */
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/* Notify normal CMDQ there are some secure task done
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* MUST NOT CHANGE, this token sync with secure world
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*/
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#define CMDQ_SYNC_SECURE_THR_EOF 647
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/* CMDQ use sw token */
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#define CMDQ_SYNC_TOKEN_USER_0 649
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#define CMDQ_SYNC_TOKEN_USER_1 650
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#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
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#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
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/* TZMP sw token */
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#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 653
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#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 654
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#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 655
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#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 656
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#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 657
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#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 658
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#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 659
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#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 660
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/* PREBUILT sw token */
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#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 682
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#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 685
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#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 688
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#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 691
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#define CMDQ_SYNC_TOKEN_DISP_VA_START 692
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#define CMDQ_SYNC_TOKEN_DISP_VA_END 693
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/* histogram sw token */
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#define CMDQ_SYNC_TOKEN_HISTOGRAM_MDP_WAIT 694
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#define CMDQ_SYNC_TOKEN_HISTOGRAM_MDP_SET 695
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#define CMDQ_SYNC_TOKEN_HISTOGRAM_VENC_WAIT 696
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#define CMDQ_SYNC_TOKEN_HISTOGRAM_VENC_SET 697
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/* event for gpr timer, used in sleep and poll with timeout */
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#define CMDQ_TOKEN_GPR_TIMER_R0 994
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#define CMDQ_TOKEN_GPR_TIMER_R1 995
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#define CMDQ_TOKEN_GPR_TIMER_R2 996
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#define CMDQ_TOKEN_GPR_TIMER_R3 997
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#define CMDQ_TOKEN_GPR_TIMER_R4 998
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#define CMDQ_TOKEN_GPR_TIMER_R5 999
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#define CMDQ_TOKEN_GPR_TIMER_R6 1000
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#define CMDQ_TOKEN_GPR_TIMER_R7 1001
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#define CMDQ_TOKEN_GPR_TIMER_R8 1002
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#define CMDQ_TOKEN_GPR_TIMER_R9 1003
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#define CMDQ_TOKEN_GPR_TIMER_R10 1004
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#define CMDQ_TOKEN_GPR_TIMER_R11 1005
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#define CMDQ_TOKEN_GPR_TIMER_R12 1006
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#define CMDQ_TOKEN_GPR_TIMER_R13 1007
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#define CMDQ_TOKEN_GPR_TIMER_R14 1008
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#define CMDQ_TOKEN_GPR_TIMER_R15 1009
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#define CMDQ_EVENT_MAX 0x3FF
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/* end of common sw token */
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/* CMDQ sw tokens END */
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#endif
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