142 lines
5.3 KiB
C
142 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __SOC_MEDIATEK_SCPSYS_H
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#define __SOC_MEDIATEK_SCPSYS_H
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#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask, _ack_mask, \
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_ignore_clr_ack) { \
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.type = _type, \
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.set_ofs = _set_ofs, \
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.clr_ofs = _clr_ofs, \
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.en_ofs = _en_ofs, \
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.sta_ofs = _sta_ofs, \
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.mask = _mask, \
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.ack_mask = _ack_mask, \
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.ignore_clr_ack = _ignore_clr_ack, \
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}
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#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask) \
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_BUS_PROT(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask, _mask, false)
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#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask) \
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_BUS_PROT(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask, _mask, true)
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#define BUS_PROT_CON(_type, _set_ofs, _clr_ofs, \
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_en_ofs, _sta_ofs, _mask, _ack_mask) \
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_BUS_PROT(_type, 0x0, 0x0, \
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_en_ofs, _sta_ofs, _mask, _ack_mask, true)
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#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
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#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
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#define MT6873_TOP_AXI_PROT_EN_MD BIT(7)
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#define MT6873_TOP_AXI_PROT_EN_VDNR_MD (BIT(2) | BIT(14) | \
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BIT(22))
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#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
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#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
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#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
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BIT(28))
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#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
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BIT(7) | BIT(8))
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#define MT6853_TOP_AXI_PROT_EN_MD (BIT(7))
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#define MT6853_TOP_AXI_PROT_EN_VDNR_MD (BIT(2) | BIT(12) | \
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BIT(20))
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#define MT6853_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18))
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#define MT6853_TOP_AXI_PROT_EN_CONN_2ND (BIT(14))
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#define MT6853_TOP_AXI_PROT_EN_1_CONN (BIT(10))
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#define MT6853_TOP_AXI_PROT_EN_1_MFG1 (BIT(21))
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#define MT6853_TOP_AXI_PROT_EN_2_MFG1 (BIT(5) | BIT(6))
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#define MT6853_TOP_AXI_PROT_EN_MFG1 (BIT(21) | BIT(22))
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#define MT6853_TOP_AXI_PROT_EN_2_MFG1_2ND (BIT(7))
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#define MT6853_TOP_AXI_PROT_EN_MM_2_ISP (BIT(8))
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#define MT6853_TOP_AXI_PROT_EN_MM_2_ISP_2ND (BIT(9))
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#define MT6853_TOP_AXI_PROT_EN_MM_IPE (BIT(16))
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#define MT6853_TOP_AXI_PROT_EN_MM_IPE_2ND (BIT(17))
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#define MT6853_TOP_AXI_PROT_EN_MM_VDEC (BIT(24))
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#define MT6853_TOP_AXI_PROT_EN_MM_VDEC_2ND (BIT(25))
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#define MT6853_TOP_AXI_PROT_EN_MM_VENC (BIT(26))
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#define MT6853_TOP_AXI_PROT_EN_MM_VENC_2ND (BIT(27))
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#define MT6853_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
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BIT(10) | BIT(12) | \
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BIT(16) | BIT(24) | \
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BIT(26))
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#define MT6853_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8))
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#define MT6853_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23))
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#define MT6853_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \
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BIT(17) | BIT(25) | \
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BIT(27))
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#define MT6853_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9))
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#define MT6853_TOP_AXI_PROT_EN_2_AUDIO (BIT(4))
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#define MT6853_TOP_AXI_PROT_EN_2_ADSP_DORMANT (BIT(3))
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#define MT6853_TOP_AXI_PROT_EN_2_CAM (BIT(0))
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#define MT6853_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
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#define MT6853_TOP_AXI_PROT_EN_1_CAM (BIT(22))
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#define MT6853_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3))
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#define MT6853_TOP_AXI_PROT_EN_VDNR_CAM (BIT(19))
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#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
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#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
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#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
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#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23))
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#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18))
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#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14)
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#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)
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#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10)
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#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21)
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#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22)
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#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0)
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#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3)
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#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4)
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#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)
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#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7)
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#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
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#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
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BIT(10) | BIT(12) | \
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BIT(14) | BIT(16) | \
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BIT(24) | BIT(26))
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#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3))
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#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \
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BIT(15) | BIT(17) | \
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BIT(25) | BIT(27))
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#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14)
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#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15)
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#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16)
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#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17)
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#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24)
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#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25)
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#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26)
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#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27)
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#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8)
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#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12))
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#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9)
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#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13))
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#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12)
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#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
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#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
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struct bus_prot {
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u32 type;
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u32 set_ofs;
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u32 clr_ofs;
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u32 en_ofs;
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u32 sta_ofs;
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u32 mask;
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u32 ack_mask;
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bool ignore_clr_ack;
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};
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#endif /* __SOC_MEDIATEK_SCPSYS_H */
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