211 lines
8.3 KiB
C
211 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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#include "sspm_ipi_table.h"
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/*
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* mbox information
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*
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* mbdev :mbox device
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* irq_num:identity of mbox irq
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* id :mbox id
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* slot :how many slots that mbox used, up to 1GB
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* opt :option for mbox or share memory, 0:mbox, 1:share memory
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* enable :mbox status, 0:disable, 1: enable
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* is64d :mbox is64d status, 0:32d, 1: 64d
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* base :mbox base address
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* set_irq_reg : mbox set irq register
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* clr_irq_reg : mbox clear irq register
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* init_base_reg: mbox initialize register
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* send_status_reg: mbox send status register
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* recv_status_reg: mbox recv status register
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* mbox lock : lock of mbox
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*/
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struct mtk_mbox_info sspm_mbox_table[SSPM_MBOX_TOTAL] = {
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{0, 0, 0, 32, 0, 1, 0, 0, 0, 0, 0, 0, 0, { { { { 0 } } } } },
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{0, 0, 1, 32, 0, 1, 0, 0, 0, 0, 0, 0, 0, { { { { 0 } } } } },
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{0, 0, 2, 32, 0, 1, 0, 0, 0, 0, 0, 0, 0, { { { { 0 } } } } },
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{0, 0, 3, 32, 0, 1, 0, 0, 0, 0, 0, 0, 0, { { { { 0 } } } } },
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{0, 0, 4, 32, 0, 1, 0, 0, 0, 0, 0, 0, 0, { { { { 0 } } } } },
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};
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/*
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* mbox pin structure, this is for send defination,
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* ipi=endpoint=pin
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* mbox : (mbox number)mbox number of the pin, up to 16(plt)
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* offset : (slot)msg offset in share memory, up to 1024*4 KB(plt)
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* send_opt : (opt)send opt, 0:send ,1: send for response(plt)
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* lock : (lock)polling lock 0:unuse,1:used
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* msg_size : (slot)message size in words, 4 bytes alignment(plt)
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* pin_index : (bit offset)pin index in the mbox(plt)
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* chan_id : (u32) ipc channel id(plt)
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* mutex : (mutex)mutex for remote response
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* completion : (completion)completion for remote response
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* pin_lock : (spinlock_t)lock of the pin
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*/
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struct mtk_mbox_pin_send sspm_mbox_pin_send[] = {
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/* the following will use mbox 0 */
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{0, IPIS_C_PPM_OUT_OFFSET, 1, 0, IPIS_C_PPM_OUT_SIZE,
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IPIS_C_PPM_OUT_OFFSET, IPIS_C_PPM,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_QOS_OUT_OFFSET, 1, 0, IPIS_C_QOS_OUT_SIZE,
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IPIS_C_QOS_OUT_OFFSET, IPIS_C_QOS,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_PMIC_OUT_OFFSET, 1, 0, IPIS_C_PMIC_OUT_SIZE,
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IPIS_C_PMIC_OUT_OFFSET, IPIS_C_PMIC,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_MET_OUT_OFFSET, 1, 0, IPIS_C_MET_OUT_SIZE,
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IPIS_C_MET_OUT_OFFSET, IPIS_C_MET,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_THERMAL_OUT_OFFSET, 1, 0, IPIS_C_THERMAL_OUT_SIZE,
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IPIS_C_THERMAL_OUT_OFFSET, IPIS_C_THERMAL,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_GPU_DVFS_OUT_OFFSET, 1, 0, IPIS_C_GPU_DVFS_OUT_SIZE,
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IPIS_C_GPU_DVFS_OUT_OFFSET, IPIS_C_GPU_DVFS,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{0, IPIS_C_GPU_PM_OUT_OFFSET, 1, 0, IPIS_C_GPU_PM_OUT_SIZE,
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IPIS_C_GPU_PM_OUT_OFFSET, IPIS_C_GPU_PM,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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/* the following will use mbox 1 */
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{1, IPIS_C_PLATFORM_OUT_OFFSET, 1, 0, IPIS_C_PLATFORM_OUT_SIZE,
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IPIS_C_PLATFORM_OUT_OFFSET, IPIS_C_PLATFORM,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIS_C_SMI_OUT_OFFSET, 1, 0, IPIS_C_SMI_OUT_SIZE,
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IPIS_C_SMI_OUT_OFFSET, IPIS_C_SMI,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIS_C_CM_OUT_OFFSET, 1, 0, IPIS_C_CM_OUT_SIZE,
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IPIS_C_CM_OUT_OFFSET, IPIS_C_CM,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIS_C_SLBC_OUT_OFFSET, 1, 0, IPIS_C_SLBC_OUT_SIZE,
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IPIS_C_SLBC_OUT_OFFSET, IPIS_C_SLBC,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIS_C_SPM_SUSPEND_OUT_OFFSET, 1, 0, IPIS_C_SPM_SUSPEND_OUT_SIZE,
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IPIS_C_SPM_SUSPEND_OUT_OFFSET, IPIS_C_SPM_SUSPEND,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIR_C_MET_OUT_OFFSET, 1, 0, IPIR_C_MET_OUT_SIZE,
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IPIR_C_MET_OUT_OFFSET, IPIR_C_MET,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIR_C_GPU_DVFS_OUT_OFFSET, 1, 0, IPIR_C_GPU_DVFS_OUT_SIZE,
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IPIR_C_GPU_DVFS_OUT_OFFSET, IPIR_C_GPU_DVFS,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIR_C_PLATFORM_OUT_OFFSET, 1, 0, IPIR_C_PLATFORM_OUT_SIZE,
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IPIR_C_PLATFORM_OUT_OFFSET, IPIR_C_PLATFORM,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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{1, IPIR_C_SLBC_OUT_OFFSET, 1, 0, IPIR_C_SLBC_OUT_SIZE,
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IPIR_C_SLBC_OUT_OFFSET, IPIR_C_SLBC,
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{ { 0 } }, { 0 }, { { { { 0 } } } } },
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};
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/*
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* mbox pin structure, this is for receive defination,
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* ipi=endpoint=pin
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* mbox : (mbox number)mbox number of the pin, up to 16(plt)
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* offset : (slot)msg offset in share memory, up to 1024*4 KB(plt)
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* recv_opt : (opt)recv option, 0:receive ,1: response(plt)
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* lock : (lock)polling lock 0:unuse,1:used
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* buf_full_opt : (opt)buffer option 0:drop, 1:assert, 2:overwrite(plt)
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* cb_ctx_opt : (opt)callback option 0:isr context, 1:process context(plt)
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* msg_size : (slot)msg used slots in the mbox, 4 bytes alignment(plt)
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* pin_index : (bit offset)pin index in the mbox(plt)
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* chan_id : (u32) ipc channel id(plt)
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* notify : (completion)notify process
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* mbox_pin_cb: (cb)cb function
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* pin_buf : (void*)buffer point
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* prdata : (void*)private data
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* pin_lock: (spinlock_t)lock of the pin
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*/
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struct mtk_mbox_pin_recv sspm_mbox_pin_recv[] = {
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/* the following will use mbox 2 */
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{2, IPIR_I_QOS_IN_OFFSET, 0, 0, 1, 1,
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IPIR_I_QOS_IN_SIZE, IPIR_I_QOS_IN_OFFSET,
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IPIR_I_QOS, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIR_C_MET_IN_OFFSET, 0, 0, 1, 1,
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IPIR_C_MET_IN_SIZE, IPIR_C_MET_IN_OFFSET,
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IPIR_C_MET, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIR_C_GPU_DVFS_IN_OFFSET, 0, 0, 1, 1,
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IPIR_C_GPU_DVFS_IN_SIZE, IPIR_C_GPU_DVFS_IN_OFFSET,
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IPIR_C_GPU_DVFS, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIR_C_PLATFORM_IN_OFFSET, 0, 0, 1, 1,
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IPIR_C_PLATFORM_IN_SIZE, IPIR_C_PLATFORM_IN_OFFSET,
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IPIR_C_PLATFORM, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIR_C_SLBC_IN_OFFSET, 0, 0, 1, 1,
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IPIR_C_SLBC_IN_SIZE, IPIR_C_SLBC_IN_OFFSET,
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IPIR_C_SLBC, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_PPM_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_PPM_IN_SIZE, IPIS_C_PPM_IN_OFFSET,
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IPIS_C_PPM, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_QOS_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_QOS_IN_SIZE, IPIS_C_QOS_IN_OFFSET,
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IPIS_C_QOS, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_PMIC_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_PMIC_IN_SIZE, IPIS_C_PMIC_IN_OFFSET,
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IPIS_C_PMIC, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_MET_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_MET_IN_SIZE, IPIS_C_MET_IN_OFFSET,
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IPIS_C_MET, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_THERMAL_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_THERMAL_IN_SIZE, IPIS_C_THERMAL_IN_OFFSET,
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IPIS_C_THERMAL, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_GPU_DVFS_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_GPU_DVFS_IN_SIZE, IPIS_C_GPU_DVFS_IN_OFFSET,
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IPIS_C_GPU_DVFS, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_GPU_PM_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_GPU_PM_IN_SIZE, IPIS_C_GPU_PM_IN_OFFSET,
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IPIS_C_GPU_PM, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_PLATFORM_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_PLATFORM_IN_SIZE, IPIS_C_PLATFORM_IN_OFFSET,
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IPIS_C_PLATFORM, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_SMI_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_SMI_IN_SIZE, IPIS_C_SMI_IN_OFFSET,
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IPIS_C_SMI, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_CM_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_CM_IN_SIZE, IPIS_C_CM_IN_OFFSET,
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IPIS_C_CM, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_SLBC_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_SLBC_IN_SIZE, IPIS_C_SLBC_IN_OFFSET,
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IPIS_C_SLBC, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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{2, IPIS_C_SPM_SUSPEND_IN_OFFSET, 1, 0, 1, 0,
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IPIS_C_SPM_SUSPEND_IN_SIZE, IPIS_C_SPM_SUSPEND_IN_OFFSET,
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IPIS_C_SPM_SUSPEND, { 0 }, 0, 0, 0, { { { { 0 } } } },
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{ 0, 0, 0, 0, 0, 0 } },
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};
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#define SSPM_TOTAL_SEND_PIN (sizeof(sspm_mbox_pin_send) \
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/ sizeof(struct mtk_mbox_pin_send))
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#define SSPM_TOTAL_RECV_PIN (sizeof(sspm_mbox_pin_recv) \
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/ sizeof(struct mtk_mbox_pin_recv))
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struct mtk_mbox_device sspm_mboxdev = {
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.name = "sspm_mboxdev",
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.pin_recv_table = &sspm_mbox_pin_recv[0],
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.pin_send_table = &sspm_mbox_pin_send[0],
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.info_table = &sspm_mbox_table[0],
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.count = SSPM_MBOX_TOTAL,
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.recv_count = SSPM_TOTAL_RECV_PIN,
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.send_count = SSPM_TOTAL_SEND_PIN,
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};
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struct mtk_ipi_device sspm_ipidev = {
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.name = "sspm_ipidev",
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.id = IPI_DEV_SSPM,
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.mbdev = &sspm_mboxdev,
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.timeout_handler = sspm_ipi_timeout_cb,
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};
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