1003 lines
20 KiB
C
1003 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 MediaTek Inc.
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*/
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#ifndef __MBOOT_PARAMS_H__
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#define __MBOOT_PARAMS_H__
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#include <linux/console.h>
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#include <linux/pstore.h>
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enum AEE_FIQ_STEP_NUM {
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AEE_FIQ_STEP_COMMON_DIE_START = 64,
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AEE_FIQ_STEP_COMMON_DIE_LOCK,
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AEE_FIQ_STEP_COMMON_DIE_KASLR,
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AEE_FIQ_STEP_COMMON_DIE_SCP,
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AEE_FIQ_STEP_COMMON_DIE_TRACE,
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AEE_FIQ_STEP_COMMON_DIE_EMISC,
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AEE_FIQ_STEP_COMMON_DIE_CS,
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AEE_FIQ_STEP_COMMON_DIE_DONE
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};
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enum AEE_EXP_TYPE_NUM {
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AEE_EXP_TYPE_HWT = 1,
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AEE_EXP_TYPE_KE = 2,
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AEE_EXP_TYPE_NESTED_PANIC = 3,
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AEE_EXP_TYPE_SMART_RESET = 4,
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AEE_EXP_TYPE_HANG_DETECT = 5,
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AEE_EXP_TYPE_BL33_CRASH = 6,
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AEE_EXP_TYPE_BL2_EXT_CRASH = 7,
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AEE_EXP_TYPE_AEE_LK_CRASH = 8,
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AEE_EXP_TYPE_TFA_CRASH = 9,
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AEE_EXP_TYPE_PL_CRASH = 10,
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AEE_EXP_TYPE_GZ_CRASH = 11,
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AEE_EXP_TYPE_MAX_NUM = 16,
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};
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC)
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extern void aee_rr_rec_clk(int id, u32 val);
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extern void aee_rr_rec_exp_type(unsigned int type);
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extern unsigned int aee_rr_curr_exp_type(void);
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extern void aee_rr_rec_kick(uint32_t kick_bit);
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extern void aee_rr_rec_check(uint32_t check_bit);
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extern void aee_rr_rec_kaslr_offset(u64 value64);
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extern void aee_rr_rec_cpu_dvfs_vproc_big(u8 val);
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extern void aee_rr_rec_cpu_dvfs_vproc_little(u8 val);
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extern void aee_rr_rec_cpu_dvfs_oppidx(u8 val);
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extern void aee_rr_rec_cpu_dvfs_cci_oppidx(u8 val);
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extern void aee_rr_rec_cpu_dvfs_status(u8 val);
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extern void aee_rr_rec_cpu_dvfs_step(u8 val);
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extern void aee_rr_rec_cpu_dvfs_cb(u8 val);
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extern void aee_rr_rec_cpufreq_cb(u8 val);
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extern u8 aee_rr_curr_cpu_dvfs_oppidx(void);
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extern u8 aee_rr_curr_cpu_dvfs_cci_oppidx(void);
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extern u8 aee_rr_curr_cpu_dvfs_status(void);
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extern u8 aee_rr_curr_cpu_dvfs_step(void);
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extern u8 aee_rr_curr_cpu_dvfs_cb(void);
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extern u8 aee_rr_curr_cpufreq_cb(void);
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extern void aee_rr_rec_ptp_devinfo_0(u32 val);
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extern void aee_rr_rec_ptp_devinfo_1(u32 val);
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extern void aee_rr_rec_ptp_devinfo_2(u32 val);
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extern void aee_rr_rec_ptp_devinfo_3(u32 val);
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extern void aee_rr_rec_ptp_devinfo_4(u32 val);
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extern void aee_rr_rec_ptp_devinfo_5(u32 val);
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extern void aee_rr_rec_ptp_devinfo_6(u32 val);
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extern void aee_rr_rec_ptp_devinfo_7(u32 val);
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extern void aee_rr_rec_ptp_e0(u32 val);
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extern void aee_rr_rec_ptp_e1(u32 val);
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extern void aee_rr_rec_ptp_e2(u32 val);
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extern void aee_rr_rec_ptp_e3(u32 val);
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extern void aee_rr_rec_ptp_e4(u32 val);
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extern void aee_rr_rec_ptp_e5(u32 val);
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extern void aee_rr_rec_ptp_e6(u32 val);
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extern void aee_rr_rec_ptp_e7(u32 val);
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extern void aee_rr_rec_ptp_e8(u32 val);
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extern void aee_rr_rec_ptp_e9(u32 val);
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extern void aee_rr_rec_ptp_e10(u32 val);
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extern void aee_rr_rec_ptp_e11(u32 val);
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extern void aee_rr_rec_ptp_vboot(u64 val);
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extern void aee_rr_rec_ptp_cpu_big_volt(u64 val);
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extern void aee_rr_rec_ptp_cpu_big_volt_1(u64 val);
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extern void aee_rr_rec_ptp_cpu_big_volt_2(u64 val);
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extern void aee_rr_rec_ptp_cpu_big_volt_3(u64 val);
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extern void aee_rr_rec_ptp_gpu_volt(u64 val);
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extern void aee_rr_rec_ptp_gpu_volt_1(u64 val);
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extern void aee_rr_rec_ptp_gpu_volt_2(u64 val);
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extern void aee_rr_rec_ptp_gpu_volt_3(u64 val);
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extern void aee_rr_rec_ptp_cpu_little_volt(u64 val);
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extern void aee_rr_rec_ptp_cpu_little_volt_1(u64 val);
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extern void aee_rr_rec_ptp_cpu_little_volt_2(u64 val);
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extern void aee_rr_rec_ptp_cpu_little_volt_3(u64 val);
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extern void aee_rr_rec_ptp_cpu_2_little_volt(u64 val);
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extern void aee_rr_rec_ptp_cpu_2_little_volt_1(u64 val);
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extern void aee_rr_rec_ptp_cpu_2_little_volt_2(u64 val);
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extern void aee_rr_rec_ptp_cpu_2_little_volt_3(u64 val);
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extern void aee_rr_rec_ptp_cpu_cci_volt(u64 val);
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extern void aee_rr_rec_ptp_cpu_cci_volt_1(u64 val);
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extern void aee_rr_rec_ptp_cpu_cci_volt_2(u64 val);
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extern void aee_rr_rec_ptp_cpu_cci_volt_3(u64 val);
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extern void aee_rr_rec_ptp_temp(u64 val);
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extern void aee_rr_rec_ptp_status(u8 val);
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extern void aee_rr_rec_eem_pi_offset(u8 val);
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extern u32 aee_rr_curr_ptp_devinfo_0(void);
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extern u32 aee_rr_curr_ptp_devinfo_1(void);
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extern u32 aee_rr_curr_ptp_devinfo_2(void);
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extern u32 aee_rr_curr_ptp_devinfo_3(void);
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extern u32 aee_rr_curr_ptp_devinfo_4(void);
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extern u32 aee_rr_curr_ptp_devinfo_5(void);
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extern u32 aee_rr_curr_ptp_devinfo_6(void);
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extern u32 aee_rr_curr_ptp_devinfo_7(void);
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extern u32 aee_rr_curr_ptp_e0(void);
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extern u32 aee_rr_curr_ptp_e1(void);
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extern u32 aee_rr_curr_ptp_e2(void);
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extern u32 aee_rr_curr_ptp_e3(void);
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extern u32 aee_rr_curr_ptp_e4(void);
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extern u32 aee_rr_curr_ptp_e5(void);
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extern u32 aee_rr_curr_ptp_e6(void);
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extern u32 aee_rr_curr_ptp_e7(void);
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extern u32 aee_rr_curr_ptp_e8(void);
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extern u32 aee_rr_curr_ptp_e9(void);
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extern u32 aee_rr_curr_ptp_e10(void);
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extern u32 aee_rr_curr_ptp_e11(void);
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extern u64 aee_rr_curr_ptp_vboot(void);
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extern u64 aee_rr_curr_ptp_cpu_big_volt(void);
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extern u64 aee_rr_curr_ptp_cpu_big_volt_1(void);
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extern u64 aee_rr_curr_ptp_cpu_big_volt_2(void);
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extern u64 aee_rr_curr_ptp_cpu_big_volt_3(void);
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extern u64 aee_rr_curr_ptp_gpu_volt(void);
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extern u64 aee_rr_curr_ptp_gpu_volt_1(void);
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extern u64 aee_rr_curr_ptp_gpu_volt_2(void);
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extern u64 aee_rr_curr_ptp_gpu_volt_3(void);
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extern u64 aee_rr_curr_ptp_cpu_little_volt(void);
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extern u64 aee_rr_curr_ptp_cpu_little_volt_1(void);
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extern u64 aee_rr_curr_ptp_cpu_little_volt_2(void);
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extern u64 aee_rr_curr_ptp_cpu_little_volt_3(void);
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extern u64 aee_rr_curr_ptp_cpu_2_little_volt(void);
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extern u64 aee_rr_curr_ptp_cpu_2_little_volt_1(void);
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extern u64 aee_rr_curr_ptp_cpu_2_little_volt_2(void);
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extern u64 aee_rr_curr_ptp_cpu_2_little_volt_3(void);
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extern u64 aee_rr_curr_ptp_cpu_cci_volt(void);
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extern u64 aee_rr_curr_ptp_cpu_cci_volt_1(void);
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extern u64 aee_rr_curr_ptp_cpu_cci_volt_2(void);
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extern u64 aee_rr_curr_ptp_cpu_cci_volt_3(void);
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extern u64 aee_rr_curr_ptp_temp(void);
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extern u8 aee_rr_curr_ptp_status(void);
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extern unsigned long *aee_rr_rec_mtk_cpuidle_footprint_va(void);
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extern unsigned long *aee_rr_rec_mtk_cpuidle_footprint_pa(void);
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extern void aee_rr_rec_sodi3_val(u32 val);
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extern u32 aee_rr_curr_sodi3_val(void);
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extern void aee_rr_rec_sodi_val(u32 val);
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extern u32 aee_rr_curr_sodi_val(void);
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extern void aee_rr_rec_deepidle_val(u32 val);
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extern u32 aee_rr_curr_deepidle_val(void);
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extern void aee_rr_rec_spm_suspend_val(u32 val);
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extern u32 aee_rr_curr_spm_suspend_val(void);
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extern void aee_rr_rec_vcore_dvfs_status(u32 val);
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extern u32 aee_rr_curr_vcore_dvfs_status(void);
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extern unsigned int *aee_rr_rec_mcdi_wfi(void);
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extern void aee_rr_rec_mcdi_val(int id, u32 val);
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extern void aee_rr_rec_vcore_dvfs_opp(u32 val);
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extern u32 aee_rr_curr_vcore_dvfs_opp(void);
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extern void aee_rr_rec_ocp_target_limit(int id, u32 val);
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extern u32 aee_rr_curr_ocp_target_limit(int id);
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extern void aee_rr_rec_ocp_enable(u8 val);
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extern u8 aee_rr_curr_ocp_enable(void);
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extern void aee_rr_rec_ppm_cluster_limit(int id, u32 val);
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extern void aee_rr_rec_ppm_step(u8 val);
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extern void aee_rr_rec_ppm_cur_state(u8 val);
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extern void aee_rr_rec_ppm_min_pwr_bgt(u32 val);
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extern void aee_rr_rec_ppm_policy_mask(u32 val);
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extern void aee_rr_rec_ppm_waiting_for_pbm(u8 val);
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extern void aee_rr_rec_gpu_dvfs_vgpu(u8 val);
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extern u8 aee_rr_curr_gpu_dvfs_vgpu(void);
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extern void aee_rr_rec_gpu_dvfs_oppidx(u8 val);
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extern void aee_rr_rec_gpu_dvfs_status(u8 val);
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extern u8 aee_rr_curr_gpu_dvfs_status(void);
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extern void aee_rr_rec_gpu_dvfs_power_count(int val);
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extern void aee_rr_rec_hang_detect_timeout_count(unsigned int val);
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extern int aee_rr_curr_fiq_step(void);
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extern void aee_rr_rec_fiq_step(u8 i);
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extern void aee_rr_rec_last_irq_enter(int cpu, int irq, u64 j);
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extern void aee_rr_rec_last_irq_exit(int cpu, int irq, u64 j);
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extern void aee_rr_rec_hotplug_footprint(int cpu, u8 fp);
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extern void aee_rr_rec_hotplug_cpu_event(u8 val);
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extern void aee_rr_rec_hotplug_cb_index(u8 val);
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extern void aee_rr_rec_hotplug_cb_fp(unsigned long val);
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extern void aee_rr_rec_hotplug_cb_times(unsigned long val);
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extern void aee_rr_rec_hps_cb_enter_times(unsigned long long val);
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extern void aee_rr_rec_hps_cb_cpu_bitmask(unsigned int val);
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extern void aee_rr_rec_hps_cb_footprint(unsigned int val);
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extern void aee_rr_rec_hps_cb_fp_times(unsigned long long val);
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extern void aee_rr_rec_last_init_func(unsigned long val);
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extern void aee_rr_rec_last_sync_func(unsigned long val);
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extern void aee_rr_rec_last_async_func(unsigned long val);
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extern void aee_rr_rec_set_bit_pmic_ext_buck(int bit, int loc);
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extern int aee_rr_init_thermal_temp(int num);
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extern int aee_rr_rec_thermal_temp(int index, s8 val);
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extern void aee_rr_rec_thermal_status(u8 val);
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extern void aee_rr_rec_thermal_ATM_status(u8 val);
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extern void aee_rr_rec_thermal_ktime(u64 val);
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extern s8 aee_rr_curr_thermal_temp(int index);
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extern u8 aee_rr_curr_thermal_status(void);
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extern u8 aee_rr_curr_thermal_ATM_status(void);
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extern u64 aee_rr_curr_thermal_ktime(void);
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extern void aee_rr_rec_cpu_caller(u32 val);
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extern void aee_rr_rec_cpu_callee(u32 val);
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extern void aee_rr_rec_cpu_up_prepare_ktime(u64 val);
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extern void aee_rr_rec_cpu_starting_ktime(u64 val);
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extern void aee_rr_rec_cpu_online_ktime(u64 val);
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extern void aee_rr_rec_cpu_down_prepare_ktime(u64 val);
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extern void aee_rr_rec_cpu_dying_ktime(u64 val);
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extern void aee_rr_rec_cpu_dead_ktime(u64 val);
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extern void aee_rr_rec_cpu_post_dead_ktime(u64 val);
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extern void aee_sram_fiq_log(const char *msg);
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extern void aee_rr_rec_wdk_ktime(u64 val);
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extern void aee_rr_rec_wdk_systimer_cnt(u64 val);
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#else
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static inline void aee_rr_rec_clk(int id, u32 val)
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{
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}
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static inline void aee_rr_rec_exp_type(unsigned int type)
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{
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}
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static inline unsigned int aee_rr_curr_exp_type(void)
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{
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return 0;
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}
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static inline void aee_rr_rec_kick(uint32_t kick_bit)
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{
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}
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static inline void aee_rr_rec_check(uint32_t check_bit)
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{
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}
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static inline void aee_rr_rec_kaslr_offset(u64 value64)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_vproc_big(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_vproc_little(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_oppidx(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_cci_oppidx(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_status(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_step(u8 val)
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{
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}
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static inline void aee_rr_rec_cpu_dvfs_cb(u8 val)
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{
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}
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static inline void aee_rr_rec_cpufreq_cb(u8 val)
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{
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}
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static inline u8 aee_rr_curr_cpu_dvfs_oppidx(void)
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{
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return 0;
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}
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static inline u8 aee_rr_curr_cpu_dvfs_cci_oppidx(void)
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{
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return 0;
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}
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static inline u8 aee_rr_curr_cpu_dvfs_status(void)
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{
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return 0;
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}
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static inline u8 aee_rr_curr_cpu_dvfs_step(void)
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{
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return 0;
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}
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static inline u8 aee_rr_curr_cpu_dvfs_cb(void)
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{
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return 0;
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}
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static inline u8 aee_rr_curr_cpufreq_cb(void)
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{
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return 0;
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}
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static inline void aee_rr_rec_ptp_devinfo_0(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_1(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_2(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_3(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_4(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_5(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_6(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_devinfo_7(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e0(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e1(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e2(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e3(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e4(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e5(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e6(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e7(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e8(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e9(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e10(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_e11(u32 val)
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{
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}
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static inline void aee_rr_rec_ptp_vboot(u64 val)
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{
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}
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static inline void aee_rr_rec_ptp_cpu_big_volt(u64 val)
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{
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}
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static inline void aee_rr_rec_ptp_cpu_big_volt_1(u64 val)
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{
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}
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static inline void aee_rr_rec_ptp_cpu_big_volt_2(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_big_volt_3(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_gpu_volt(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_gpu_volt_1(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_gpu_volt_2(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_gpu_volt_3(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_little_volt(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_little_volt_1(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_little_volt_2(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_little_volt_3(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_2_little_volt(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_2_little_volt_1(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_2_little_volt_2(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_2_little_volt_3(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_cci_volt(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_cci_volt_1(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_cci_volt_2(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_cpu_cci_volt_3(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_temp(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ptp_status(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_eem_pi_offset(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_0(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_4(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_5(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_6(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_devinfo_7(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e0(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e4(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e5(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e6(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e7(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e8(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e9(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e10(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ptp_e11(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_vboot(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_big_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_big_volt_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_big_volt_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_big_volt_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_gpu_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_gpu_volt_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_gpu_volt_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_gpu_volt_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_little_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_little_volt_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_little_volt_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_little_volt_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_2_little_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_2_little_volt_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_2_little_volt_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_2_little_volt_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_cci_volt(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_cci_volt_1(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_cci_volt_2(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_cpu_cci_volt_3(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_ptp_temp(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_ptp_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline unsigned long *aee_rr_rec_mtk_cpuidle_footprint_va(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline unsigned long *aee_rr_rec_mtk_cpuidle_footprint_pa(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline void aee_rr_rec_sodi3_val(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_sodi3_val(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_sodi_val(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_sodi_val(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_deepidle_val(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_deepidle_val(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_spm_suspend_val(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_spm_suspend_val(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_vcore_dvfs_status(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_vcore_dvfs_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline unsigned int *aee_rr_rec_mcdi_wfi(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline void aee_rr_rec_mcdi_val(int id, u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_vcore_dvfs_opp(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_vcore_dvfs_opp(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_ocp_target_limit(int id, u32 val)
|
|
{
|
|
}
|
|
|
|
static inline u32 aee_rr_curr_ocp_target_limit(int id)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_ocp_enable(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_ocp_enable(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_cluster_limit(int id, u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_step(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_cur_state(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_min_pwr_bgt(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_policy_mask(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_ppm_waiting_for_pbm(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_gpu_dvfs_vgpu(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_gpu_dvfs_vgpu(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_gpu_dvfs_oppidx(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_gpu_dvfs_status(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_gpu_dvfs_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_gpu_dvfs_power_count(int val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hang_detect_timeout_count(unsigned int val)
|
|
{
|
|
}
|
|
|
|
static inline int aee_rr_curr_fiq_step(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_fiq_step(u8 i)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_last_irq_enter(int cpu, int irq, u64 j)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_last_irq_exit(int cpu, int irq, u64 j)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hotplug_footprint(int cpu, u8 fp)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hotplug_cpu_event(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hotplug_cb_index(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hotplug_cb_fp(unsigned long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hotplug_cb_times(unsigned long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hps_cb_enter_times(unsigned long long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hps_cb_cpu_bitmask(unsigned int val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hps_cb_footprint(unsigned int val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_hps_cb_fp_times(unsigned long long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_last_init_func(unsigned long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_last_sync_func(unsigned long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_last_async_func(unsigned long val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_set_bit_pmic_ext_buck(int bit, int loc)
|
|
{
|
|
}
|
|
|
|
static inline int aee_rr_init_thermal_temp(int num)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int aee_rr_rec_thermal_temp(int index, s8 val)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_thermal_status(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_thermal_ATM_status(u8 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_thermal_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline s8 aee_rr_curr_thermal_temp(int index)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_thermal_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 aee_rr_curr_thermal_ATM_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 aee_rr_curr_thermal_ktime(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_caller(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_callee(u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_up_prepare_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_starting_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_online_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_down_prepare_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_dying_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_dead_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_cpu_post_dead_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_sram_fiq_log(const char *msg)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_wdk_ktime(u64 val)
|
|
{
|
|
}
|
|
|
|
static inline void aee_rr_rec_wdk_systimer_cnt(u64 val)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_MTK_AEE_IPANIC */
|
|
|
|
#endif
|