190 lines
2.9 KiB
C
190 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019 MediaTek Inc. */
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#ifndef __ADAPTOR_DEF_H__
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#define __ADAPTOR_DEF_H__
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#define MODE_MAXCNT 25
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#define OF_SENSOR_NAMES_MAXCNT 20
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//#define POWERON_ONCE_OPENED
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#define IMGSENSOR_DEBUG
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#define OF_SENSOR_NAME_PREFIX "sensor"
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#define IMGSENSOR_LOG_MORE 0
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enum {
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CLK_6M = 0,
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CLK_12M,
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CLK_13M,
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CLK_19_2M,
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CLK_24M,
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CLK_26M,
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CLK_52M,
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CLK_MCLK,
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CLK1_6M,
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CLK1_12M,
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CLK1_13M,
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CLK1_19_2M,
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CLK1_24M,
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CLK1_26M,
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CLK1_26M_ULPOSC,
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CLK1_52M,
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CLK1_MCLK1,
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CLK_MAXCNT,
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};
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#define ADAPTOR_CLK_NAMES \
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"6", \
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"12", \
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"13", \
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"19.2", \
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"24", \
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"26", \
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"52", \
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"mclk", \
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"clk1_6", \
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"clk1_12", \
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"clk1_13", \
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"clk1_19.2", \
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"clk1_24", \
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"clk1_26", \
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"clk1_26_ulposc", \
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"clk1_52", \
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"clk1_mclk1", \
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enum {
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STATE_MCLK_OFF = 0,
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STATE_MCLK_2MA,
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STATE_MCLK_4MA,
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STATE_MCLK_6MA,
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STATE_MCLK_8MA,
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STATE_RST_LOW,
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STATE_RST_HIGH,
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STATE_PDN_LOW,
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STATE_PDN_HIGH,
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STATE_MIPI_SWITCH_OFF,
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STATE_MIPI_SWITCH_ON,
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STATE_AVDD_OFF,
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STATE_AVDD_ON,
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STATE_DVDD_OFF,
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STATE_DVDD_ON,
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STATE_DOVDD_OFF,
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STATE_DOVDD_ON,
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STATE_AFVDD_OFF,
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STATE_AFVDD_ON,
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STATE_AFVDD1_OFF,
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STATE_AFVDD1_ON,
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STATE_AVDD1_OFF,
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STATE_AVDD1_ON,
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STATE_AVDD2_OFF,
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STATE_AVDD2_ON,
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STATE_MCLK1_OFF,
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STATE_MCLK1_2MA,
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STATE_MCLK1_4MA,
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STATE_MCLK1_6MA,
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STATE_MCLK1_8MA,
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STATE_DVDD1_OFF,
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STATE_DVDD1_ON,
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STATE_RST1_LOW,
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STATE_RST1_HIGH,
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STATE_PONV_LOW,
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STATE_PONV_HIGH,
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STATE_SCL_AP,
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STATE_SCL_SCP,
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STATE_SDA_AP,
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STATE_SDA_SCP,
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STATE_EINT,
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STATE_MAXCNT,
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};
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#define ADAPTOR_STATE_NAMES \
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"mclk_off", \
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"mclk_2mA", \
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"mclk_4mA", \
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"mclk_6mA", \
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"mclk_8mA", \
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"rst_low", \
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"rst_high", \
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"pdn_low", \
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"pdn_high", \
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"mipi_switch_off", \
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"mipi_switch_on", \
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"avdd_off", \
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"avdd_on", \
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"dvdd_off", \
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"dvdd_on", \
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"dovdd_off", \
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"dovdd_on", \
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"afvdd_off", \
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"afvdd_on", \
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"afvdd1_off", \
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"afvdd1_on", \
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"avdd1_off", \
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"avdd1_on", \
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"avdd2_off", \
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"avdd2_on", \
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"mclk1_off", \
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"mclk1_2mA", \
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"mclk1_4mA", \
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"mclk1_6mA", \
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"mclk1_8mA", \
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"dvdd1_off", \
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"dvdd1_on", \
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"rst1_low", \
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"rst1_high", \
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"ponv_low", \
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"ponv_high", \
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"scl_ap", \
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"scl_scp", \
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"sda_ap", \
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"sda_scp", \
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"eint", \
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enum {
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REGULATOR_AVDD = 0,
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REGULATOR_DVDD,
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REGULATOR_DOVDD,
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REGULATOR_AFVDD,
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REGULATOR_AFVDD1,
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REGULATOR_AVDD1,
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REGULATOR_AVDD2,
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REGULATOR_DVDD1,
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REGULATOR_RST,
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REGULATOR_MAXCNT,
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};
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#define ADAPTOR_REGULATOR_NAMES \
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"avdd", \
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"dvdd", \
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"dovdd", \
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"afvdd", \
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"afvdd1", \
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"avdd1", \
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"avdd2", \
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"dvdd1", \
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"rst", \
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/* Format code util */
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#define to_std_fmt_code(code) \
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((code) & 0xFFFF)
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#define to_mtk_ext_fmt_code(stdcode, mode) \
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(0x10000000 | (((mode) & 0xFF) << 16) | to_std_fmt_code(stdcode))
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#define set_std_parts_fmt_code(code, stdcode) \
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{ \
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code = (((code) & 0xFFFF0000) | to_std_fmt_code(stdcode)); \
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}
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#define is_mtk_ext_fmt_code(code) \
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(((code) >> 28) == 0x1)
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#define get_sensor_mode_from_fmt_code(code) \
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({ \
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int __val = 0; \
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__val = ((code) >> 16) & 0xFF; \
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__val; \
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})
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#endif
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