349 lines
14 KiB
C
349 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc.
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*/
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#ifndef __GPUFREQ_MT6835_H__
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#define __GPUFREQ_MT6835_H__
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/**************************************************
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* GPUFREQ Config
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**************************************************/
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/*
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* 0 -> power on once then never off and disable DDK power on/off callback
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*/
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#define GPUFREQ_POWER_CTRL_ENABLE (1)
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/*
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* (DVFS_ENABLE, CUST_INIT)
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* (1, 1) -> DVFS enable and init to CUST_INIT_OPPIDX
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* (1, 0) -> DVFS enable
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* (0, 1) -> DVFS disable but init to CUST_INIT_OPPIDX (do DVFS only onces)
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* (0, 0) -> DVFS disable
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*/
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#define GPUFREQ_DVFS_ENABLE (1)
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#define GPUFREQ_CUST_INIT_ENABLE (0)
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#define GPUFREQ_CUST_INIT_OPPIDX (0)
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/* MFGSYS Feature */
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#define GPUFREQ_HWDCM_ENABLE (1)
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#define GPUFREQ_VCORE_DVFS_ENABLE (1)
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#define GPUFREQ_MERGER_ENABLE (1)
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#define GPUFREQ_AVS_ENABLE (1)
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#define GPUFREQ_ASENSOR_ENABLE (0)
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#define GPUFREQ_SELF_CTRL_MTCMOS (1)
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#define GPUFREQ_SHARED_STATUS_REG (0)
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#define GPUFREQ_TEMPER_COMP_ENABLE (1)
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/**************************************************
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* Clock Setting
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**************************************************/
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#define POSDIV_2_MAX_FREQ (1900000) /* KHz */
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#define POSDIV_2_MIN_FREQ (750000) /* KHz */
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#define POSDIV_4_MAX_FREQ (950000) /* KHz */
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#define POSDIV_4_MIN_FREQ (375000) /* KHz */
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#define POSDIV_8_MAX_FREQ (475000) /* KHz */
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#define POSDIV_8_MIN_FREQ (187500) /* KHz */
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#define POSDIV_16_MAX_FREQ (237500) /* KHz */
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#define POSDIV_16_MIN_FREQ (125000) /* KHz */
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#define POSDIV_SHIFT (24) /* bit */
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#define DDS_SHIFT (14) /* bit */
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#define TO_MHZ_HEAD (100)
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#define TO_MHZ_TAIL (10)
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#define ROUNDING_VALUE (5)
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#define MFGPLL_FIN (26) /* MHz */
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#define MFG_PLL_SEL_MASK (BIT(16)) /* [16] */
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#define MFG_REF_SEL_MASK (GENMASK(17, 16)) /* [17:16] */
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/**************************************************
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* Frequency Hopping Setting
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**************************************************/
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#define GPUFREQ_FHCTL_ENABLE (1)
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#define MFG_PLL_NAME "mfgpll"
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/**************************************************
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* Power Domain Setting
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**************************************************/
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#define GPUFREQ_CHECK_MTCMOS_PWR_STATUS (0)
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#define MFG_0_1_PWR_MASK (0x6) /* 0000 0110 */
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#define MFG_0_3_PWR_MASK (0x1E) /* 0001 1110 */
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#define MFG_1_3_PWR_MASK (0x1C) /* 0001 1100 */
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/**************************************************
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* Shader Core Setting
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**************************************************/
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#define MFG2_SHADER_STACK0 (T0C0) /* MFG2 */
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#define MFG3_SHADER_STACK2 (T2C0) /* MFG3 */
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#define GPU_SHADER_PRESENT_1 \
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(MFG2_SHADER_STACK0)
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#define GPU_SHADER_PRESENT_2 \
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(MFG2_SHADER_STACK0 | MFG3_SHADER_STACK2)
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#define SHADER_CORE_NUM (2)
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struct gpufreq_core_mask_info g_core_mask_table[] = {
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{2, GPU_SHADER_PRESENT_2},
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{1, GPU_SHADER_PRESENT_1},
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};
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/**************************************************
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* Reference Power Setting
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**************************************************/
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#define GPU_ACT_REF_POWER (977) /* mW */
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#define GPU_ACT_REF_FREQ (1100000) /* KHz */
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#define GPU_ACT_REF_VOLT (85000) /* mV x 100 */
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#define GPU_LEAKAGE_POWER (30)
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/**************************************************
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* PMIC Setting
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**************************************************/
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/*
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* PMIC hardware range:
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* VCORE 0.4 ~ 1.19375 V (MT6363 VBUCK2)
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* VGPU 0.4 ~ 1.19375 V (MT6363 VBUCK5)
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* VSRAM 0.4 ~ 1.19375 V (MT6363 VBUCK4)
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*/
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#define VGPU_MAX_VOLT (119375) /* mV x 100 */
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#define VGPU_MIN_VOLT (40000) /* mV x 100 */
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#define VSRAM_MAX_VOLT (119375) /* mV x 100 */
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#define VSRAM_MIN_VOLT (40000) /* mV x 100 */
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#define PMIC_STEP (625) /* mV x 100 */
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#define VGPU_LEVEL_0 (55000) /* mV x 100 */
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#define VOLT_NORMALIZATION(volt) \
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((volt % 625) ? (volt - (volt % 625) + 625) : volt)
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/**************************************************
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* SRAM Setting
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**************************************************/
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#define VSRAM_LEVEL_0 (75000)
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#define VSRAM_LEVEL_1 (80000)
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#define VSRAM_LEVEL_2 (85000)
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#define SRAM_PARK_VOLT (75000)
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/**************************************************
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* DVFSRC Setting
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**************************************************/
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#define MAX_VCORE_LEVEL (3)
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#define VCORE_LEVEL_0 (55000)
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#define VCORE_LEVEL_1 (60000)
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#define VCORE_LEVEL_2 (65000)
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#define VCORE_LEVEL_3 (72500)
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/**************************************************
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* Power Throttling Setting
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**************************************************/
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#define GPUFREQ_BATT_OC_ENABLE (1)
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#define GPUFREQ_LOW_BATT_ENABLE (1)
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#define GPUFREQ_BATT_OC_FREQ (467000)
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#define GPUFREQ_LOW_BATT_FREQ (467000)
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/**************************************************
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* Aging Sensor Setting
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**************************************************/
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#define GPUFREQ_AGING_KEEP_FGPU (660000)
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#define GPUFREQ_AGING_KEEP_VGPU (65000)
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#define GPUFREQ_AGING_LKG_VGPU (70000)
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#define GPUFREQ_AGING_KEEP_VSRAM (65000)
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#define GPUFREQ_AGING_LKG_VGPU (70000)
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#define GPUFREQ_AGING_GAP_MIN (-3)
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#define GPUFREQ_AGING_GAP_1 (2)
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#define GPUFREQ_AGING_GAP_2 (4)
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#define GPUFREQ_AGING_GAP_3 (6)
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#define GPUFREQ_AGING_MAX_TABLE_IDX (1)
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#define GPUFREQ_AGING_MOST_AGRRESIVE (0)
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/**************************************************
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* Temperature Compensation Setting
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**************************************************/
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#define GPU_MAX_SIGNOFF_VOLT (90000)
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#define TEMPERATURE_DEFAULT (-274) /* 'C */
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#define TEMPER_COMP_DEFAULT_VOLT (0)
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#define TEMPER_COMP_10_25_VOLT (2500) /* mV * 100 */
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#define TEMPER_COMP_10_VOLT (4375) /* mV * 100 */
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/**************************************************
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* SPM MTCMOS Setting
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**************************************************/
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/* bus protect control mask */
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#define MFG0_PROT_STEP0_0_MASK (BIT(4))
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#define MFG0_PROT_STEP0_0_ACK_MASK (BIT(4))
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#define MFG0_PROT_STEP1_0_MASK (BIT(9))
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#define MFG0_PROT_STEP1_0_ACK_MASK (BIT(9))
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#define MFG1_PROT_STEP0_0_MASK (BIT(0))
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#define MFG1_PROT_STEP0_0_ACK_MASK (BIT(0))
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#define MFG1_PROT_STEP1_0_MASK (BIT(20))
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#define MFG1_PROT_STEP1_0_ACK_MASK (BIT(20))
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#define MFG1_PROT_STEP2_0_MASK (BIT(1))
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#define MFG1_PROT_STEP2_0_ACK_MASK (BIT(1))
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#define MFG1_PROT_STEP3_0_MASK (BIT(18) | BIT(19))
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#define MFG1_PROT_STEP3_0_ACK_MASK (BIT(18) | BIT(19))
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#define MFG1_PROT_STEP4_0_MASK (BIT(2))
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#define MFG1_PROT_STEP4_0_ACK_MASK (BIT(2))
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#define MFG1_PROT_STEP5_0_MASK (BIT(3))
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#define MFG1_PROT_STEP5_0_ACK_MASK (BIT(3))
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/* power control bit mapping */
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#define PWR_RST_B BIT(0)
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#define PWR_ISO BIT(1)
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#define PWR_ON BIT(2)
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#define PWR_ON_2ND BIT(3)
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#define PWR_CLK_DIS BIT(4)
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#define SRAM_CKISO BIT(5)
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#define SRAM_ISOINT_B BIT(6)
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#define SRAM_PDN BIT(8)
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#define SRAM_SLP_B BIT(9)
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#define SRAM_PDN_ACK BIT(12)
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#define SRAM_SLP_B_ACK BIT(13)
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/* power status bit mapping */
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#define MFG0_PWR_STA_MASK BIT(1)
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#define MFG1_PWR_STA_MASK BIT(2)
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#define MFG2_PWR_STA_MASK BIT(3)
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#define MFG3_PWR_STA_MASK BIT(4)
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/**************************************************
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* Enumeration
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**************************************************/
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enum gpufreq_segment {
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ENG_SEGMENT = 0,
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MT6835_23_SEGMENT = 1,
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MT6835_23P_SEGMENT = 2,
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MT6835_24_SEGMENT = 3,
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MT6835_24P_SEGMENT = 4,
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MT6835_24PP_SEGMENT = 5,
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};
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enum gpufreq_clk_src {
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CLOCK_SUB = 0,
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CLOCK_MAIN,
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};
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/**************************************************
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* Structure
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**************************************************/
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struct gpufreq_pmic_info {
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struct regulator *reg_vcore;
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struct regulator *reg_dvfsrc;
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struct regulator *reg_vgpu;
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struct regulator *reg_vsram;
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};
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struct gpufreq_clk_info {
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struct clk *clk_mux;
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struct clk *clk_ref_mux;
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struct clk *clk_main_parent;
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struct clk *clk_sub_parent;
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struct clk *subsys_bg3d;
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};
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struct gpufreq_mtcmos_info {
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struct device *mfg0_dev;
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struct device *mfg1_dev;
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struct device *mfg2_dev;
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struct device *mfg3_dev;
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};
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struct gpufreq_status {
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struct gpufreq_opp_info *signed_table;
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struct gpufreq_opp_info *working_table;
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int buck_count;
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int mtcmos_count;
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int cg_count;
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int power_count;
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unsigned int segment_id;
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int signed_opp_num;
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int segment_upbound;
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int segment_lowbound;
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int opp_num;
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int max_oppidx;
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int min_oppidx;
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int cur_oppidx;
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unsigned int cur_freq;
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unsigned int cur_volt;
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unsigned int cur_vsram;
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unsigned int cur_vcore;
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};
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/**************************************************
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* GPU Platform OPP Table Definition
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**************************************************/
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#define GPU_SIGNED_OPP_0 (0)
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#define GPU_SIGNED_OPP_1 (32)
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#define GPU_SIGNED_OPP_2 (44)
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#define NUM_GPU_SIGNED_IDX ARRAY_SIZE(g_gpu_signed_idx)
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#define NUM_GPU_SIGNED_OPP ARRAY_SIZE(g_gpu_default_opp_table)
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static const int g_gpu_signed_idx[] = {
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GPU_SIGNED_OPP_0,
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GPU_SIGNED_OPP_1,
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GPU_SIGNED_OPP_2,
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};
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static struct gpufreq_opp_info g_gpu_default_opp_table[] = {
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GPUOP(1100000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 0 sign off */
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GPUOP(1086000, 89375, 89375, POSDIV_POWER_2, 0, 0), /* 1 */
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GPUOP(1072000, 88750, 88750, POSDIV_POWER_2, 0, 0), /* 2 */
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GPUOP(1058000, 88125, 88125, POSDIV_POWER_2, 0, 0), /* 3 */
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GPUOP(1045000, 87500, 87500, POSDIV_POWER_2, 0, 0), /* 4 */
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GPUOP(1031000, 86875, 86875, POSDIV_POWER_2, 0, 0), /* 5 */
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GPUOP(1017000, 86250, 86250, POSDIV_POWER_2, 0, 0), /* 6 */
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GPUOP(1003000, 85625, 85625, POSDIV_POWER_2, 0, 0), /* 7 */
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GPUOP(990000, 85000, 85000, POSDIV_POWER_2, 0, 0), /* 8 */
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GPUOP(976000, 84375, 84375, POSDIV_POWER_2, 0, 0), /* 9 */
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GPUOP(962000, 83125, 83125, POSDIV_POWER_2, 0, 0), /* 10 */
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GPUOP(948000, 82500, 82500, POSDIV_POWER_4, 0, 0), /* 11 */
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GPUOP(935000, 81875, 81875, POSDIV_POWER_4, 0, 0), /* 12 */
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GPUOP(921000, 81250, 81250, POSDIV_POWER_4, 0, 0), /* 13 */
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GPUOP(907000, 80625, 80625, POSDIV_POWER_4, 0, 0), /* 14 */
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GPUOP(893000, 80000, 80000, POSDIV_POWER_4, 0, 0), /* 15 */
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GPUOP(880000, 79375, 79375, POSDIV_POWER_4, 0, 0), /* 16 */
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GPUOP(868000, 78750, 78750, POSDIV_POWER_4, 0, 0), /* 17 */
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GPUOP(857000, 78125, 78125, POSDIV_POWER_4, 0, 0), /* 18 */
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GPUOP(846000, 77500, 77500, POSDIV_POWER_4, 0, 0), /* 19 */
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GPUOP(835000, 76875, 76875, POSDIV_POWER_4, 0, 0), /* 20 */
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GPUOP(823000, 76250, 76250, POSDIV_POWER_4, 0, 0), /* 21 */
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GPUOP(812000, 75625, 75625, POSDIV_POWER_4, 0, 0), /* 22 */
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GPUOP(801000, 75625, 75625, POSDIV_POWER_4, 0, 0), /* 23 */
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GPUOP(790000, 75000, 75000, POSDIV_POWER_4, 0, 0), /* 24 */
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GPUOP(778000, 74375, 75000, POSDIV_POWER_4, 0, 0), /* 25 */
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GPUOP(767000, 73750, 75000, POSDIV_POWER_4, 0, 0), /* 26 */
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GPUOP(756000, 73125, 75000, POSDIV_POWER_4, 0, 0), /* 27 */
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GPUOP(745000, 72500, 75000, POSDIV_POWER_4, 0, 0), /* 28 */
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GPUOP(733000, 71875, 75000, POSDIV_POWER_4, 0, 0), /* 29 */
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GPUOP(722000, 71250, 75000, POSDIV_POWER_4, 0, 0), /* 30 */
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GPUOP(711000, 70625, 75000, POSDIV_POWER_4, 0, 0), /* 31 */
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GPUOP(700000, 70000, 75000, POSDIV_POWER_4, 0, 0), /* 32 sign off*/
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GPUOP(674000, 70000, 75000, POSDIV_POWER_4, 0, 0), /* 33 */
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GPUOP(648000, 70000, 75000, POSDIV_POWER_4, 0, 0), /* 34 */
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GPUOP(622000, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 35 */
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GPUOP(596000, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 36 */
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GPUOP(570000, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 37 */
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GPUOP(545000, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 38 */
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GPUOP(519000, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 39 */
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GPUOP(493000, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 40 */
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GPUOP(467000, 68125, 75000, POSDIV_POWER_4, 0, 0), /* 41 */
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GPUOP(441000, 68125, 75000, POSDIV_POWER_4, 0, 0), /* 42 */
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GPUOP(415000, 68125, 75000, POSDIV_POWER_4, 0, 0), /* 43 */
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GPUOP(390000, 67500, 75000, POSDIV_POWER_4, 0, 0), /* 44 sign off*/
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};
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/**************************************************
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* OPP Adjustment
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**************************************************/
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static struct gpufreq_adj_info g_avs_table[NUM_GPU_SIGNED_IDX] = {
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ADJOP(GPU_SIGNED_OPP_0, 0, 0, 0),
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ADJOP(GPU_SIGNED_OPP_1, 0, 0, 0),
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ADJOP(GPU_SIGNED_OPP_2, 0, 0, 0),
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};
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static struct gpufreq_adj_info g_gpu_aging_table[][NUM_GPU_SIGNED_IDX] = {
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{ /* aging table 0 */
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ADJOP(GPU_SIGNED_OPP_0, 0, 625, 0),
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ADJOP(GPU_SIGNED_OPP_1, 0, 625, 0),
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ADJOP(GPU_SIGNED_OPP_2, 0, 625, 0),
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},
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{ /* aging table 1 */
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ADJOP(GPU_SIGNED_OPP_0, 0, 0, 0),
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ADJOP(GPU_SIGNED_OPP_1, 0, 0, 0),
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ADJOP(GPU_SIGNED_OPP_2, 0, 0, 0),
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},
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/* aging table 2: remove for code size */
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/* aging table 3: remove for code size */
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};
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#endif /* __GPUFREQ_MT6835_H__ */
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