11403 lines
326 KiB
Text
11403 lines
326 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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/dts-v1/;
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#include <dt-bindings/clock/mt6886-clk.h>
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#include <dt-bindings/power/mt6886-power.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/mt6886-pinfunc.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/memory/mt6886-larb-port.h>
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/iio/mt635x-auxadc.h>
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#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
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#include <dt-bindings/gce/mt6886-gce.h>
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#include <dt-bindings/soc/mediatek,boot-mode.h>
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#include <dt-bindings/iio/adc/mediatek,mt6375_auxadc.h>
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#include <dt-bindings/iio/adc/mediatek,mt6375_adc.h>
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#include <dt-bindings/mfd/mt6375.h>
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#include <dt-bindings/power/mt6375-gauge.h>
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#include <dt-bindings/interconnect/mtk,mmqos.h>
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#include <dt-bindings/mml/mml-mt6886.h>
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#include <dt-bindings/clock/mmdvfs-clk.h>
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/ {
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model = "MT6886";
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compatible = "mediatek,MT6886";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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i2c9 = &i2c9;
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i2c10 = &i2c10;
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i2c11 = &i2c11;
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ovl0 = &disp_ovl0;
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ovl3 = &disp_ovl0_2l;
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ovl4 = &disp_ovl1_2l;
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rdma0 = &disp_rdma0;
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rdma1 = &disp_rdma1;
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wdma0 = &disp_wdma0;
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wdma1 = &disp_wdma1;
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dsc0 = &disp_dsc0_wrap;
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dsi0 = &dsi0;
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rsz0 = &disp_rsz0;
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postmask0 = &disp_postmask0;
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mtksmmu0 = &disp_iommu;
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mtksmmu1 = &apu_iommu0;
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color0 = &disp_color0;
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ccorr0 = &disp_ccorr0_0;
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ccorr1 = &disp_ccorr0_1;
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c3d0 = &disp_c3d0;
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aal0 = &disp_aal0;
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gamma0 = &disp_gamma0;
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dither0 = &disp_dither0;
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chist0 = &disp_chist0;
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cm0 = &disp_cm0;
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spr0 = &disp_spr0;
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inlinerotate0 = &inlinerot0;
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y2r0 = &disp_y2r0;
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dlo-async3 = &disp_dlo_async3;
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dli-async3 = &disp_dli_async3;
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mml-wrot0 = &mml_wrot0;
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};
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cache-parity {
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compatible = "mediatek,mt6985-cache-parity";
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ecc-irq-support = <1>;
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arm_complex_ecc_hwirq = <40 41 42>;
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arm_dsu_ecc_hwirq = <48>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 0 Fault IRQ */
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 1 Fault IRQ */
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 2 Fault IRQ */
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 3 Fault IRQ */
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 4 Fault IRQ */
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 5 Fault IRQ */
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 6 Fault IRQ */
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, /* Core 7 Fault IRQ */
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, /* Complex 0 Fault IRQ */
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>, /* Complex 1 Fault IRQ */
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>, /* Complex 2 Fault IRQ */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; /* DSU Fault IRQ */
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};
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/* chosen */
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chosen: chosen {
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bootargs = "console=tty0 root=/dev/ram \
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rcupdate.rcu_expedited=1 \
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loglevel=8 disable_dma32=on \
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8250.nr_uarts=2 \
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allow_mismatched_32bit_el0 \
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androidboot.hardware=mt6886 \
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initcall_debug=1 cgroup.memory=nosocket,nokmem \
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vdmalloc=400M swiotlb=noforce transparent_hugepage=never \
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firmware_class.path=/vendor/firmware";
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kaslr-seed = <0 0>;
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mkp_panic="on";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0000>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0100>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0200>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0300>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0400>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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performance-domains = <&performance 0>;
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reg = <0x0500>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <374>;
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};
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cpu6: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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performance-domains = <&performance 1>;
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reg = <0x0600>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff_b
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <1024>;
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};
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cpu7: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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performance-domains = <&performance 1>;
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reg = <0x0700>;
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enable-method = "psci";
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cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff_b
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&system_mem &system_pll &system_bus
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&system_vcore &s2idle>;
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capacity-dmips-mhz = <1024>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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doe_dvfs_cl0: doe {
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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doe_dvfs_cl1: doe {
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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cpuoff_l: cpuoff-l {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x00010000>;
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local-timer-stop;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <11100>;
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};
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cpuoff_b: cpuoff-b {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x00010000>;
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local-timer-stop;
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entry-latency-us = <120>;
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exit-latency-us = <240>;
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min-residency-us = <7600>;
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};
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clusteroff_l: clusteroff-l {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010001>;
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local-timer-stop;
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entry-latency-us = <160>;
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exit-latency-us = <340>;
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min-residency-us = <11200>;
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};
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clusteroff_b: clusteroff-b {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010001>;
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local-timer-stop;
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entry-latency-us = <165>;
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exit-latency-us = <260>;
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min-residency-us = <11900>;
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};
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mcusysoff_l: mcusysoff-l {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010007>;
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local-timer-stop;
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entry-latency-us = <640>;
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exit-latency-us = <1400>;
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min-residency-us = <12700>;
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};
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mcusysoff_b: mcusysoff-b {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010007>;
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local-timer-stop;
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entry-latency-us = <640>;
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exit-latency-us = <1400>;
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min-residency-us = <12000>;
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};
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system_mem: system-mem {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0101000f>;
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local-timer-stop;
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entry-latency-us = <640>;
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exit-latency-us = <1800>;
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min-residency-us = <13200>;
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};
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system_pll: system-pll {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0101001f>;
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local-timer-stop;
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entry-latency-us = <640>;
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exit-latency-us = <1850>;
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min-residency-us = <13200>;
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};
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system_bus: system-bus {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0101007f>;
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local-timer-stop;
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entry-latency-us = <640>;
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exit-latency-us = <2800>;
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min-residency-us = <13200>;
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};
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system_vcore: system-vcore {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x010100ff>;
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local-timer-stop;
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entry-latency-us = <940>;
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exit-latency-us = <3500>;
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min-residency-us = <35200>;
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};
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s2idle: s2idle {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x010180ff>;
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local-timer-stop;
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entry-latency-us = <10000>;
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exit-latency-us = <10000>;
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min-residency-us = <4294967295>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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gic: interrupt-controller {
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/*TODO: please check interrupt controller again*/
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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#address-cells = <2>;
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#size-cells = <2>;
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#redistributor-regions = <1>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c400000 0 0x40000>, // distributor
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<0 0x0c440000 0 0x200000>; // redistributor
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu6 &cpu7>;
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};
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};
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};
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pmu-a510 {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
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};
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pmu-makalu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
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};
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dsu-pmu-0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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tboard_thermistor1: thermal-ntc1@1c805554 {
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compatible = "mediatek,mt6685-tia-ntc";
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#thermal-sensor-cells = <0>;
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reg = <0 0x1c805554 0 0x4>; /* TIA DATA T0 */
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temperature-lookup-table = <
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(-40000) 4397119
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(-39000) 4092874
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(-38000) 3811717
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(-37000) 3551749
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|
(-36000) 3311236
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|
(-35000) 3088599
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|
(-34000) 2882396
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|
(-33000) 2691310
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|
(-32000) 2514137
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|
(-31000) 2349778
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|
(-30000) 2197225
|
|
(-29000) 2055558
|
|
(-28000) 1923932
|
|
(-27000) 1801573
|
|
(-26000) 1687773
|
|
(-25000) 1581881
|
|
(-24000) 1483100
|
|
(-23000) 1391113
|
|
(-22000) 1305413
|
|
(-21000) 1225531
|
|
(-20000) 1151037
|
|
(-19000) 1081535
|
|
(-18000) 1016661
|
|
(-17000) 956080
|
|
(-16000) 899481
|
|
(-15000) 846579
|
|
(-14000) 797111
|
|
(-13000) 750834
|
|
(-12000) 707524
|
|
(-11000) 666972
|
|
(-10000) 628988
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|
(-9000) 593342
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|
(-8000) 559931
|
|
(-7000) 528602
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|
(-6000) 499212
|
|
(-5000) 471632
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|
(-4000) 445772
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|
(-3000) 421480
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(-2000) 398652
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|
(-1000) 377193
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|
0 357012
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|
1000 338006
|
|
2000 320122
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|
3000 303287
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|
4000 287434
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|
5000 272500
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|
6000 258426
|
|
7000 245160
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|
8000 232649
|
|
9000 220847
|
|
10000 209710
|
|
11000 199196
|
|
12000 189268
|
|
13000 179890
|
|
14000 171027
|
|
15000 162651
|
|
16000 154726
|
|
17000 147232
|
|
18000 140142
|
|
19000 133432
|
|
20000 127080
|
|
21000 121066
|
|
22000 115368
|
|
23000 109970
|
|
24000 104852
|
|
25000 100000
|
|
26000 95398
|
|
27000 91032
|
|
28000 86889
|
|
29000 82956
|
|
30000 79222
|
|
31000 75675
|
|
32000 72306
|
|
33000 69104
|
|
34000 66061
|
|
35000 63167
|
|
36000 60415
|
|
37000 57797
|
|
38000 55306
|
|
39000 52934
|
|
40000 50677
|
|
41000 48528
|
|
42000 46482
|
|
43000 44533
|
|
44000 42675
|
|
45000 40904
|
|
46000 39213
|
|
47000 37601
|
|
48000 36063
|
|
49000 34595
|
|
50000 33195
|
|
51000 31859
|
|
52000 30584
|
|
53000 29366
|
|
54000 28203
|
|
55000 27091
|
|
56000 26028
|
|
57000 25013
|
|
58000 24042
|
|
59000 23113
|
|
60000 22224
|
|
61000 21374
|
|
62000 20560
|
|
63000 19782
|
|
64000 19036
|
|
65000 18322
|
|
66000 17640
|
|
67000 16986
|
|
68000 16360
|
|
69000 15759
|
|
70000 15184
|
|
71000 14631
|
|
72000 14100
|
|
73000 13591
|
|
74000 13103
|
|
75000 12635
|
|
76000 12187
|
|
77000 11756
|
|
78000 11343
|
|
79000 10946
|
|
80000 10565
|
|
81000 10199
|
|
82000 9847
|
|
83000 9509
|
|
84000 9184
|
|
85000 8872
|
|
86000 8572
|
|
87000 8283
|
|
88000 8005
|
|
89000 7738
|
|
90000 7481
|
|
91000 7234
|
|
92000 6997
|
|
93000 6769
|
|
94000 6548
|
|
95000 6337
|
|
96000 6132
|
|
97000 5934
|
|
98000 5744
|
|
99000 5561
|
|
100000 5384
|
|
101000 5214
|
|
102000 5051
|
|
103000 4893
|
|
104000 4741
|
|
105000 4594
|
|
106000 4453
|
|
107000 4316
|
|
108000 4184
|
|
109000 4057
|
|
110000 3934
|
|
111000 3816
|
|
112000 3701
|
|
113000 3591
|
|
114000 3484
|
|
115000 3380
|
|
116000 3281
|
|
117000 3185
|
|
118000 3093
|
|
119000 3003
|
|
120000 2916
|
|
121000 2832
|
|
122000 2751
|
|
123000 2672
|
|
124000 2596
|
|
125000 2522>;
|
|
};
|
|
|
|
tboard_thermistor2: thermal-ntc2@1c805558 {
|
|
compatible = "mediatek,mt6685-tia-ntc";
|
|
#thermal-sensor-cells = <0>;
|
|
reg = <0 0x1c805558 0 0x4>; /* TIA DATA T1 */
|
|
temperature-lookup-table = <
|
|
(-40000) 4397119
|
|
(-39000) 4092874
|
|
(-38000) 3811717
|
|
(-37000) 3551749
|
|
(-36000) 3311236
|
|
(-35000) 3088599
|
|
(-34000) 2882396
|
|
(-33000) 2691310
|
|
(-32000) 2514137
|
|
(-31000) 2349778
|
|
(-30000) 2197225
|
|
(-29000) 2055558
|
|
(-28000) 1923932
|
|
(-27000) 1801573
|
|
(-26000) 1687773
|
|
(-25000) 1581881
|
|
(-24000) 1483100
|
|
(-23000) 1391113
|
|
(-22000) 1305413
|
|
(-21000) 1225531
|
|
(-20000) 1151037
|
|
(-19000) 1081535
|
|
(-18000) 1016661
|
|
(-17000) 956080
|
|
(-16000) 899481
|
|
(-15000) 846579
|
|
(-14000) 797111
|
|
(-13000) 750834
|
|
(-12000) 707524
|
|
(-11000) 666972
|
|
(-10000) 628988
|
|
(-9000) 593342
|
|
(-8000) 559931
|
|
(-7000) 528602
|
|
(-6000) 499212
|
|
(-5000) 471632
|
|
(-4000) 445772
|
|
(-3000) 421480
|
|
(-2000) 398652
|
|
(-1000) 377193
|
|
0 357012
|
|
1000 338006
|
|
2000 320122
|
|
3000 303287
|
|
4000 287434
|
|
5000 272500
|
|
6000 258426
|
|
7000 245160
|
|
8000 232649
|
|
9000 220847
|
|
10000 209710
|
|
11000 199196
|
|
12000 189268
|
|
13000 179890
|
|
14000 171027
|
|
15000 162651
|
|
16000 154726
|
|
17000 147232
|
|
18000 140142
|
|
19000 133432
|
|
20000 127080
|
|
21000 121066
|
|
22000 115368
|
|
23000 109970
|
|
24000 104852
|
|
25000 100000
|
|
26000 95398
|
|
27000 91032
|
|
28000 86889
|
|
29000 82956
|
|
30000 79222
|
|
31000 75675
|
|
32000 72306
|
|
33000 69104
|
|
34000 66061
|
|
35000 63167
|
|
36000 60415
|
|
37000 57797
|
|
38000 55306
|
|
39000 52934
|
|
40000 50677
|
|
41000 48528
|
|
42000 46482
|
|
43000 44533
|
|
44000 42675
|
|
45000 40904
|
|
46000 39213
|
|
47000 37601
|
|
48000 36063
|
|
49000 34595
|
|
50000 33195
|
|
51000 31859
|
|
52000 30584
|
|
53000 29366
|
|
54000 28203
|
|
55000 27091
|
|
56000 26028
|
|
57000 25013
|
|
58000 24042
|
|
59000 23113
|
|
60000 22224
|
|
61000 21374
|
|
62000 20560
|
|
63000 19782
|
|
64000 19036
|
|
65000 18322
|
|
66000 17640
|
|
67000 16986
|
|
68000 16360
|
|
69000 15759
|
|
70000 15184
|
|
71000 14631
|
|
72000 14100
|
|
73000 13591
|
|
74000 13103
|
|
75000 12635
|
|
76000 12187
|
|
77000 11756
|
|
78000 11343
|
|
79000 10946
|
|
80000 10565
|
|
81000 10199
|
|
82000 9847
|
|
83000 9509
|
|
84000 9184
|
|
85000 8872
|
|
86000 8572
|
|
87000 8283
|
|
88000 8005
|
|
89000 7738
|
|
90000 7481
|
|
91000 7234
|
|
92000 6997
|
|
93000 6769
|
|
94000 6548
|
|
95000 6337
|
|
96000 6132
|
|
97000 5934
|
|
98000 5744
|
|
99000 5561
|
|
100000 5384
|
|
101000 5214
|
|
102000 5051
|
|
103000 4893
|
|
104000 4741
|
|
105000 4594
|
|
106000 4453
|
|
107000 4316
|
|
108000 4184
|
|
109000 4057
|
|
110000 3934
|
|
111000 3816
|
|
112000 3701
|
|
113000 3591
|
|
114000 3484
|
|
115000 3380
|
|
116000 3281
|
|
117000 3185
|
|
118000 3093
|
|
119000 3003
|
|
120000 2916
|
|
121000 2832
|
|
122000 2751
|
|
123000 2672
|
|
124000 2596
|
|
125000 2522>;
|
|
};
|
|
|
|
tboard_thermistor3: thermal-ntc3@1c80555c {
|
|
compatible = "mediatek,mt6685-tia-ntc";
|
|
#thermal-sensor-cells = <0>;
|
|
reg = <0 0x1c80555c 0 0x4>; /* TIA DATA T2 */
|
|
temperature-lookup-table = <
|
|
(-40000) 4397119
|
|
(-39000) 4092874
|
|
(-38000) 3811717
|
|
(-37000) 3551749
|
|
(-36000) 3311236
|
|
(-35000) 3088599
|
|
(-34000) 2882396
|
|
(-33000) 2691310
|
|
(-32000) 2514137
|
|
(-31000) 2349778
|
|
(-30000) 2197225
|
|
(-29000) 2055558
|
|
(-28000) 1923932
|
|
(-27000) 1801573
|
|
(-26000) 1687773
|
|
(-25000) 1581881
|
|
(-24000) 1483100
|
|
(-23000) 1391113
|
|
(-22000) 1305413
|
|
(-21000) 1225531
|
|
(-20000) 1151037
|
|
(-19000) 1081535
|
|
(-18000) 1016661
|
|
(-17000) 956080
|
|
(-16000) 899481
|
|
(-15000) 846579
|
|
(-14000) 797111
|
|
(-13000) 750834
|
|
(-12000) 707524
|
|
(-11000) 666972
|
|
(-10000) 628988
|
|
(-9000) 593342
|
|
(-8000) 559931
|
|
(-7000) 528602
|
|
(-6000) 499212
|
|
(-5000) 471632
|
|
(-4000) 445772
|
|
(-3000) 421480
|
|
(-2000) 398652
|
|
(-1000) 377193
|
|
0 357012
|
|
1000 338006
|
|
2000 320122
|
|
3000 303287
|
|
4000 287434
|
|
5000 272500
|
|
6000 258426
|
|
7000 245160
|
|
8000 232649
|
|
9000 220847
|
|
10000 209710
|
|
11000 199196
|
|
12000 189268
|
|
13000 179890
|
|
14000 171027
|
|
15000 162651
|
|
16000 154726
|
|
17000 147232
|
|
18000 140142
|
|
19000 133432
|
|
20000 127080
|
|
21000 121066
|
|
22000 115368
|
|
23000 109970
|
|
24000 104852
|
|
25000 100000
|
|
26000 95398
|
|
27000 91032
|
|
28000 86889
|
|
29000 82956
|
|
30000 79222
|
|
31000 75675
|
|
32000 72306
|
|
33000 69104
|
|
34000 66061
|
|
35000 63167
|
|
36000 60415
|
|
37000 57797
|
|
38000 55306
|
|
39000 52934
|
|
40000 50677
|
|
41000 48528
|
|
42000 46482
|
|
43000 44533
|
|
44000 42675
|
|
45000 40904
|
|
46000 39213
|
|
47000 37601
|
|
48000 36063
|
|
49000 34595
|
|
50000 33195
|
|
51000 31859
|
|
52000 30584
|
|
53000 29366
|
|
54000 28203
|
|
55000 27091
|
|
56000 26028
|
|
57000 25013
|
|
58000 24042
|
|
59000 23113
|
|
60000 22224
|
|
61000 21374
|
|
62000 20560
|
|
63000 19782
|
|
64000 19036
|
|
65000 18322
|
|
66000 17640
|
|
67000 16986
|
|
68000 16360
|
|
69000 15759
|
|
70000 15184
|
|
71000 14631
|
|
72000 14100
|
|
73000 13591
|
|
74000 13103
|
|
75000 12635
|
|
76000 12187
|
|
77000 11756
|
|
78000 11343
|
|
79000 10946
|
|
80000 10565
|
|
81000 10199
|
|
82000 9847
|
|
83000 9509
|
|
84000 9184
|
|
85000 8872
|
|
86000 8572
|
|
87000 8283
|
|
88000 8005
|
|
89000 7738
|
|
90000 7481
|
|
91000 7234
|
|
92000 6997
|
|
93000 6769
|
|
94000 6548
|
|
95000 6337
|
|
96000 6132
|
|
97000 5934
|
|
98000 5744
|
|
99000 5561
|
|
100000 5384
|
|
101000 5214
|
|
102000 5051
|
|
103000 4893
|
|
104000 4741
|
|
105000 4594
|
|
106000 4453
|
|
107000 4316
|
|
108000 4184
|
|
109000 4057
|
|
110000 3934
|
|
111000 3816
|
|
112000 3701
|
|
113000 3591
|
|
114000 3484
|
|
115000 3380
|
|
116000 3281
|
|
117000 3185
|
|
118000 3093
|
|
119000 3003
|
|
120000 2916
|
|
121000 2832
|
|
122000 2751
|
|
123000 2672
|
|
124000 2596
|
|
125000 2522>;
|
|
};
|
|
|
|
tboard_thermistor4: thermal-ntc4 {
|
|
compatible = "generic-adc-thermal";
|
|
#thermal-sensor-cells = <0>;
|
|
io-channels = <&pmic_adc (ADC_PURES_OPEN_MASK | AUXADC_VIN2)>;
|
|
io-channel-names = "sensor-channel";
|
|
temperature-lookup-table = <
|
|
(-40000) 1760
|
|
(-39000) 1757
|
|
(-38000) 1754
|
|
(-37000) 1751
|
|
(-36000) 1747
|
|
(-35000) 1744
|
|
(-34000) 1740
|
|
(-33000) 1736
|
|
(-32000) 1731
|
|
(-31000) 1727
|
|
(-30000) 1722
|
|
(-29000) 1716
|
|
(-28000) 1711
|
|
(-27000) 1705
|
|
(-26000) 1699
|
|
(-25000) 1693
|
|
(-24000) 1686
|
|
(-23000) 1679
|
|
(-22000) 1672
|
|
(-21000) 1664
|
|
(-20000) 1656
|
|
(-19000) 1648
|
|
(-18000) 1639
|
|
(-17000) 1630
|
|
(-16000) 1620
|
|
(-15000) 1610
|
|
(-14000) 1599
|
|
(-13000) 1588
|
|
(-12000) 1577
|
|
(-11000) 1565
|
|
(-10000) 1553
|
|
(-9000) 1540
|
|
(-8000) 1527
|
|
(-7000) 1514
|
|
(-6000) 1500
|
|
(-5000) 1485
|
|
(-4000) 1470
|
|
(-3000) 1455
|
|
(-2000) 1439
|
|
(-1000) 1423
|
|
0 1406
|
|
1000 1389
|
|
2000 1372
|
|
3000 1354
|
|
4000 1335
|
|
5000 1317
|
|
6000 1298
|
|
7000 1279
|
|
8000 1259
|
|
9000 1239
|
|
10000 1219
|
|
11000 1198
|
|
12000 1178
|
|
13000 1157
|
|
14000 1136
|
|
15000 1115
|
|
16000 1093
|
|
17000 1072
|
|
18000 1050
|
|
19000 1029
|
|
20000 1007
|
|
21000 986
|
|
22000 964
|
|
23000 943
|
|
24000 921
|
|
25000 900
|
|
26000 879
|
|
27000 858
|
|
28000 837
|
|
29000 816
|
|
30000 796
|
|
31000 775
|
|
32000 755
|
|
33000 736
|
|
34000 716
|
|
35000 697
|
|
36000 678
|
|
37000 659
|
|
38000 641
|
|
39000 623
|
|
40000 605
|
|
41000 588
|
|
42000 571
|
|
43000 555
|
|
44000 538
|
|
45000 523
|
|
46000 507
|
|
47000 492
|
|
48000 477
|
|
49000 463
|
|
50000 449
|
|
51000 435
|
|
52000 422
|
|
53000 409
|
|
54000 396
|
|
55000 384
|
|
56000 372
|
|
57000 360
|
|
58000 349
|
|
59000 338
|
|
60000 327
|
|
61000 317
|
|
62000 307
|
|
63000 297
|
|
64000 288
|
|
65000 279
|
|
66000 270
|
|
67000 261
|
|
68000 253
|
|
69000 245
|
|
70000 237
|
|
71000 230
|
|
72000 222
|
|
73000 215
|
|
74000 209
|
|
75000 202
|
|
76000 196
|
|
77000 189
|
|
78000 183
|
|
79000 178
|
|
80000 172
|
|
81000 167
|
|
82000 161
|
|
83000 156
|
|
84000 151
|
|
85000 147
|
|
86000 142
|
|
87000 138
|
|
88000 133
|
|
89000 129
|
|
90000 125
|
|
91000 121
|
|
92000 118
|
|
93000 114
|
|
94000 111
|
|
95000 107
|
|
96000 104
|
|
97000 101
|
|
98000 98
|
|
99000 95
|
|
100000 92
|
|
101000 89
|
|
102000 87
|
|
103000 84
|
|
104000 81
|
|
105000 79
|
|
106000 77
|
|
107000 74
|
|
108000 72
|
|
109000 70
|
|
110000 68
|
|
111000 66
|
|
112000 64
|
|
113000 62
|
|
114000 61
|
|
115000 59
|
|
116000 57
|
|
117000 56
|
|
118000 54
|
|
119000 52
|
|
120000 51
|
|
121000 50
|
|
122000 48
|
|
123000 47
|
|
124000 46
|
|
125000 44>;
|
|
};
|
|
|
|
tsx_thermistor: thermal-ntc5@1c80554c {
|
|
compatible = "mediatek,mt6685-tia-ntc";
|
|
#thermal-sensor-cells = <0>;
|
|
reg = <0 0x1c80554c 0 0x4>; /* TIA DATA TSX */
|
|
temperature-lookup-table = <
|
|
(-40000) 5319893
|
|
(-39000) 4921450
|
|
(-38000) 4555864
|
|
(-37000) 4220193
|
|
(-36000) 3911778
|
|
(-35000) 3628214
|
|
(-34000) 3367324
|
|
(-33000) 3127136
|
|
(-32000) 2905864
|
|
(-31000) 2701885
|
|
(-30000) 2513730
|
|
(-29000) 2340060
|
|
(-28000) 2179662
|
|
(-27000) 2031430
|
|
(-26000) 1894358
|
|
(-25000) 1767530
|
|
(-24000) 1650110
|
|
(-23000) 1541338
|
|
(-22000) 1440519
|
|
(-21000) 1347016
|
|
(-20000) 1260250
|
|
(-19000) 1179692
|
|
(-18000) 1104854
|
|
(-17000) 1035294
|
|
(-16000) 970604
|
|
(-15000) 910412
|
|
(-14000) 854374
|
|
(-13000) 802177
|
|
(-12000) 753533
|
|
(-11000) 708176
|
|
(-10000) 665864
|
|
(-9000) 626371
|
|
(-8000) 589493
|
|
(-7000) 555039
|
|
(-6000) 522835
|
|
(-5000) 492719
|
|
(-4000) 464542
|
|
(-3000) 438167
|
|
(-2000) 413469
|
|
(-1000) 390328
|
|
0 368639
|
|
1000 348299
|
|
2000 329218
|
|
3000 311309
|
|
4000 294493
|
|
5000 278697
|
|
6000 263852
|
|
7000 249896
|
|
8000 236769
|
|
9000 224418
|
|
10000 212791
|
|
11000 201843
|
|
12000 191528
|
|
13000 181808
|
|
14000 172643
|
|
15000 163999
|
|
16000 155844
|
|
17000 148146
|
|
18000 140877
|
|
19000 134011
|
|
20000 127523
|
|
21000 121390
|
|
22000 115591
|
|
23000 110105
|
|
24000 104914
|
|
25000 100000
|
|
26000 95347
|
|
27000 90939
|
|
28000 86762
|
|
29000 82803
|
|
30000 79049
|
|
31000 75488
|
|
32000 72109
|
|
33000 68902
|
|
34000 65857
|
|
35000 62965
|
|
36000 60218
|
|
37000 57607
|
|
38000 55125
|
|
39000 52765
|
|
40000 50520
|
|
41000 48384
|
|
42000 46351
|
|
43000 44415
|
|
44000 42572
|
|
45000 40816
|
|
46000 39143
|
|
47000 37548
|
|
48000 36028
|
|
49000 34578
|
|
50000 33195
|
|
51000 31875
|
|
52000 30615
|
|
53000 29412
|
|
54000 28264
|
|
55000 27167
|
|
56000 26119
|
|
57000 25117
|
|
58000 24159
|
|
59000 23243
|
|
60000 22368
|
|
61000 21530
|
|
62000 20728
|
|
63000 19961
|
|
64000 19226
|
|
65000 18523
|
|
66000 17849
|
|
67000 17203
|
|
68000 16584
|
|
69000 15991
|
|
70000 15423
|
|
71000 14878
|
|
72000 14355
|
|
73000 13853
|
|
74000 13372
|
|
75000 12910
|
|
76000 12466
|
|
77000 12040
|
|
78000 11631
|
|
79000 11238
|
|
80000 10861
|
|
81000 10498
|
|
82000 10149
|
|
83000 9814
|
|
84000 9491
|
|
85000 9181
|
|
86000 8883
|
|
87000 8596
|
|
88000 8319
|
|
89000 8053
|
|
90000 7797
|
|
91000 7551
|
|
92000 7313
|
|
93000 7084
|
|
94000 6864
|
|
95000 6651
|
|
96000 6446
|
|
97000 6249
|
|
98000 6059
|
|
99000 5875
|
|
100000 5698
|
|
101000 5527
|
|
102000 5362
|
|
103000 5203
|
|
104000 5050
|
|
105000 4901
|
|
106000 4758
|
|
107000 4620
|
|
108000 4486
|
|
109000 4357
|
|
110000 4233
|
|
111000 4112
|
|
112000 3996
|
|
113000 3883
|
|
114000 3774
|
|
115000 3669
|
|
116000 3567
|
|
117000 3469
|
|
118000 3374
|
|
119000 3281
|
|
120000 3192
|
|
121000 3106
|
|
122000 3022
|
|
123000 2941
|
|
124000 2863
|
|
125000 2787>;
|
|
};
|
|
|
|
mt6363_temp: mt6363-temp {
|
|
compatible = "mediatek,mt6363-pmic-temp";
|
|
io-channels =
|
|
<&pmic_adc AUXADC_CHIP_TEMP>,
|
|
<&pmic_adc AUXADC_VCORE_TEMP>,
|
|
<&pmic_adc AUXADC_VPROC_TEMP>,
|
|
<&pmic_adc AUXADC_VGPU_TEMP>;
|
|
io-channel-names =
|
|
"pmic6363_ts1",
|
|
"pmic6363_ts2",
|
|
"pmic6363_ts3",
|
|
"pmic6363_ts4";
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
nvmem-cells = <&mt6363_thermal_efuse>;
|
|
nvmem-cell-names = "mt6363_e_data";
|
|
};
|
|
|
|
mt6368_temp: mt6368-temp {
|
|
compatible = "mediatek,mt6368-pmic-temp";
|
|
io-channels =
|
|
<&mt6368_adc AUXADC_CHIP_TEMP>,
|
|
<&mt6368_adc AUXADC_VCORE_TEMP>,
|
|
<&mt6368_adc AUXADC_VPROC_TEMP>,
|
|
<&mt6368_adc AUXADC_VGPU_TEMP>;
|
|
io-channel-names =
|
|
"pmic6368_ts1",
|
|
"pmic6368_ts2",
|
|
"pmic6368_ts3",
|
|
"pmic6368_ts4";
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
nvmem-cells = <&mt6368_thermal_efuse>;
|
|
nvmem-cell-names = "mt6368_e_data";
|
|
};
|
|
|
|
seninf_top: seninf_top@1a00e000 {
|
|
compatible = "mediatek,seninf-core";
|
|
reg = <0 0x1a00e000 0 0x18000>,
|
|
<0 0x11c80000 0 0x10000>;
|
|
reg-names = "base", "ana-rx";
|
|
interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
seninf_num = <8>;
|
|
mux_num = <13>; // physical mux num
|
|
cam_mux_num = <30>;
|
|
|
|
mux-camsv-sat_range = <0 2>;
|
|
mux-camsv-normal_range = <3 3>;
|
|
mux-raw_range = <4 9>;
|
|
mux-uisp_range = <3 3>;
|
|
mux-pdp_range = <10 12>;
|
|
|
|
cammux-camsv-sat_range = <0 23>;
|
|
cammux-camsv-normal_range = <24 24>;
|
|
cammux-raw_range = <25 26>;
|
|
cammux-uisp_range = <24 24>;
|
|
cammux-pdp_range = <27 29>;
|
|
|
|
mtk_iomem_ver = "mt6886";
|
|
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_SENINF_CON_0>,
|
|
<&topckgen_clk CLK_TOP_SENINF_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF1_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF2_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF3_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "clk_cam_seninf",
|
|
"clk_top_seninf",
|
|
"clk_top_seninf1",
|
|
"clk_top_seninf2",
|
|
"clk_top_seninf3",
|
|
"clk_top_camtm";
|
|
};
|
|
|
|
remoteproc_ccd: remoteproc_ccd@1a030000 {
|
|
compatible = "mediatek,ccd";
|
|
reg = <0 0x1a030000 0 0x10000>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L16_CQI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R2>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R3>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R5>,
|
|
<&disp_iommu M4U_PORT_L16_IMGO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_BPCI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_LSCI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_UFEO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_LTMSO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_DRZB2NO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_AAO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_AFO_R1>;
|
|
|
|
msg_dev {
|
|
mtk,rpmsg-name = "mtk_ccd_msgdev";
|
|
};
|
|
};
|
|
|
|
camisp: camisp@1a000000 {
|
|
compatible = "mediatek,mt6886-camisp";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
reg-names = "base";
|
|
mediatek,ccd = <&remoteproc_ccd>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
operating-points-v2 = <&opp_table_cam>;
|
|
clocks = <&mmdvfs_clk CLK_MMDVFS_CAM>;
|
|
clock-names = "mmdvfs_clk";
|
|
mboxes = <&gce_m 24 0 CMDQ_THR_PRIO_1>;
|
|
};
|
|
|
|
cam_raw_a@1a030000 {
|
|
compatible = "mediatek,cam-raw";
|
|
reg = <0 0x1a030000 0 0x8000>,
|
|
<0 0x1a038000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,cam-id = <0>;
|
|
mediatek,larbs = <&smi_larb16>;
|
|
interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_ADLRD_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_ADLWR_CON_0>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_LARBX>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_CAM>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_CAMTG>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "camsys_cam_cgpdn",
|
|
"camsys_camtg_cgpdn",
|
|
"camsys_rawa_larbx_cgpdn",
|
|
"camsys_rawa_cam_cgpdn",
|
|
"camsys_rawa_camtg_cgpdn",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
iommus = <&disp_iommu M4U_PORT_L16_CQI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R2>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R3>,
|
|
<&disp_iommu M4U_PORT_L16_RAWI_R5>,
|
|
<&disp_iommu M4U_PORT_L16_IMGO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_BPCI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_LSCI_R1>,
|
|
<&disp_iommu M4U_PORT_L16_UFEO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_LTMSO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_DRZB2NO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_AAO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_AFO_R1>,
|
|
<&disp_iommu M4U_PORT_L16_RGBWI_R1>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CQI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R5)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_IMGO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_BPCI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_LSCI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_UFEO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_LTMSO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_DRZB2NO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_AAO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_AFO_R1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"cqi_r1",
|
|
"rawi_r2",
|
|
"rawi_r3",
|
|
"rawi_r5",
|
|
"imgo_r1",
|
|
"bpci_r1",
|
|
"lsci_r1",
|
|
"ufeo_r1",
|
|
"ltmso_r1",
|
|
"drzb2no_r1",
|
|
"aao_r1",
|
|
"afo_r1";
|
|
|
|
};
|
|
|
|
cam_yuv_a@1a050000 {
|
|
compatible = "mediatek,cam-yuv";
|
|
reg = <0 0x1a050000 0 0x8000>,
|
|
<0 0x1a058000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,cam-id = <0>;
|
|
mediatek,larbs = <&smi_larb17>;
|
|
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_yuva_clk CLK_CAM_YA_LARBX>,
|
|
<&camsys_yuva_clk CLK_CAM_YA_CAM>,
|
|
<&camsys_yuva_clk CLK_CAM_YA_CAMTG>;
|
|
clock-names = "camsys_yuva_larbx_cgpdn",
|
|
"camsys_yuva_cam_cgpdn",
|
|
"camsys_yuva_camtg_cgpdn";
|
|
iommus = <&disp_iommu M4U_PORT_L17_YUVO_R1>,
|
|
<&disp_iommu M4U_PORT_L17_YUVO_R3>,
|
|
<&disp_iommu M4U_PORT_L17_YUVO_R2>,
|
|
<&disp_iommu M4U_PORT_L17_YUVO_R5>,
|
|
<&disp_iommu M4U_PORT_L17_TCYSO_R1>,
|
|
<&disp_iommu M4U_PORT_L17_DRZHNO_R9>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R5)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUV_R_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_TCYSO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_DRZHNO_R9)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"yuvo_r1",
|
|
"yuvo_r3",
|
|
"yuvo_r2",
|
|
"yuvo_r5",
|
|
"yuv_r_0",
|
|
"tcyso_r1",
|
|
"drzhno_r9";
|
|
};
|
|
|
|
cam_raw_b@1a070000 {
|
|
compatible = "mediatek,cam-raw";
|
|
reg = <0 0x1a070000 0 0x8000>,
|
|
<0 0x1a078000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,cam-id = <1>;
|
|
mediatek,larbs = <&smi_larb30>;
|
|
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_ADLRD_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_ADLWR_CON_0>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_LARBX>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_CAM>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_CAMTG>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "camsys_cam_cgpdn",
|
|
"camsys_camtg_cgpdn",
|
|
"camsys_rawb_larbx_cgpdn",
|
|
"camsys_rawb_cam_cgpdn",
|
|
"camsys_rawb_camtg_cgpdn",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
iommus = <&disp_iommu M4U_PORT_L30_CQI_R1>,
|
|
<&disp_iommu M4U_PORT_L30_RAWI_R2>,
|
|
<&disp_iommu M4U_PORT_L30_RAWI_R3>,
|
|
<&disp_iommu M4U_PORT_L30_RAWI_R5>,
|
|
<&disp_iommu M4U_PORT_L30_IMGO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_BPCI_R1>,
|
|
<&disp_iommu M4U_PORT_L30_LSCI_R1>,
|
|
<&disp_iommu M4U_PORT_L30_UFEO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_LTMSO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_DRZB2NO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_AAO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_AFO_R1>,
|
|
<&disp_iommu M4U_PORT_L30_RGBWI_R1>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_CQI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R5)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_IMGO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_BPCI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_LSCI_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_UFEO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_LTMSO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_DRZB2NO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_AAO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_AFO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RGBWI_R1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"cqi_r1",
|
|
"rawi_r2",
|
|
"rawi_r3",
|
|
"rawi_r5",
|
|
"imgo_r1",
|
|
"bpci_r1",
|
|
"lsci_r1",
|
|
"ufeo_r1",
|
|
"ltmso_r1",
|
|
"drzb2no_r1",
|
|
"aao_r1",
|
|
"afo_r1",
|
|
"rgbwi_r1";
|
|
|
|
};
|
|
|
|
cam_yuv_b@1a090000 {
|
|
compatible = "mediatek,cam-yuv";
|
|
reg = <0 0x1a090000 0 0x8000>,
|
|
<0 0x1a098000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,cam-id = <1>;
|
|
mediatek,larbs = <&smi_larb34>;
|
|
interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_yuvb_clk CLK_CAM_YB_LARBX>,
|
|
<&camsys_yuvb_clk CLK_CAM_YB_CAM>,
|
|
<&camsys_yuvb_clk CLK_CAM_YB_CAMTG>;
|
|
clock-names = "camsys_yuvb_larbx_cgpdn",
|
|
"camsys_yuvb_cam_cgpdn",
|
|
"camsys_yuvb_camtg_cgpdn";
|
|
iommus = <&disp_iommu M4U_PORT_L34_YUVO_R1>,
|
|
<&disp_iommu M4U_PORT_L34_YUVO_R3>,
|
|
<&disp_iommu M4U_PORT_L34_YUVO_R2>,
|
|
<&disp_iommu M4U_PORT_L34_YUVO_R5>,
|
|
<&disp_iommu M4U_PORT_L34_TCYSO_R1>,
|
|
<&disp_iommu M4U_PORT_L34_DRZHNO_R9>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R5)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUV_R_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_TCYSO_R1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L34_DRZHNO_R9)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"yuvo_r1",
|
|
"yuvo_r3",
|
|
"yuvo_r2",
|
|
"yuvo_r5",
|
|
"yuv_r_0",
|
|
"tcyso_r1",
|
|
"drzhno_r9";
|
|
};
|
|
|
|
camsv1@1a100000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a100000 0 0x1000>,
|
|
<0 0x1a110000 0 0x1000>,
|
|
<0 0x1a120000 0 0x1000>,
|
|
<0 0x1a108000 0 0x1000>,
|
|
<0 0x1a118000 0 0x1000>,
|
|
<0 0x1a128000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <0>;
|
|
mediatek,cammux-id = <0>;
|
|
mediatek,larbs = <&smi_larb14>;
|
|
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L14_CAMSV_CQI_E0>,
|
|
<&disp_iommu M4U_PORT_L14_CAMSV_E0_WDMA>,
|
|
<&disp_iommu M4U_PORT_L14_CAMSV_R_0_WDMA>,
|
|
<&disp_iommu M4U_PORT_L14_CAMSV_R_1_WDMA>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_A_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb14_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_a_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_CQI_E0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_E0_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l14_cqi_a",
|
|
"l14_imgo_a";
|
|
};
|
|
camsv2@1a101000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a101000 0 0x1000>,
|
|
<0 0x1a111000 0 0x1000>,
|
|
<0 0x1a121000 0 0x1000>,
|
|
<0 0x1a109000 0 0x1000>,
|
|
<0 0x1a119000 0 0x1000>,
|
|
<0 0x1a129000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <1>;
|
|
mediatek,cammux-id = <8>;
|
|
mediatek,larbs = <&smi_larb13>;
|
|
interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L13_CAMSV_CQI_E1>,
|
|
<&disp_iommu M4U_PORT_L13_CAMSV_E1_WDMA>,
|
|
<&disp_iommu M4U_PORT_L13_FAKE_ENG>,
|
|
<&disp_iommu M4U_PORT_L13_CAMSV_R_0>,
|
|
<&disp_iommu M4U_PORT_L13_CAMSV_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_B_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb13_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_b_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_CQI_E1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_E1_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l13_cqi_b",
|
|
"l13_imgo_b";
|
|
};
|
|
camsv3@1a102000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a102000 0 0x1000>,
|
|
<0 0x1a112000 0 0x1000>,
|
|
<0 0x1a122000 0 0x1000>,
|
|
<0 0x1a10a000 0 0x1000>,
|
|
<0 0x1a11a000 0 0x1000>,
|
|
<0 0x1a12a000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <2>;
|
|
mediatek,cammux-id = <0>;
|
|
mediatek,larbs = <&smi_larb29>;
|
|
interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L29_CAMSV_CQI_E2>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E3>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E4>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E5>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E2_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E3_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E4_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E5_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_0>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_C_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb29_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_c_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E2_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l29_cqi_c",
|
|
"l29_imgo_c";
|
|
};
|
|
camsv4@1a103000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a103000 0 0x1000>,
|
|
<0 0x1a113000 0 0x1000>,
|
|
<0 0x1a123000 0 0x1000>,
|
|
<0 0x1a10b000 0 0x1000>,
|
|
<0 0x1a11b000 0 0x1000>,
|
|
<0 0x1a12b000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <3>;
|
|
mediatek,cammux-id = <16>;
|
|
mediatek,larbs = <&smi_larb29>;
|
|
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L29_CAMSV_CQI_E2>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E3>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E4>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E5>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E2_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E3_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E4_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E5_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_0>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_D_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb29_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_d_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E3_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l29_cqi_d",
|
|
"l29_imgo_d";
|
|
};
|
|
camsv5@1a104000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a104000 0 0x1000>,
|
|
<0 0x1a114000 0 0x1000>,
|
|
<0 0x1a124000 0 0x1000>,
|
|
<0 0x1a10c000 0 0x1000>,
|
|
<0 0x1a11c000 0 0x1000>,
|
|
<0 0x1a12c000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <4>;
|
|
mediatek,cammux-id = <24>;
|
|
mediatek,larbs = <&smi_larb29>;
|
|
interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L29_CAMSV_CQI_E2>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E3>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E4>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E5>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E2_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E3_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E4_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E5_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_0>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_E_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb29_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_e_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E4)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E4_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l29_cqi_e",
|
|
"l29_imgo_e";
|
|
};
|
|
camsv6@1a105000 {
|
|
compatible = "mediatek,camsv";
|
|
reg = <0 0x1a105000 0 0x1000>,
|
|
<0 0x1a115000 0 0x1000>,
|
|
<0 0x1a125000 0 0x1000>,
|
|
<0 0x1a10d000 0 0x1000>,
|
|
<0 0x1a11d000 0 0x1000>,
|
|
<0 0x1a12d000 0 0x1000>;
|
|
reg-names = "base", "base_DMA", "base_SCQ", "inner_base",
|
|
"inner_base_DMA", "inner_base_SCQ";
|
|
mediatek,camsv-id = <5>;
|
|
mediatek,cammux-id = <0>;
|
|
mediatek,larbs = <&smi_larb29>;
|
|
interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L29_CAMSV_CQI_E2>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E3>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E4>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_CQI_E5>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E2_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E3_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E4_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_E5_WDMA>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_0>,
|
|
<&disp_iommu M4U_PORT_L29_CAMSV_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAMSV_CON_1>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_larb29_con",
|
|
"cam_main_cam_con",
|
|
"cam_main_camtg_con",
|
|
"cam_main_camsv_top_con",
|
|
"cam_main_camsv_f_con",
|
|
"topckgen_top_cam_sel",
|
|
"topckgen_top_camtg_sel",
|
|
"topckgen_top_camtm_sel";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E5)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E5_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l29_cqi_f",
|
|
"l29_imgo_f";
|
|
};
|
|
|
|
mraw1@1a130000 {
|
|
compatible = "mediatek,mraw";
|
|
reg = <0 0x1a130000 0 0x8000>,
|
|
<0 0x1a138000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,mraw-id = <0>;
|
|
mediatek,cammux-id = <27>;
|
|
mediatek,larbs = <&smi_larb25>;
|
|
interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L25_MRAW0_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW0_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_2>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_3>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_4>,
|
|
<&disp_iommu M4U_PORT_L25_PDAO_A_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_2>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_3>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_4>,
|
|
<&disp_iommu M4U_PORT_L25_PDAO_B_0>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW0_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW_R_0>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_CAMTG>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_MRAW0>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_mraw_cg_con",
|
|
"camsys_mraw_larbx",
|
|
"camsys_mraw_camtg",
|
|
"camsys_main_mraw0",
|
|
"topckgen_top_muxcamtm";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_CQI_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGBO_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGO_M1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l25_cqi_m1_0",
|
|
"l25_imgo_m1_0",
|
|
"l25_imgbo_m1_0";
|
|
};
|
|
mraw2@1a140000 {
|
|
compatible = "mediatek,mraw";
|
|
reg = <0 0x1a140000 0 0x8000>,
|
|
<0 0x1a148000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,mraw-id = <1>;
|
|
mediatek,cammux-id = <28>;
|
|
mediatek,larbs = <&smi_larb26>;
|
|
interrupts = <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L26_MRAW1_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW1_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW1_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW_R_0>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_CAMTG>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_MRAW1>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_mraw_cg_con",
|
|
"camsys_mraw_larbx",
|
|
"camsys_mraw_camtg",
|
|
"camsys_main_mraw1",
|
|
"topckgen_top_muxcamtm";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_CQI_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGBO_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGO_M1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l26_cqi_m1_1",
|
|
"l26_imgo_m1_1",
|
|
"l26_imgbo_m1_1";
|
|
};
|
|
mraw3@1a150000 {
|
|
compatible = "mediatek,mraw";
|
|
reg = <0 0x1a150000 0 0x8000>,
|
|
<0 0x1a158000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,mraw-id = <2>;
|
|
mediatek,cammux-id = <29>;
|
|
mediatek,larbs = <&smi_larb25>;
|
|
interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L25_MRAW0_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW0_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_2>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_3>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_4>,
|
|
<&disp_iommu M4U_PORT_L25_PDAO_A_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_2>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_3>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_B_4>,
|
|
<&disp_iommu M4U_PORT_L25_PDAO_B_0>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW0_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW2_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW_R_0>,
|
|
<&disp_iommu M4U_PORT_L25_MRAW_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_CAMTG>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_MRAW2>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_mraw_cg_con",
|
|
"camsys_mraw_larbx",
|
|
"camsys_mraw_camtg",
|
|
"camsys_main_mraw2",
|
|
"topckgen_top_muxcamtm";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_CQI_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGBO_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGO_M1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l25_cqi_m1_2",
|
|
"l25_imgo_m1_2",
|
|
"l25_imgbo_m1_2";
|
|
};
|
|
mraw4@1a160000 {
|
|
compatible = "mediatek,mraw";
|
|
reg = <0 0x1a160000 0 0x8000>,
|
|
<0 0x1a168000 0 0x8000>;
|
|
reg-names = "base", "inner_base";
|
|
mediatek,mraw-id = <3>;
|
|
mediatek,cammux-id = <0>;
|
|
mediatek,larbs = <&smi_larb26>;
|
|
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&disp_iommu M4U_PORT_L26_MRAW1_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW1_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_CQI_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_IMGO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW1_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW3_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW4_IMGBO_M1>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW_R_0>,
|
|
<&disp_iommu M4U_PORT_L26_MRAW_R_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_CAMTG>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_MRAW3>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>;
|
|
clock-names = "cam_main_mraw_cg_con",
|
|
"camsys_mraw_larbx",
|
|
"camsys_mraw_camtg",
|
|
"camsys_main_mraw3",
|
|
"topckgen_top_muxcamtm";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_CQI_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGBO_M1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGO_M1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l26_cqi_m1_3",
|
|
"l26_imgo_m1_3",
|
|
"l26_imgbo_m1_3";
|
|
};
|
|
|
|
md_cooler: md-cooler {
|
|
compatible = "mediatek,mt6298-md-cooler";
|
|
pa1: pa1 {
|
|
mutt_pa1: mutt-pa1 {
|
|
#cooling-cells = <2>;
|
|
};
|
|
tx_pwr_pa1: tx-pwr-pa1 {
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
pa2: pa2 {
|
|
mutt_pa2: mutt-pa2 {
|
|
#cooling-cells = <2>;
|
|
};
|
|
tx_pwr_pa2: tx-pwr-pa2 {
|
|
#cooling-cells = <2>;
|
|
};
|
|
scg_off_pa2: scg-off-pa2 {
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
charger_cooler: charger-cooler {
|
|
compatible = "mediatek,mt6375-charger-cooler";
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
backlight_cooler: backlight-cooler {
|
|
compatible = "mediatek,backlight-cooler";
|
|
backlight-names = "lcd-backlight";
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
wifi_cooler: wifi-cooler {
|
|
compatible = "mediatek,wifi-level-cooler";
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
therm_intf: therm-intf@114000 {
|
|
compatible = "mediatek,therm_intf";
|
|
reg = <0 0x00114000 0 0x400>,
|
|
<0 0x190e1000 0 0x1000>;
|
|
reg-names = "therm_sram",
|
|
"apu_mbox";
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
soc_max {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 0>;
|
|
|
|
trips {
|
|
soc_max_crit: soc-max-crit {
|
|
temperature = <119000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
cpu-little1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 1>;
|
|
};
|
|
cpu-little2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 2>;
|
|
};
|
|
cpu-little3 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 3>;
|
|
};
|
|
cpu-little4 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 4>;
|
|
};
|
|
cpu-big1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 5>;
|
|
};
|
|
cpu-big2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 6>;
|
|
};
|
|
cpu-big3 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 7>;
|
|
};
|
|
cpu-big4 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 8>;
|
|
};
|
|
cpu-little5 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 9>;
|
|
};
|
|
cpu-little6 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 10>;
|
|
};
|
|
cpu-dsu1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 11>;
|
|
};
|
|
cpu-dsu2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 12>;
|
|
};
|
|
gpu1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 13>;
|
|
};
|
|
gpu2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 14>;
|
|
};
|
|
apu1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 15>;
|
|
};
|
|
apu2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 16>;
|
|
};
|
|
soc-top1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 17>;
|
|
};
|
|
soc-top2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 18>;
|
|
};
|
|
soc-top3 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 19>;
|
|
};
|
|
soc-bottom1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 20>;
|
|
};
|
|
soc-bottom2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 21>;
|
|
};
|
|
md1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 22>;
|
|
};
|
|
md2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 23>;
|
|
};
|
|
md3 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&lvts 24>;
|
|
};
|
|
ap_ntc: ap_ntc {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&tboard_thermistor1>;
|
|
};
|
|
ltepa_ntc: ltepa_ntc {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&tboard_thermistor2>;
|
|
};
|
|
nrpa_ntc: nrpa_ntc {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&tboard_thermistor3>;
|
|
};
|
|
quiet_ntc: quiet_ntc {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&tboard_thermistor4>;
|
|
};
|
|
tsx_ntc: tsx-ntc {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&tsx_thermistor>;
|
|
};
|
|
pmic6363-vio18 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6363_temp 0>;
|
|
};
|
|
pmic6363-vs1-vs3 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6363_temp 1>;
|
|
};
|
|
pmic6363-bk3-bk7 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6363_temp 2>;
|
|
};
|
|
pmic6363-vs2 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6363_temp 3>;
|
|
};
|
|
pmic6368-buck1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6368_temp 0>;
|
|
};
|
|
pmic6368-vpa {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6368_temp 1>;
|
|
};
|
|
pmic6368-vcn33-1 {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6368_temp 2>;
|
|
};
|
|
pmic6368-vrf18-aif {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&mt6368_temp 3>;
|
|
};
|
|
consys {
|
|
polling-delay = <0>; /* milliseconds */
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
thermal-sensors = <&consys>;
|
|
};
|
|
};
|
|
|
|
lastbus: lastbus {
|
|
compatible = "mediatek,lastbus";
|
|
enabled = <1>;
|
|
sw_version = <1>;
|
|
timeout_ms = <200>;
|
|
timeout_type = <0>;
|
|
monitors {
|
|
monitor1 {
|
|
monitor_name = "debug_ctrl_ao_INFRA_AO";
|
|
base = <0x10023000>;
|
|
idle_masks = <0x1c 0x08000000>;
|
|
num_ports = <62>;
|
|
bus_freq_mhz = <78>;
|
|
};
|
|
monitor2 {
|
|
monitor_name = "debug_ctrl_ao_INFRA_AO1";
|
|
base = <0x1002b000>;
|
|
num_ports = <16>;
|
|
bus_freq_mhz = <78>;
|
|
};
|
|
monitor3 {
|
|
monitor_name = "debug_ctrl_ao_NEMI_AO";
|
|
base = <0x10042000>;
|
|
idle_masks = <0xc 0xffff8000>,
|
|
<0x10 0x3fff>;
|
|
num_ports = <17>;
|
|
bus_freq_mhz = <688>;
|
|
};
|
|
monitor4 {
|
|
monitor_name = "debug_ctrl_ao_PERI_PAR_AO";
|
|
base = <0x11037000>;
|
|
num_ports = <19>;
|
|
bus_freq_mhz = <78>;
|
|
};
|
|
monitor5 {
|
|
monitor_name = "debug_ctrl_ao_VLP_AO";
|
|
base = <0x1c01d000>;
|
|
num_ports = <13>;
|
|
bus_freq_mhz = <156>;
|
|
};
|
|
monitor6 {
|
|
monitor_name = "debug_ctrl_ao_MM_AO";
|
|
base = <0x1e825000>;
|
|
num_ports = <24>;
|
|
bus_freq_mhz = <688>;
|
|
};
|
|
monitor7 {
|
|
monitor_name = "debug_ctrl_ao_MMUP_AO";
|
|
base = <0x1ec51000>;
|
|
num_ports = <13>;
|
|
bus_freq_mhz = <728>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lk_charger: lk_charger {
|
|
compatible = "mediatek,lk_charger";
|
|
enable_anime;
|
|
/* enable_pe_plus; */
|
|
enable_pd20_reset;
|
|
power_path_support;
|
|
max_charger_voltage = <6500000>;
|
|
fast_charge_voltage = <3000000>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
non_std_ac_charger_current = <500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
ta_ac_charger_current = <3000000>;
|
|
pd_charger_current = <500000>;
|
|
|
|
/* battery temperature protection */
|
|
temp_t4_threshold = <50>;
|
|
temp_t3_threshold = <45>;
|
|
temp_t1_threshold = <0>;
|
|
|
|
/* enable check vsys voltage */
|
|
enable_check_vsys;
|
|
};
|
|
|
|
pe: pe {
|
|
compatible = "mediatek,charger,pe";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
ta_12v_support;
|
|
ta_9v_support;
|
|
|
|
pe_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
ta_ac_12v_input_current = <3200000>;
|
|
ta_ac_9v_input_current = <3200000>;
|
|
ta_ac_7v_input_current = <3200000>;
|
|
pe_charger_current = <3000000>;
|
|
vbat_threshold = <4150>;
|
|
};
|
|
|
|
pe2: pe2 {
|
|
compatible = "mediatek,charger,pe2";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
/* PE 2.0 */
|
|
pe20_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* cable measurement impedance */
|
|
cable_imp_threshold = <699>;
|
|
vbat_cable_imp_threshold = <3900000>; /* uV */
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
vbat_threshold = <4150>;
|
|
};
|
|
|
|
pdc: pdc {
|
|
compatible = "mediatek,charger,pd";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min-charger-voltage = <4600000>;
|
|
pd-vbus-low-bound = <5000000>;
|
|
pd-vbus-upper-bound = <5000000>;
|
|
vsys-watt = <5000000>;
|
|
ibus-err = <14>;
|
|
|
|
pd-stop-battery-soc = <80>;
|
|
|
|
/* single charger */
|
|
sc-input-current = <3200000>;
|
|
sc-charger-current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs-input-current = <3200000>;
|
|
dcs-chg1-charger-current = <1500000>;
|
|
dcs-chg2-charger-current = <1500000>;
|
|
|
|
/* dual charger */
|
|
dual-polling-ieoc = <450000>;
|
|
slave-mivr-diff = <100000>;
|
|
vbat-threshold = <4150>;
|
|
|
|
/* rcable */
|
|
enable-inductor-protect = <1>;
|
|
};
|
|
|
|
pe45: pe45 {
|
|
compatible = "mediatek,charger,pe45";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min-charger-voltage = <4600000>;
|
|
pe45-stop-battery-soc = <80>;
|
|
|
|
high-temp-to-leave-pe45 = <46>;
|
|
high-temp-to-enter-pe45 = <39>;
|
|
low-temp-to-leave-pe45 = <10>;
|
|
low-temp-to-enter-pe45 = <16>;
|
|
ibus-err = <14>;
|
|
|
|
/* PE 4.5 cable impedance (mohm) */
|
|
pe45-r-cable-1a-lower = <500>;
|
|
pe45-r-cable-2a-lower = <351>;
|
|
pe45-r-cable-3a-lower = <240>;
|
|
pe45-r-cable-level = <200 300 400 500 500>;
|
|
pe45-r-cable-voltage = <5000 5500 6000 6500 7000>;
|
|
pe45-r-cable-current-limit = <3000 3000 3000 2500 2200>;
|
|
|
|
/* single charger */
|
|
sc-input-current = <3200000>;
|
|
sc-charger-current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs-input-current = <3200000>;
|
|
dcs-chg1-charger-current = <1500000>;
|
|
dcs-chg2-charger-current = <1500000>;
|
|
|
|
dual-polling-ieoc = <450000>;
|
|
slave-mivr-diff = <100000>;
|
|
vbat-threshold = <4150>;
|
|
};
|
|
|
|
pe5: pe5 {
|
|
compatible = "mediatek,charger,pe5";
|
|
gauge = <&mtk_gauge>;
|
|
polling_interval = <10000>;
|
|
ta_cv_ss_repeat_tmin = <25>;
|
|
vbat_cv = <4350>;
|
|
start_soc_min = <0>;
|
|
start_soc_max = <80>;
|
|
start_vbat_max = <4300>;
|
|
idvchg_term = <500>;
|
|
idvchg_step = <50>;
|
|
ita_level = <3000 2500 2000 1500>;
|
|
rcable_level = <250 300 375 500>;
|
|
ita_level_dual = <5000 3700 3400 3000>;
|
|
rcable_level_dual = <230 350 450 550>;
|
|
idvchg_ss_init = <1000>;
|
|
idvchg_ss_step = <250>;
|
|
idvchg_ss_step1 = <100>;
|
|
idvchg_ss_step2 = <50>;
|
|
idvchg_ss_step1_vbat = <4000>;
|
|
idvchg_ss_step2_vbat = <4200>;
|
|
ta_blanking = <400>;
|
|
swchg_aicr = <0>;
|
|
swchg_ichg = <1200>;
|
|
swchg_aicr_ss_init = <400>;
|
|
swchg_aicr_ss_step = <200>;
|
|
swchg_off_vbat = <4250>;
|
|
force_ta_cv_vbat = <4250>;
|
|
chg_time_max = <5400>;
|
|
tta_level_def = <0 0 0 0 25 50 60 70 80>;
|
|
tta_curlmt = <0 0 0 0 0 300 600 900 (-1)>;
|
|
tta_recovery_area = <3>;
|
|
tbat_level_def = <0 0 0 5 25 40 43 46 50>;
|
|
tbat_curlmt = <(-1) (-1) (-1) 300 0 600 900 1050 (-1)>;
|
|
tbat_recovery_area = <3>;
|
|
tdvchg_level_def = <0 0 0 5 25 55 60 65 70>;
|
|
tdvchg_curlmt = <(-1) (-1) (-1) 300 0 300 600 900 (-1)>;
|
|
tdvchg_recovery_area = <3>;
|
|
tswchg_level_def = <0 0 0 5 25 65 70 75 80>;
|
|
tswchg_curlmt = <(-1) (-1) (-1) 200 0 200 300 400 (-1)>;
|
|
tswchg_recovery_area = <3>;
|
|
ifod_threshold = <200>;
|
|
rsw_min = <20>;
|
|
ircmp_rbat = <40>;
|
|
ircmp_vclamp = <0>;
|
|
vta_cap_min = <6800>;
|
|
vta_cap_max = <11000>;
|
|
ita_cap_min = <1000>;
|
|
support_ta = "pca_ta_pps", "pd_adapter";
|
|
allow_not_check_ta_status;
|
|
vbat_threshold = <4150>;
|
|
};
|
|
|
|
charger: charger {
|
|
compatible = "mediatek,charger";
|
|
gauge = <&mtk_gauge>;
|
|
charger = <&mt6375_chg>;
|
|
bootmode = <&chosen>;
|
|
|
|
algorithm_name = "Basic";
|
|
charger_configuration= <0>;
|
|
|
|
/* common */
|
|
battery_cv = <4350000>;
|
|
max_charger_voltage = <6500000>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* sw jeita */
|
|
enable_vbat_mon= <1>;
|
|
/* enable_sw_jeita; */
|
|
jeita_temp_above_t4_cv = <4240000>;
|
|
jeita_temp_t3_to_t4_cv = <4240000>;
|
|
jeita_temp_t2_to_t3_cv = <4340000>;
|
|
jeita_temp_t1_to_t2_cv = <4240000>;
|
|
jeita_temp_t0_to_t1_cv = <4040000>;
|
|
jeita_temp_below_t0_cv = <4040000>;
|
|
temp_t4_thres = <50>;
|
|
temp_t4_thres_minus_x_degree = <47>;
|
|
temp_t3_thres = <45>;
|
|
temp_t3_thres_minus_x_degree = <39>;
|
|
temp_t2_thres = <10>;
|
|
temp_t2_thres_plus_x_degree = <16>;
|
|
temp_t1_thres = <0>;
|
|
temp_t1_thres_plus_x_degree = <6>;
|
|
temp_t0_thres = <0>;
|
|
temp_t0_thres_plus_x_degree = <0>;
|
|
temp_neg_10_thres = <0>;
|
|
|
|
/* battery temperature protection */
|
|
enable_min_charge_temp;
|
|
min_charge_temp = <0>;
|
|
min_charge_temp_plus_x_degree = <6>;
|
|
max_charge_temp = <50>;
|
|
max_charge_temp_minus_x_degree = <47>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
charging_host_charger_current = <1500000>;
|
|
|
|
/* dynamic mivr */
|
|
enable_dynamic_mivr;
|
|
min_charger_voltage_1 = <4400000>;
|
|
min_charger_voltage_2 = <4200000>;
|
|
max_dmivr_charger_current = <1800000>;
|
|
|
|
/* fast charging algo support indicator */
|
|
enable_fast_charging_indicator;
|
|
};
|
|
|
|
logstore: logstore {
|
|
enabled = <1>;
|
|
pmic-register = <0xa0d>;
|
|
};
|
|
|
|
bus_parity {
|
|
compatible = "mediatek,bus-parity";
|
|
reg = <0 0x0c000900 0 0x20>, /* MST_EMI0_CH0 */
|
|
<0 0x0c000920 0 0x20>, /* MST_EMI0_CH1 */
|
|
<0 0x0c000980 0 0x20>, /* MST_INFRA */
|
|
<0 0x0c0009a0 0 0x30>, /* SLV_L3GIC */
|
|
<0 0x10270600 0 0x20>, /* MCU2EMI_M0 */
|
|
<0 0x10270620 0 0x20>, /* MCU2EMI_M1 */
|
|
<0 0x100017a8 0 0x14>, /* MCU2IFR_REG */
|
|
<0 0x100017bc 0 0x8>, /* INF_L3C2MCU */
|
|
<0 0x0c0009dc 0 0x4>; /* BUS_PARITY_FAIL */
|
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>, /* MCU */
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; /* Infra */
|
|
interrupt-names = "mcu-bus-parity", "infra-bus-parity";
|
|
|
|
mcu-names = "MST_EMI0_CH0", "MST_EMI0_CH1", "MST_INFRA", "SLV_L3GIC";
|
|
infra-names = "MCU2EMI_M0", "MCU2EMI_M1", "MCU2IFR_REG", "INF_L3C2MCU";
|
|
|
|
/* 0:master, 1:slave, 2:emi */
|
|
mcu-types = <0 0 0 1>;
|
|
infra-types = <2 2 1 0>;
|
|
|
|
/* offset of MST_XXX_LOG_RD0/SLV_XXX_LOG_WD0 for mcu bpm */
|
|
mcu-rd0wd0-offset = <0x0c 0x0c 0x0c 0x24>;
|
|
|
|
/* shift of parity fail bit in BUS_PARITY_FAIL for mcu bpm */
|
|
mcu-fail-bit-shift = <0 1 4 5>;
|
|
|
|
mcu-data-len = <4 4 4 2>;
|
|
};
|
|
|
|
bus_tracer@d040000 {
|
|
compatible = "mediatek,bus_tracer-v1";
|
|
reg = <0 0x0d040000 0 0x1000>, /* dem base */
|
|
<0 0x0d01a000 0 0x1000>, /* dbgao base */
|
|
<0 0x0d041000 0 0x3000>, /* funnel/rep/etr base */
|
|
<0 0x0d044000 0 0x1000>, /* bus tracer etf base */
|
|
<0 0x0d040800 0 0x100>, /* ap bus tracer base */
|
|
<0 0x0d040900 0 0x100>; /* infra bus tracer base */
|
|
|
|
mediatek,err-flag = <0xfff8ffff>;
|
|
|
|
/*
|
|
* index 0 for ap bus tracer
|
|
* index 1 for infra bus tracer
|
|
* enabled_tracer disabled by default
|
|
*/
|
|
mediatek,num-tracer = <2>;
|
|
mediatek,enabled-tracer = <0 1>;
|
|
mediatek,at-id = <0x10 0x30>;
|
|
|
|
/* filters: disabled by default */
|
|
/*
|
|
* mediatek,watchpoint-filter = <0x0 0x10010000 0xfffff000>;
|
|
* mediatek,bypass-filter = <0x14000000 0xffff0000>;
|
|
* mediatek,id-filter = <0x10 0x40>;
|
|
* mediatek,rw-filter = <0x0 0x1>;
|
|
*/
|
|
};
|
|
|
|
bus_dbg@10208000 {
|
|
compatible = "mediatek,bus_dbg";
|
|
reg = <0 0x10208000 0 0x1000>;
|
|
};
|
|
|
|
emicen: emicen@10219000 {
|
|
compatible = "mediatek,mt6877-emicen",
|
|
"mediatek,common-emicen";
|
|
reg = <0 0x10219000 0 0x1000>;
|
|
mediatek,emi-reg = <&emichn>;
|
|
a2d_hash = <0xb>;
|
|
a2d_disph = <0>;
|
|
};
|
|
|
|
emichn: emichn@10235000 {
|
|
compatible = "mediatek,mt6877-emichn",
|
|
"mediatek,common-emichn";
|
|
reg = <0 0x10235000 0 0x1000>,
|
|
<0 0x10245000 0 0x1000>;
|
|
};
|
|
|
|
emi-fake-eng@1026c000 {
|
|
compatible = "mediatek,emi-fake-engine";
|
|
reg = <0 0x1026c000 0 0x1000>,
|
|
<0 0x1026d000 0 0x1000>;
|
|
};
|
|
|
|
emiisu {
|
|
compatible = "mediatek,mt6983-emiisu",
|
|
"mediatek,common-emiisu";
|
|
ctrl_intf = <1>;
|
|
};
|
|
|
|
emimpu: emimpu@10226000 {
|
|
compatible = "mediatek,mt6983-emimpu";
|
|
reg = <0 0x10226000 0 0x1000>;
|
|
mediatek,emi-reg = <&emicen>;
|
|
mediatek,miukp-reg = <&miukp>;
|
|
mediatek,miumpu-reg = <&miumpu>;
|
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
sr_cnt = <63>;
|
|
aid_cnt = <256>;
|
|
aid_num_per_set = <32>;
|
|
dump = <0x1f0 0x1f8 0x1fc>;
|
|
clear = <0x1f0 0x80000000 1>,
|
|
<0x160 0xffffffff 16>,
|
|
<0x200 0x00000003 16>;
|
|
clear_hp = <0x1fc 0x40000000 1>;
|
|
clear_md = <0x1fc 0x80000000 1>;
|
|
};
|
|
|
|
miukp: miukp@10351000 {
|
|
compatible = "mediatek,common-miukp";
|
|
reg = <0 0x10351000 0 0x1000>;
|
|
dump = <0xc00 0xc04 0xc10 0xc14>;
|
|
clear = <0x410 0x1 1>,
|
|
<0x410 0x0 1>;
|
|
vio-info = <0x1 0xf 0x3 0xf>;
|
|
};
|
|
|
|
miumpu: miumpu@10351000 {
|
|
compatible = "mediatek,common-miumpu";
|
|
reg = <0 0x10351000 0 0x1000>;
|
|
dump = <0xe00 0xe08 0xe0c 0xe10 0xe14 0xe18 0xe1c 0xe20 0xe28
|
|
0xe80 0xe88 0xe8c 0xe90 0xe94 0xe98 0xe9c 0xea0 0xea8>;
|
|
clear = <0xe00 0x1 1>,
|
|
<0xe00 0x0 1>,
|
|
<0xe80 0x1 1>,
|
|
<0xe80 0x0 1>;
|
|
vio-info = <0x0 0x2 0x9 0x2>;
|
|
bypass = <0xe1c 0xe9c 0xe28 0xea8>;
|
|
bypass-axi = <0x6 0x7f80 0x2000 0x7 0xff81 0x4001>;
|
|
};
|
|
|
|
emislb: emislb@10342000 {
|
|
compatible = "mediatek,common-emislb";
|
|
reg = <0 0x10342000 0 0x1000>;
|
|
mediatek,emimpu-reg = <&emimpu>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dump = <0xd14 0xd18 0xd1c 0xd20 0xd24>;
|
|
clear = <0x680 0x80000000 1>;
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
|
|
hwrng: hwrng {
|
|
compatible = "arm,sec-rng";
|
|
methods = "smc";
|
|
method-fid = /bits/ 16 <0x26a>;
|
|
quality = /bits/ 16 <900>;
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0 0x40000000 0 0x40000000>;
|
|
};
|
|
|
|
odm: odm {
|
|
compatible = "simple-bus";
|
|
/* reserved for overlay by odm */
|
|
};
|
|
|
|
uarthub: uarthub {
|
|
compatible = "mediatek,mt6886-uarthub";
|
|
uarthub_disable = <1>;
|
|
};
|
|
|
|
reserved_memory: reserved-memory {
|
|
/*TODO: add reserved memory node here*/
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
reserve-memory-scp_share {
|
|
compatible = "mediatek,reserve-memory-scp_share";
|
|
no-map;
|
|
size = <0 0x00600000>; /* 6MB */
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x50000000 0 0x40000000>;
|
|
};
|
|
|
|
ssmr_cma_mem: ssmr-reserved-cma_memory {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0 0x10000000>;
|
|
alignment = <0 0x1000000>;
|
|
};
|
|
|
|
ssheap_cma_mem: ssheap-reserved-cma_memory {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0 0x10000000>;
|
|
alignment = <0 0x200000>;
|
|
};
|
|
|
|
dpmaif_resv_cache_mem: ccci_dpmaif_cache-memory {
|
|
compatible = "mediatek,dpmaif-resv-cache-mem";
|
|
size = <0 0x00190000>; /* 1638400 Bytes for 1rxq */
|
|
alignment = <0 0x1000>;
|
|
alloc-ranges = <0 0x40000000 0 0xF0000000>;
|
|
};
|
|
|
|
dpmaif_resv_nocache_mem: ccci_dpmaif_nocache-memory {
|
|
compatible = "mediatek,dpmaif-resv-nocache-mem";
|
|
no-map;
|
|
size = <0 0x0050000>; /* 327680 Bytes */
|
|
alignment = <0 0x1000>;
|
|
alloc-ranges = <0 0x40000000 0 0xF0000000>;
|
|
};
|
|
};
|
|
|
|
memory_ssmr_features: memory-ssmr-features {
|
|
compatible = "mediatek,memory-ssmr-features";
|
|
svp-region-based-size = <0 0x6000000>;
|
|
svp-page-based-size = <0 0x38000000>;
|
|
tui-size = <0 0x4000000>;
|
|
wfd-region-based-size = <0 0x4000000>;
|
|
wfd-page-based-size = <0 0x4000000>;
|
|
prot-region-based-size = <0 0x8000000>;
|
|
prot-page-based-size = <0 0>;
|
|
sapu-data-shm-size = <0 0x1000000>;
|
|
};
|
|
|
|
ssmr {
|
|
compatible = "mediatek,trusted_mem";
|
|
memory-region = <&ssmr_cma_mem>;
|
|
};
|
|
|
|
ssheap {
|
|
compatible = "mediatek,trusted_mem_ssheap";
|
|
memory-region = <&ssheap_cma_mem>;
|
|
};
|
|
|
|
drm_wv: drm_wv {
|
|
compatible = "mediatek,drm_wv";
|
|
status = "okay";
|
|
};
|
|
|
|
mtee_svp: mtee_svp {
|
|
compatible = "medaitek,svp";
|
|
};
|
|
|
|
clk_ao: clk_ao {
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
clkitg: clkitg {
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
disable_unused: disable_unused {
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
clkchk {
|
|
compatible = "mediatek,mt6886-clkchk";
|
|
};
|
|
|
|
pdchk {
|
|
compatible = "mediatek,mt6886-pdchk";
|
|
};
|
|
|
|
clocks {
|
|
clk32k: clk32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
};
|
|
clk26m: clk26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
};
|
|
clk13m: clk13m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
ulposc: ulposc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <260000000>;
|
|
};
|
|
ulposc2: ulposc2 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <700000000>;
|
|
};
|
|
clk10m: clk10m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <10000000>;
|
|
};
|
|
};
|
|
|
|
cpuhvfs: cpuhvfs@114400 {
|
|
compatible = "mediatek,cpufreq-hybrid";
|
|
reg = <0 0x00114400 0 0xc00>,
|
|
<0 0x0011bc00 0 0x1400>,
|
|
<0 0x00118000 0 0x800>,
|
|
<0 0x00114f40 0 0xc0>;
|
|
reg-names = "USRAM", "CSRAM", "ESRAM";
|
|
cslog-range = <0x03d0>, <0x0fa0>;
|
|
tbl-off = <4>, <76>, <148>;
|
|
|
|
/* pll mcucfg */
|
|
mcucfg-ver = <0>;
|
|
apmixedsys = <&cpu_pll>;
|
|
clk-div-base = <&cpu_mcucfg>;
|
|
pll-con = <0x40c>, <0x80c>, <0x00c>;
|
|
clk-div = <0x10c>, <0x118>, <0x100>;
|
|
|
|
/* regulator */
|
|
proc1-supply = <&mt6363_vbuck2>; //L
|
|
proc2-supply = <&mt6319_6_vbuck1>; //B
|
|
proc3-supply = <&mt6363_vbuck2>; //DSU
|
|
|
|
// /* leakage info */
|
|
// nvmem-cells = <&lkginfo>;
|
|
// nvmem-cell-names = "lkginfo";
|
|
};
|
|
|
|
hwv: syscon@10320000 {
|
|
compatible = "mediatek,mt6886-hwv", "syscon";
|
|
reg = <0 0x10320000 0 0x2000>;
|
|
};
|
|
|
|
topckgen_clk: syscon@10000000 {
|
|
compatible = "mediatek,mt6886-topckgen", "syscon";
|
|
reg = <0 0x10000000 0 0x1000>;
|
|
hw-voter-regmap = <&hwv>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg_ao_clk: syscon@10001000 {
|
|
compatible = "mediatek,mt6886-infracfg_ao", "syscon";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apmixedsys_clk: syscon@1000c000 {
|
|
compatible = "mediatek,mt6886-apmixedsys", "syscon";
|
|
reg = <0 0x1000c000 0 0x1000>;
|
|
hw-voter-regmap = <&hwv>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
emi_bus_clk: syscon@10270000 {
|
|
compatible = "mediatek,mt6886-emi_bus", "syscon";
|
|
reg = <0 0x10270000 0 0x1000>;
|
|
};
|
|
|
|
pericfg_ao_clk: syscon@11036000 {
|
|
compatible = "mediatek,mt6886-pericfg_ao", "syscon";
|
|
reg = <0 0x11036000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
afe_clk: syscon@11050000 {
|
|
compatible = "mediatek,mt6886-audiosys", "syscon";
|
|
reg = <0 0x11050000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imp_iic_wrap_c_clk: syscon@11284000 {
|
|
compatible = "mediatek,mt6886-imp_iic_wrap_c", "syscon";
|
|
reg = <0 0x11284000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
ufscfg_ao_clk: syscon@112b8000 {
|
|
compatible = "mediatek,mt6886-ufscfg_ao", "syscon", "simple-mfd";
|
|
reg = <0 0x112b8000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
|
|
ufsaocfg_rst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
|
|
ti,reset-bits = <
|
|
/* ufs unipro reset */
|
|
/* 8: unipro */
|
|
0x48 8 0x4c 8 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
>;
|
|
};
|
|
};
|
|
|
|
ufscfg_pdn_clk: syscon@112bc000 {
|
|
compatible = "mediatek,mt6886-ufscfg_pdn", "syscon", "simple-mfd";
|
|
reg = <0 0x112bc000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
|
|
ufspdncfg_rst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
|
|
ti,reset-bits = <
|
|
/* ufs ufshci/crypto reset */
|
|
/* 0: ufs-crypto */
|
|
0x48 0 0x4c 0 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
/* 1: ufshci */
|
|
0x48 1 0x4c 1 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
>;
|
|
};
|
|
};
|
|
|
|
imp_iic_wrap_es_clk: syscon@11c73000 {
|
|
compatible = "mediatek,mt6886-imp_iic_wrap_es", "syscon";
|
|
reg = <0 0x11c73000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imp_iic_wrap_w_clk: syscon@11e02000 {
|
|
compatible = "mediatek,mt6886-imp_iic_wrap_w", "syscon";
|
|
reg = <0 0x11e02000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imp_iic_wrap_e_clk: syscon@11e83000 {
|
|
compatible = "mediatek,mt6886-imp_iic_wrap_e", "syscon";
|
|
reg = <0 0x11e83000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpusys: power-controller@13f91000 {
|
|
compatible = "mediatek,mt6886-gpusys", "syscon";
|
|
reg = <0 0x13f91000 0 0x1000>;
|
|
#power-domain-cells = <1>;
|
|
infracfg = <&infracfg_ao_clk>;
|
|
emi-bus = <&emi_bus_clk>;
|
|
ufscfg-ao-bus = <&ufscfg_ao_clk>;
|
|
gpu_eb_rpc = <&gpusys>;
|
|
img_sub0_bus = <&img_sub0_bus_clk>;
|
|
img_sub1_bus = <&img_sub1_bus_clk>;
|
|
cam_sub0_bus = <&cam_sub0_bus_clk>;
|
|
cam_sub2_bus = <&cam_sub2_bus_clk>;
|
|
cam_sub1_bus = <&cam_sub1_bus_clk>;
|
|
vlpcfg = <&vlpcfg_bus>;
|
|
};
|
|
|
|
mfgpll_pll_ctrl_clk: syscon@13fa0000 {
|
|
compatible = "mediatek,mt6886-mfgpll_pll_ctrl", "syscon";
|
|
reg = <0 0x13fa0000 0 0x0800>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mfgscpll_pll_ctrl_clk: syscon@13fa0c00 {
|
|
compatible = "mediatek,mt6886-mfgscpll_pll_ctrl", "syscon";
|
|
reg = <0 0x13fa0c00 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dispsys_config_clk: syscon@14000000 {
|
|
compatible = "mediatek,mt6886-mmsys0", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imgsys_main_clk: syscon@15000000 {
|
|
compatible = "mediatek,mt6886-imgsys_main", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
img_sub0_bus_clk: syscon@15002000 {
|
|
compatible = "mediatek,mt6886-img_sub0_bus", "syscon";
|
|
reg = <0 0x15002000 0 0x1000>;
|
|
};
|
|
|
|
img_sub1_bus_clk: syscon@15003000 {
|
|
compatible = "mediatek,mt6886-img_sub1_bus", "syscon";
|
|
reg = <0 0x15003000 0 0x1000>;
|
|
};
|
|
|
|
dip_top_dip1_clk: syscon@15110000 {
|
|
compatible = "mediatek,mt6886-dip_top_dip1", "syscon";
|
|
reg = <0 0x15110000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dip_nr1_dip1_clk: syscon@15130000 {
|
|
compatible = "mediatek,mt6886-dip_nr1_dip1", "syscon";
|
|
reg = <0 0x15130000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dip_nr2_dip1_clk: syscon@15170000 {
|
|
compatible = "mediatek,mt6886-dip_nr2_dip1", "syscon";
|
|
reg = <0 0x15170000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
wpe1_dip1_clk: syscon@15220000 {
|
|
compatible = "mediatek,mt6886-wpe1_dip1", "syscon";
|
|
reg = <0 0x15220000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
wpe2_dip1_clk: syscon@15520000 {
|
|
compatible = "mediatek,mt6886-wpe2_dip1", "syscon";
|
|
reg = <0 0x15520000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
wpe3_dip1_clk: syscon@15620000 {
|
|
compatible = "mediatek,mt6886-wpe3_dip1", "syscon";
|
|
reg = <0 0x15620000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
traw_dip1_clk: syscon@15710000 {
|
|
compatible = "mediatek,mt6886-traw_dip1", "syscon";
|
|
reg = <0 0x15710000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vdec_gcon_base_clk: syscon@1602f000 {
|
|
compatible = "mediatek,mt6886-vdecsys", "syscon";
|
|
reg = <0 0x1602f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
venc_gcon_clk: syscon@17000000 {
|
|
compatible = "mediatek,mt6886-vencsys", "syscon";
|
|
reg = <0 0x17000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cam_sub0_bus_clk: syscon@1a005000 {
|
|
compatible = "mediatek,mt6886-cam_sub0_bus", "syscon";
|
|
reg = <0 0x1a005000 0 0x1000>;
|
|
};
|
|
|
|
cam_sub2_bus_clk: syscon@1a006000 {
|
|
compatible = "mediatek,mt6886-cam_sub2_bus", "syscon";
|
|
reg = <0 0x1a006000 0 0x1000>;
|
|
};
|
|
|
|
cam_sub1_bus_clk: syscon@1a007000 {
|
|
compatible = "mediatek,mt6886-cam_sub1_bus", "syscon";
|
|
reg = <0 0x1a007000 0 0x1000>;
|
|
};
|
|
|
|
scpsys: power-controller@1c001000 {
|
|
compatible = "mediatek,mt6886-scpsys", "syscon";
|
|
reg = <0 0x1c001000 0 0x1000>;
|
|
#power-domain-cells = <1>;
|
|
clocks = <&topckgen_clk CLK_TOP_ADSP_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CCUSYS_SEL>,
|
|
<&topckgen_clk CLK_TOP_CCU_AHB_SEL>,
|
|
<&topckgen_clk CLK_TOP_DISP0_SEL>,
|
|
<&topckgen_clk CLK_TOP_MDP0_SEL>,
|
|
<&topckgen_clk CLK_TOP_MMINFRA_SEL>,
|
|
<&topckgen_clk CLK_TOP_MMUP_SEL>,
|
|
<&topckgen_clk CLK_TOP_IMG1_SEL>,
|
|
<&topckgen_clk CLK_TOP_VDEC_SEL>,
|
|
<&topckgen_clk CLK_TOP_VENC_SEL>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2SYS_GALS_CON_0>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&mdpsys_config_clk CLK_MDP_SMI0>,
|
|
<&imgsys_main_clk CLK_IMG_LARB12>,
|
|
<&imgsys_main_clk CLK_IMG_LARB9>,
|
|
<&imgsys_main_clk CLK_IMG_VCORE_GALS>,
|
|
<&imgsys_main_clk CLK_IMG_GALS>,
|
|
<&imgsys_main_clk CLK_IMG_IPE>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_SUBA_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_SUBB_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&imgsys_main_clk CLK_IMG_TRAW0>,
|
|
<&imgsys_main_clk CLK_IMG_DIP0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE1>,
|
|
<&imgsys_main_clk CLK_IMG_WPE2>,
|
|
<&pericfg_ao_clk CLK_PERAO_AUDIO_SLV_CKP>,
|
|
<&pericfg_ao_clk CLK_PERAO_AUDIO_MST_CKP>,
|
|
<&pericfg_ao_clk CLK_PERAO_INTBUS_CKP>;
|
|
clock-names = "adsp", "audio", "cam", "ccu", "ccu_ahb",
|
|
"disp", "mdp", "mm_infra", "mmup", "isp",
|
|
"vde", "ven",
|
|
"cam-0", "cam-1", "cam-2", "cam-3",
|
|
"cam_lp-0", "cam_lp-1", "cam_lp-2",
|
|
"disp-0", "mdp-0", "isp-0", "isp-1", "isp-2",
|
|
"isp-3", "isp-4", "vde0-0", "cam_suba-0",
|
|
"cam_subb-0", "cam_mraw-0", "dip1-0", "dip1-1",
|
|
"dip1-2", "dip1-3", "dip1-4", "audio-0", "audio-1",
|
|
"audio-2";
|
|
infracfg = <&infracfg_ao_clk>;
|
|
emi-bus = <&emi_bus_clk>;
|
|
ufscfg-ao-bus = <&ufscfg_ao_clk>;
|
|
gpu_eb_rpc = <&gpusys>;
|
|
img_sub0_bus = <&img_sub0_bus_clk>;
|
|
img_sub1_bus = <&img_sub1_bus_clk>;
|
|
cam_sub0_bus = <&cam_sub0_bus_clk>;
|
|
cam_sub2_bus = <&cam_sub2_bus_clk>;
|
|
cam_sub1_bus = <&cam_sub1_bus_clk>;
|
|
vlpcfg = <&vlpcfg_bus>;
|
|
isp_main-supply = <&mt6319_6_vbuck3>;
|
|
cam_main-supply = <&mt6319_6_vbuck3>;
|
|
};
|
|
|
|
vlpcfg_bus: syscon@1c00c000 {
|
|
compatible = "mediatek,mt6886-vlpcfg_bus", "syscon";
|
|
reg = <0 0x1c00c000 0 0x1000>;
|
|
};
|
|
|
|
vlp_cksys_clk: syscon@1c013000 {
|
|
compatible = "mediatek,mt6886-vlp_cksys", "syscon";
|
|
reg = <0 0x1c013000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
scp_clk: syscon@1c721000 {
|
|
compatible = "mediatek,mt6886-scp", "syscon";
|
|
reg = <0 0x1c721000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
scp_iic_clk: syscon@1c7b7000 {
|
|
compatible = "mediatek,mt6886-scp_iic", "syscon";
|
|
reg = <0 0x1c7b7000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_main_clk: syscon@1a000000 {
|
|
compatible = "mediatek,mt6886-camsys_main", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_rawa_clk: syscon@1a04f000 {
|
|
compatible = "mediatek,mt6886-camsys_rawa", "syscon";
|
|
reg = <0 0x1a04f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_yuva_clk: syscon@1a06f000 {
|
|
compatible = "mediatek,mt6886-camsys_yuva", "syscon";
|
|
reg = <0 0x1a06f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_rawb_clk: syscon@1a08f000 {
|
|
compatible = "mediatek,mt6886-camsys_rawb", "syscon";
|
|
reg = <0 0x1a08f000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_yuvb_clk: syscon@1a0af000 {
|
|
compatible = "mediatek,mt6886-camsys_yuvb", "syscon";
|
|
reg = <0 0x1a0af000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_mraw_clk: syscon@1a170000 {
|
|
compatible = "mediatek,mt6886-camsys_mraw", "syscon";
|
|
reg = <0 0x1a170000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pda: pda@1a180000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,camera-pda";
|
|
reg = <0 0x1a180000 0 0x1000>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&camsys_mraw_clk CLK_CAM_MR_PDA0>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_PDA1>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>;
|
|
clock-names = "camsys_mraw_pda0",
|
|
"camsys_mraw_pda1",
|
|
"mraw_larbx",
|
|
"cam_main_cam2mm0_gals_cg_con",
|
|
"cam_main_cam2mm1_gals_cg_con",
|
|
"cam_main_cam_cg_con";
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
mediatek,larbs = <&smi_larb25>;
|
|
iommus = <&disp_iommu M4U_PORT_L25_PDAI_A_0>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_1>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_2>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_3>,
|
|
<&disp_iommu M4U_PORT_L25_PDAI_A_4>,
|
|
<&disp_iommu M4U_PORT_L25_PDAO_A_0>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_2)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_3)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_4)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAO_A_0)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "l25_pdai_a0",
|
|
"l25_pdai_a1",
|
|
"l25_pdai_a2",
|
|
"l25_pdai_a3",
|
|
"l25_pdai_a4",
|
|
"l25_pdao_a";
|
|
};
|
|
|
|
vmmspm: vmmspm {
|
|
compatible = "mediatek,vmm_spm_mt6886";
|
|
reg = <0 0x1c001000 0 0x1000>; // sys_spm
|
|
reg-names = "SPM_BASE";
|
|
|
|
vmm-pmic-supply = <&mt6319_6_vbuck3>;
|
|
};
|
|
|
|
camera-fsync-ccu {
|
|
compatible = "mediatek,camera-fsync-ccu";
|
|
mediatek,ccu-rproc = <&ccu_rproc>;
|
|
};
|
|
|
|
camera-camsys-ccu {
|
|
compatible = "mediatek,camera-camsys-ccu";
|
|
mediatek,ccu-rproc = <&ccu_rproc>;
|
|
};
|
|
|
|
ccu_rproc: ccu_rproc@1b080000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,ccu_rproc";
|
|
reg = <0 0x1b080000 0 0x9000>;
|
|
interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>,
|
|
<&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
mediatek,larbs = <&smi_larb19>;
|
|
clocks = <&topckgen_clk CLK_TOP_CCUSYS>,
|
|
<&topckgen_clk CLK_TOP_CCU_AHB>,
|
|
<&ccu_main_clk CLK_CCU_LARB19>,
|
|
<&ccu_main_clk CLK_CCU_AHB>,
|
|
<&ccu_main_clk CLK_CCUSYS_CCU0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CCUSYS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2SYS_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>;
|
|
clock-names = "CLK_TOP_CCUSYS_SEL",
|
|
"CLK_TOP_CCU_AHB_SEL",
|
|
"CLK_CCU_LARB",
|
|
"CLK_CCU_AHB",
|
|
"CLK_CCUSYS_CCU0",
|
|
"CAM_CCUSYS",
|
|
"CAM_CAM2SYS_GALS",
|
|
"CAM_CAM2MM1_GALS",
|
|
"CAM_CAM2MM0_GALS",
|
|
"CAM_MRAW",
|
|
"CAM_CG";
|
|
mediatek,ccu_rproc1 = <&ccu_rproc1>;
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L19_CCUO>,
|
|
<&disp_iommu M4U_PORT_L19_CCUI>;
|
|
interconnects =
|
|
<&mmqos SLAVE_LARB(36) &mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_CCUO)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_CCUI)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"ccu_g",
|
|
"ccu_o",
|
|
"ccu_i";
|
|
secured = "yes";
|
|
ccu_version = <72>;
|
|
ccu_sramSize = <0x00010000>;
|
|
ccu_sramOffset = <0x00020000>;
|
|
ccu_dramSize = <0x00100000>;
|
|
ccu_dramAddr = <0x80000000>;
|
|
ccu_emiRegion = <20>;
|
|
};
|
|
|
|
ccu_rproc1: ccu_rproc1 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,ccu_rproc1";
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L19_CCUO2>,
|
|
<&disp_iommu M4U_PORT_L19_CCUI2>;
|
|
};
|
|
|
|
ccu_main_clk: syscon@1b200000 {
|
|
compatible = "mediatek,mt6886-ccu", "syscon";
|
|
reg = <0 0x1b200000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mminfra_config_clk: syscon@1e800000 {
|
|
compatible = "mediatek,mt6886-mminfra_config", "syscon";
|
|
reg = <0 0x1e800000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
ccipll_pll_ctrl_clk: syscon@c030000 {
|
|
compatible = "mediatek,mt6886-ccipll_pll_ctrl", "syscon";
|
|
reg = <0 0xc030000 0 0x0400>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
armpll_ll_pll_ctrl_clk: syscon@c030400 {
|
|
compatible = "mediatek,mt6886-armpll_ll_pll_ctrl", "syscon";
|
|
reg = <0 0xc030400 0 0x0400>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
armpll_bl_pll_ctrl_clk: syscon@c030800 {
|
|
compatible = "mediatek,mt6886-armpll_bl_pll_ctrl", "syscon";
|
|
reg = <0 0xc030800 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
ptppll_pll_ctrl_clk: syscon@c034000 {
|
|
compatible = "mediatek,mt6886-ptppll_pll_ctrl", "syscon";
|
|
reg = <0 0xc034000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dem_clk: syscon@d0a0000 {
|
|
compatible = "mediatek,mt6886-dem", "syscon";
|
|
reg = <0 0xd0a0000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mmqos-wrapper {
|
|
compatible = "mediatek,mt6886-mmqos-wrapper";
|
|
};
|
|
|
|
mmqos: interconnect {
|
|
compatible = "mediatek,mt6886-mmqos";
|
|
#mtk-interconnect-cells = <1>;
|
|
mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2
|
|
&smi_larb4 &smi_larb7 &smi_larb9
|
|
&smi_larb10 &smi_larb11 &smi_larb12
|
|
&smi_larb13 &smi_larb14 &smi_larb15
|
|
&smi_larb16 &smi_larb17 &smi_larb19
|
|
&smi_larb22 &smi_larb23 &smi_larb25
|
|
&smi_larb26 &smi_larb27 &smi_larb28
|
|
&smi_larb29 &smi_larb30 &smi_larb34>;
|
|
mediatek,commons = <&smi_disp_common>;
|
|
clocks = <&topckgen_clk CLK_TOP_MMINFRA_SEL>,
|
|
<&topckgen_clk CLK_TOP_MMINFRA_SEL>;
|
|
clock-names = "mm";
|
|
interconnects = <&dvfsrc MT6873_MASTER_MMSYS &dvfsrc MT6873_SLAVE_DDR_EMI>,
|
|
<&dvfsrc MT6873_MASTER_HRT_MMSYS
|
|
&dvfsrc MT6873_SLAVE_HRT_DDR_EMI>;
|
|
interconnect-names = "icc-bw", "icc-hrt-bw";
|
|
};
|
|
|
|
disp_ssc0_smi_2x1_sub_comm: disp-ssc0-smi-2x1-sub-comm@1e808000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1e808000 0 0x1000>;
|
|
mediatek,common-id = <3>;
|
|
init-power-on;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
disp_ssc1_smi_2x1_sub_comm: disp-ssc1-smi-2x1-sub-comm@1e809000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1e809000 0 0x1000>;
|
|
mediatek,common-id = <4>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
mmsram_smi_2x1_sub_comm3: mmsram-smi-2x1-sub-comm3@1e80b000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1e80b000 0 0x1000>;
|
|
mediatek,common-id = <7>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_disp_common: smi-disp-comm@1e801000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon";
|
|
reg = <0 0x1e801000 0 0x1000>;
|
|
mediatek,smi = <&disp_ssc0_smi_2x1_sub_comm &disp_ssc1_smi_2x1_sub_comm>;
|
|
mediatek,common-id = <0>;
|
|
mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
operating-points-v2 = <&opp_table_mdp>;
|
|
smi-common;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_sysram_common: smi-sysram-comm@1e80a000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon";
|
|
reg = <0 0x1e80a000 0 0x1000>;
|
|
mediatek,smi = <&mmsram_smi_2x1_sub_comm3>;
|
|
mediatek,common-id = <2>;
|
|
smi-common;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_3X1_sub_common: smi-3X1-sub-common@1e807000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1e807000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,common-id = <9>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
disp_mmsram_smi_subcomm: disp-mmsram-smi-subcomm@14023000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x14023000 0 0x1000>;
|
|
mediatek,smi = <&smi_sysram_common>;
|
|
mediatek,common-id = <10>;
|
|
init-power-on;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_DISP>;
|
|
clocks = <&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_img_4x1_subcomm0: smi-img-4x1-subcomm0@15002000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x15002000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,common-id = <11>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
clocks = <&imgsys_main_clk CLK_IMG_TRAW0>,
|
|
<&imgsys_main_clk CLK_IMG_DIP0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE1>,
|
|
<&imgsys_main_clk CLK_IMG_WPE2>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_img_5x1_subcomm1: smi-img-5x1-subcomm1@15003000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x15003000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,common-id = <12>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
clocks = <&imgsys_main_clk CLK_IMG_LARB9>,
|
|
<&imgsys_main_clk CLK_IMG_DIP0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE0>,
|
|
<&imgsys_main_clk CLK_IMG_IPE>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_disp_cam_7x1_subcomm0: smi-disp-cam-7x1-subcomm0@1a005000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1a005000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,common-id = <13>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_disp_cam_7x1_subcomm2: smi-disp-cam-7x1-subcomm2@1a006000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1a006000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,common-id = <15>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_sram_cam_2x1_subcomm2: smi-sram-cam-2x1-subcomm2@1a007000 {
|
|
compatible = "mediatek,mt6886-smi-common",
|
|
"mediatek,smi-common", "syscon", "mediatek,smi-sub-common";
|
|
reg = <0 0x1a007000 0 0x1000>;
|
|
mediatek,smi = <&smi_sysram_common>;
|
|
mediatek,common-id = <14>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>;
|
|
clock-names = "apb", "smi", "gals0", "gals1";
|
|
};
|
|
|
|
smi_pd_disp: smi-pd-disp {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_common &smi_sysram_common>;
|
|
mediatek,suspend-check-port = <0x3 0x1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_DISP>;
|
|
init-power-on;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_mdp: smi-pd-mdp {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_3X1_sub_common &smi_sysram_common>;
|
|
mediatek,suspend-check-port = <0x1 0x2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MDP0>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_vdec: smi-pd-vdec {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_common>;
|
|
mediatek,suspend-check-port = <0x8>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VDE0>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_venc: smi-pd-venc {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_3X1_sub_common &smi_sysram_common>;
|
|
mediatek,suspend-check-port = <0x2 0x4>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VEN0>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_isp_main: smi-pd-isp-main {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_common>;
|
|
mediatek,suspend-check-port = <0x30>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_isp_dip1: smi-pd-isp-dip1 {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_img_4x1_subcomm0 &smi_img_5x1_subcomm1>;
|
|
mediatek,suspend-check-port = <0xf 0x6>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_cam_main: smi-pd-cam-main {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_common &smi_sysram_common>;
|
|
mediatek,suspend-check-port = <0xc0 0x8>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_cam_suba: smi-pd-cam-suba {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_cam_7x1_subcomm0
|
|
&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,suspend-check-port = <0x4 0x2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBA>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_cam_subb: smi-pd-cam-subb {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_cam_7x1_subcomm0
|
|
&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,suspend-check-port = <0x8 0x8>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBB>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_pd_cam_mraw: smi-pd-cam-mraw {
|
|
compatible = "mediatek,smi-pd";
|
|
mediatek,suspend-check-dev = <&smi_disp_cam_7x1_subcomm0
|
|
&smi_disp_cam_7x1_subcomm2 &smi_sram_cam_2x1_subcomm2>;
|
|
mediatek,suspend-check-port = <0x60 0x40 0x1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
suspend-check;
|
|
};
|
|
|
|
smi_larb0: smi-larb0@14021000 {
|
|
compatible = "mediatek,smi_larb0",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x14021000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common &disp_mmsram_smi_subcomm>;
|
|
mediatek,larb-id = <0>;
|
|
init-power-on;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_DISP>;
|
|
clocks = <&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb1: smi-larb1@14022000 {
|
|
compatible = "mediatek,smi_larb1",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x14022000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common &disp_mmsram_smi_subcomm>;
|
|
mediatek,larb-id = <1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_DISP>;
|
|
clocks = <&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi-test {
|
|
compatible = "mediatek,smi-testcase";
|
|
mediatek,larbs = <&smi_larb2>;
|
|
};
|
|
|
|
smi_larb2: smi-larb2@1f002000 {
|
|
compatible = "mediatek,smi_larb2",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1f002000 0 0x1000>;
|
|
mediatek,smi = <&smi_3X1_sub_common>;
|
|
mediatek,larb-id = <2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MDP0>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_SMI0>,
|
|
<&mdpsys_config_clk CLK_MDP_SMI0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb4: smi-larb4@1602e000 {
|
|
compatible = "mediatek,smi_larb4",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1602e000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_common>;
|
|
mediatek,larb-id = <4>;
|
|
clk-on-delay;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VDE0>;
|
|
clocks = <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb7: smi-larb7@17010000 {
|
|
compatible = "mediatek,smi_larb7",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
mediatek,smi = <&smi_3X1_sub_common &smi_sysram_common>;
|
|
mediatek,larb-id = <7>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VEN0>;
|
|
clocks = <&venc_gcon_clk CLK_VEN_CKE0_LARB>,
|
|
<&venc_gcon_clk CLK_VEN_CKE1_VENC>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb9: smi-larb9@15001000 {
|
|
compatible = "mediatek,smi_larb9",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15001000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_5x1_subcomm1>;
|
|
mediatek,larb-id = <9>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
clocks = <&imgsys_main_clk CLK_IMG_LARB9>,
|
|
<&imgsys_main_clk CLK_IMG_LARB9>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb10: smi-larb10@15120000 {
|
|
compatible = "mediatek,smi_larb10",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15120000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_4x1_subcomm0>;
|
|
mediatek,larb-id = <10>;
|
|
mediatek,comm-port-id = <1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&dip_top_dip1_clk CLK_DIP_TOP_DIP1_DIP_TOP>,
|
|
<&dip_top_dip1_clk CLK_DIP_TOP_DIP1_LARB10>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb11: smi-larb11@15230000 {
|
|
compatible = "mediatek,smi_larb11",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15230000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_5x1_subcomm1>;
|
|
mediatek,larb-id = <11>;
|
|
mediatek,comm-port-id = <2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&wpe1_dip1_clk CLK_WPE1_DIP1_WPE>,
|
|
<&wpe1_dip1_clk CLK_WPE1_DIP1_LARB11>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb22: smi-larb22@15530000 {
|
|
compatible = "mediatek,smi_larb22",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15530000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_4x1_subcomm0>;
|
|
mediatek,larb-id = <22>;
|
|
mediatek,comm-port-id = <2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&wpe2_dip1_clk CLK_WPE2_DIP1_WPE>,
|
|
<&wpe2_dip1_clk CLK_WPE2_DIP1_LARB11>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb23: smi-larb23@15630000 {
|
|
compatible = "mediatek,smi_larb23",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15630000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_4x1_subcomm0>;
|
|
mediatek,larb-id = <23>;
|
|
mediatek,comm-port-id = <3>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&wpe3_dip1_clk CLK_WPE3_DIP1_WPE>,
|
|
<&wpe3_dip1_clk CLK_WPE3_DIP1_LARB11>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb12: smi-larb12@15340000 {
|
|
compatible = "mediatek,smi_larb12",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15340000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_5x1_subcomm1>;
|
|
mediatek,larb-id = <12>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
clocks = <&imgsys_main_clk CLK_IMG_LARB12>,
|
|
<&imgsys_main_clk CLK_IMG_LARB12>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb15: smi-larb15@15140000 {
|
|
compatible = "mediatek,smi_larb15",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15140000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_5x1_subcomm1>;
|
|
mediatek,larb-id = <15>;
|
|
mediatek,comm-port-id = <1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_DIP_NR>,
|
|
<&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_LARB15>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb28: smi-larb28@15720000 {
|
|
compatible = "mediatek,smi_larb28",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x15720000 0 0x1000>;
|
|
mediatek,smi = <&smi_img_4x1_subcomm0>;
|
|
mediatek,larb-id = <28>;
|
|
mediatek,comm-port-id = <0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_DIP1>;
|
|
clocks = <&traw_dip1_clk CLK_TRAW_DIP1_TRAW>,
|
|
<&traw_dip1_clk CLK_TRAW_DIP1_LARB28>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb13: smi-larb13@1a001000 {
|
|
compatible = "mediatek,smi_larb13",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a001000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,larb-id = <13>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb14: smi-larb14@1a002000 {
|
|
compatible = "mediatek,smi_larb14",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a002000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0>;
|
|
mediatek,larb-id = <14>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb16: smi-larb16@1a026000 {
|
|
compatible = "mediatek,smi_larb16",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a026000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0>;
|
|
mediatek,larb-id = <16>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBA>;
|
|
clocks = <&camsys_rawa_clk CLK_CAM_RA_LARBX>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb17: smi-larb17@1a027000 {
|
|
compatible = "mediatek,smi_larb17",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a027000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,larb-id = <17>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBA>;
|
|
clocks = <&camsys_yuva_clk CLK_CAM_YA_LARBX>,
|
|
<&camsys_yuva_clk CLK_CAM_YA_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb19: smi-larb19@1b201000 {
|
|
compatible = "mediatek,smi_larb19",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1b201000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0 &smi_sram_cam_2x1_subcomm2>;
|
|
mediatek,larb-id = <19>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&ccu_main_clk CLK_CCU_LARB19>,
|
|
<&ccu_main_clk CLK_CCU_LARB19>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb25: smi-larb25@1a02c000 {
|
|
compatible = "mediatek,smi_larb25",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a02c000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,larb-id = <25>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb26: smi-larb26@1a02d000 {
|
|
compatible = "mediatek,smi_larb26",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a02d000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0>;
|
|
mediatek,larb-id = <26>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MRAW>;
|
|
clocks = <&camsys_mraw_clk CLK_CAM_MR_LARBX>,
|
|
<&camsys_mraw_clk CLK_CAM_MR_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb27: smi-larb27@1a003000 {
|
|
compatible = "mediatek,smi_larb27",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a003000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm2 &smi_sram_cam_2x1_subcomm2>;
|
|
mediatek,larb-id = <27>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb29: smi-larb29@1a004000 {
|
|
compatible = "mediatek,smi_larb29",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0>;
|
|
mediatek,larb-id = <29>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_MAIN>;
|
|
clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>,
|
|
<&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
smi_larb30: smi-larb30@1a028000 {
|
|
compatible = "mediatek,smi_larb30",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a028000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm2>;
|
|
mediatek,larb-id = <30>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBB>;
|
|
clocks = <&camsys_rawb_clk CLK_CAM_RB_LARBX>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
firmware: firmware {
|
|
scmi: scmi {
|
|
compatible = "arm,scmi";
|
|
mboxes = <&tinysys_mbox 0>, <&tinysys_mbox 1>;
|
|
shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
|
|
mbox-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
scmi_tinysys: protocol@80 {
|
|
reg = <0x80>;
|
|
scmi-qos = <1>;
|
|
scmi-met = <3>;
|
|
scmi-apmcupm = <4>;
|
|
scmi-mminfra = <5>;
|
|
scmi-gpupm = <6>;
|
|
scmi-plt = <7>;
|
|
scmi_smi = <8>;
|
|
scmi-cm = <9>;
|
|
scmi-slbc = <10>;
|
|
scmi_ssc = <11>;
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
smi_larb34: smi-larb34@1a029000 {
|
|
compatible = "mediatek,smi_larb34",
|
|
"mediatek,mt6886-smi-larb", "mediatek,smi-larb";
|
|
reg = <0 0x1a029000 0 0x1000>;
|
|
mediatek,smi = <&smi_disp_cam_7x1_subcomm0>;
|
|
mediatek,larb-id = <34>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_SUBB>;
|
|
clocks = <&camsys_yuvb_clk CLK_CAM_YB_LARBX>,
|
|
<&camsys_yuvb_clk CLK_CAM_YB_LARBX>;
|
|
clock-names = "apb", "smi";
|
|
};
|
|
|
|
masp: masp@1c009000 {
|
|
compatible = "mediatek,masp";
|
|
reg = <0 0x1c009000 0 0x1000>;
|
|
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
/* GIC_IRQ ID(sej_axgpt_irq) - 32 = 356 - 32 = 324 */
|
|
};
|
|
|
|
security_ao@1c00b000 {
|
|
compatible = "mediatek,security_ao";
|
|
reg = <0 0x1c00b000 0 0x1000>;
|
|
};
|
|
|
|
systimer: systimer@1c011000 {
|
|
compatible = "mediatek,mt6895-timer",
|
|
"mediatek,mt6765-timer";
|
|
reg = <0 0x1c011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk13m>;
|
|
};
|
|
|
|
sspm: sspm@1c340000 {
|
|
compatible = "mediatek,sspm";
|
|
reg = <0 0x1c300000 0 0x30000>,
|
|
<0 0x1c340000 0 0x10000>,
|
|
<0 0x1c380000 0 0x80>;
|
|
|
|
reg-names = "sspm_base",
|
|
"cfgreg",
|
|
"mbox_share";
|
|
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interrupt-names = "ipc";
|
|
sspm_res_ram_start = <0x0>;
|
|
sspm_res_ram_size = <0x110000>; /* 1M + 64K */
|
|
};
|
|
|
|
/* Microtrust SW IRQ number 816(848 - 32) ~ 817(849 - 32) */
|
|
utos: utos {
|
|
compatible = "microtrust,utos";
|
|
interrupts = <GIC_SPI 817 IRQ_TYPE_EDGE_RISING 0>;
|
|
};
|
|
|
|
utos_tester {
|
|
compatible = "microtrust,tester-v1";
|
|
};
|
|
|
|
teeperf {
|
|
compatible = "mediatek,teeperf";
|
|
cpu-type = <2>; /* 1: CPU_V9_TYPE, 2: CPU_V8_TYPE */
|
|
cpu-map = <2>; /* 1: CPU_4_3_1_MAP, 2: CPU_6_2_MAP */
|
|
};
|
|
|
|
/* Trustonic Mobicore SW IRQ number 144 = 32 + 814 */
|
|
mobicore: mobicore {
|
|
compatible = "trustonic,mobicore";
|
|
interrupts = <GIC_SPI 814 IRQ_TYPE_EDGE_RISING 0>;
|
|
};
|
|
|
|
ssram1@1c350000 {
|
|
compatible = "mmio-sram_1";
|
|
reg = <0x0 0x1c350000 0x0 0x80>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0x1c350000 0x80>;
|
|
|
|
scmi_tx_shmem: tiny_mbox@0 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x0 0x80>;
|
|
};
|
|
};
|
|
|
|
ssram2@1c360000 {
|
|
compatible = "mmio-sram_2";
|
|
reg = <0x0 0x1c360000 0x0 0x80>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0x1c360000 0x80>;
|
|
|
|
scmi_rx_shmem: tiny_mbox@1 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x0 0x80>;
|
|
};
|
|
};
|
|
|
|
tinysys_mbox: tinysys_mbox@1c351000 {
|
|
compatible = "mediatek,tinysys_mbox";
|
|
reg = <0 0x1c351000 0 0x1000>,
|
|
<0 0x1c361000 0 0x1000>;
|
|
/* for profiling */
|
|
shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
|
|
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
/* ATF logger */
|
|
atf_logger: atf_logger {
|
|
compatible = "mediatek,tfa_debug";
|
|
};
|
|
|
|
dcm: dcm@10001000 {
|
|
compatible = "mediatek,mt6886-dcm";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10022000 0 0x1000>,
|
|
<0 0x11035000 0 0x1000>,
|
|
<0 0x112ba000 0 0x1000>,
|
|
<0 0x1c017000 0 0x1000>,
|
|
<0 0xc000000 0 0x1000>,
|
|
<0 0xc040000 0 0x10000>,
|
|
<0 0xc18c000 0 0x10000>,
|
|
<0 0xc1ac000 0 0x10000>,
|
|
<0 0xc1cc000 0 0x10000>;
|
|
reg-names = "infracfg_ao",
|
|
"infra_ao_bcrm",
|
|
"peri_ao_bcrm",
|
|
"ufs0_ao_bcrm",
|
|
"vlp_ao_bcrm",
|
|
"mcusys_par_wrap",
|
|
"mcusys_cpc",
|
|
"mcusys_par_wrap_complex0",
|
|
"mcusys_par_wrap_complex1",
|
|
"mcusys_par_wrap_complex2";
|
|
};
|
|
|
|
/* feature : $enable $dl_mem $ul_mem $ref_mem $size */
|
|
snd_audio_dsp: snd-audio-dsp {
|
|
compatible = "mediatek,snd-audio-dsp";
|
|
mtk-dsp-voip = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk-dsp-primary = <0x5 0xffffffff 0xffffffff \
|
|
0xffffffff 0x30000>;
|
|
mtk-dsp-offload = <0x1d 0xffffffff 0xffffffff \
|
|
0xffffffff 0x400000>;
|
|
mtk-dsp-deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk-dsp-playback = <0x1 0xa 0xffffffff 0x16 0x30000>;
|
|
mtk-dsp-music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>;
|
|
mtk-dsp-capture1 = <0x1 0xffffffff 0xe 0x15 0x20000>;
|
|
mtk-dsp-a2dp = <0x1 0xffffffff 0xffffffff 0xffffffff 0x40000>;
|
|
mtk-dsp-bledl = <0x1 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk-dsp-dataprovider = <0x0 0xffffffff 0x10 0xffffffff 0x30000>;
|
|
mtk-dsp-call-final = <0x5 0xa 0x11 0x16 0x18000>;
|
|
mtk-dsp-fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>;
|
|
mtk-dsp-ktv = <0x1 0x8 0x13 0xffffffff 0x10000>;
|
|
mtk-dsp-capture-raw = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>;
|
|
mtk-dsp-fm = <0x1 0xffffffff 0x11 0xffffffff 0x10000>;
|
|
mtk-dsp-bleul = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>;
|
|
mtk-dsp-ulproc = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>;
|
|
mtk-dsp-a2dp-irq = <0x1>;
|
|
mtk-dsp-ver = <0x1>;
|
|
swdsp-smartpa-process-enable = <0x5>;
|
|
mtk-dsp-mem-afe = <0x1 0x40000>;
|
|
};
|
|
|
|
mt_soc_offload_common {
|
|
compatible = "mediatek,mt_soc_offload_common";
|
|
};
|
|
|
|
speech_usip_mem: speech-usip-mem {
|
|
compatible = "mediatek,speech-usip-mem";
|
|
adsp-phone-call-enh-enable = <0x1>;
|
|
adsp-ble-phone-call-enable = <0x1>;
|
|
};
|
|
|
|
cm_mgr: cm-mgr@c100000 {
|
|
compatible = "mediatek,mt6886-cm_mgr";
|
|
reg = <0 0xc100000 0 0x9000>;
|
|
reg-names = "cm_mgr_base";
|
|
interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
|
|
interconnect-names = "cm-perf-bw";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>,
|
|
<&dvfsrc_freq_opp3>,
|
|
<&dvfsrc_freq_opp4>,
|
|
<&dvfsrc_freq_opp5>,
|
|
<&dvfsrc_freq_opp6>,
|
|
<&dvfsrc_freq_opp7>;
|
|
cm-mgr,cp-down = <100 100 100 100 100 100 100>;
|
|
cm-mgr,cp-up = <100 100 100 100 100 100 100>;
|
|
cm-mgr,dt-down = <0 0 0 0 0 0 0>;
|
|
cm-mgr,dt-up = <0 0 0 0 0 0 0>;
|
|
cm-mgr,vp-down = <100 100 100 100 100 100 100>;
|
|
cm-mgr,vp-up = <100 100 100 100 100 100 100>;
|
|
|
|
use-cpu-to-dram-map = "enable";
|
|
cm-mgr-cpu-opp-to-dram = <1 1 8 8 8 8 8 8
|
|
8 8 8 8 8 8 8 8
|
|
8 8 8 8 8 8 8 8
|
|
8 8 8 8 8 8 8 8>;
|
|
|
|
use-bcpu-weight = "enable";
|
|
cpu-power-bcpu-weight-max = <100>;
|
|
cpu-power-bcpu-weight-min = <100>;
|
|
|
|
/* use-cpu-to-dram-map-new = "enable"; */
|
|
};
|
|
|
|
fpsgo: fpsgo {
|
|
compatible = "mediatek,fpsgo";
|
|
interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
|
|
interconnect-names = "fpsgo-perf-bw";
|
|
required-opps = <&dvfsrc_freq_opp0>;
|
|
cpu_limit = <2>;
|
|
gcc_enable = <1>;
|
|
fbt_cpu_mask = <255 192 63 63 192 63>;
|
|
sbe_resceue_enable = <1>;
|
|
};
|
|
|
|
apusys_rv: apusys-rv@190e1000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,mt6886-apusys_rv";
|
|
status = "okay";
|
|
|
|
reg = <0 0x190e1000 0 0x1000>,
|
|
<0 0x19001000 0 0x1000>,
|
|
<0 0x19002000 0 0x10>,
|
|
<0 0x1903c000 0 0x8000>,
|
|
<0 0x19050000 0 0x10000>,
|
|
<0 0x190f2000 0 0x1000>,
|
|
<0 0x1d000000 0 0x20000>,
|
|
<0 0x0d298000 0 0x10000>;
|
|
|
|
reg-names = "apu_mbox",
|
|
"md32_sysctrl",
|
|
"apu_wdt",
|
|
"apu_sctrl_reviser",
|
|
"md32_cache_dump",
|
|
"apu_ao_ctl",
|
|
"md32_tcm",
|
|
"md32_debug_apb";
|
|
|
|
mediatek,apusys_power = <&apu_top_3>;
|
|
apu-iommu0 = <&apu_iommu0>;
|
|
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
|
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interrupt-names = "apu_wdt",
|
|
"mbox0_irq",
|
|
"mbox1_irq";
|
|
|
|
up-code-buf-sz = <0x100000>;
|
|
up-coredump-buf-sz = <0x180000>;
|
|
regdump-buf-sz = <0x10000>;
|
|
mdla-coredump-buf-sz = <0x0>;
|
|
mvpu-coredump-buf-sz = <0x0>;
|
|
mvpu-sec-coredump-buf-sz = <0x0>;
|
|
|
|
apu-ctrl {
|
|
compatible = "mediatek,apu-ctrl-rpmsg";
|
|
mtk,rpmsg-name = "apu-ctrl-rpmsg";
|
|
};
|
|
|
|
apu-top-rpmsg {
|
|
compatible = "mediatek,aputop-rpmsg";
|
|
mtk,rpmsg-name = "apu_top_3_rpmsg";
|
|
};
|
|
|
|
apu-mdw-rpmsg {
|
|
compatible = "mediatek,apu-mdw-rpmsg";
|
|
mtk,rpmsg-name = "apu-mdw-rpmsg";
|
|
};
|
|
|
|
apu-reviser {
|
|
compatible = "mediatek,apu-reviser-rpmsg";
|
|
mtk,rpmsg-name = "apu-reviser-rpmsg";
|
|
};
|
|
|
|
apu-edma {
|
|
compatible = "mediatek,apu-edma-rpmsg";
|
|
mtk,rpmsg-name = "apu-edma-rpmsg";
|
|
};
|
|
|
|
apu-mnoc {
|
|
compatible = "mediatek,apu-mnoc-rpmsg";
|
|
mtk,rpmsg-name = "apu-mnoc-rpmsg";
|
|
};
|
|
|
|
mdla-tx-rpmsg {
|
|
compatible = "mediatek,mdla-tx-rpmsg";
|
|
mtk,rpmsg-name = "mdla-tx-rpmsg";
|
|
};
|
|
|
|
mdla-rx-rpmsg {
|
|
compatible = "mediatek,mdla-rx-rpmsg";
|
|
mtk,rpmsg-name = "mdla-rx-rpmsg";
|
|
};
|
|
|
|
mvpu-tx-rpmsg {
|
|
compatible = "mediatek,mvpu-tx-rpmsg";
|
|
mtk,rpmsg-name = "mvpu-tx-rpmsg";
|
|
};
|
|
|
|
mvpu-rx-rpmsg {
|
|
compatible = "mediatek,mvpu-rx-rpmsg";
|
|
mtk,rpmsg-name = "mvpu-rx-rpmsg";
|
|
};
|
|
|
|
sapu-lock-rpmsg {
|
|
compatible = "mediatek,apu-lock-rv-rpmsg";
|
|
mtk,rpmsg-name = "apu-lock-rv-rpmsg";
|
|
};
|
|
|
|
};
|
|
|
|
apusys-hw-logger@19024000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,apusys_hw_logger";
|
|
status = "okay";
|
|
|
|
reg = <0 0x19024000 0 0x1000>,
|
|
<0 0x190e1000 0 0x1000>;
|
|
reg-names = "apu_logtop",
|
|
"apu_mbox";
|
|
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
mtk_apu_mem_code: mtk-apu-mem-code {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek, apu_mem_code";
|
|
status = "okay";
|
|
type = <1>;
|
|
mask = /bits/ 64 <0x00000003ffffffff>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
mtk_apu_mem_data: mtk-apu-mem-data {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek, apu_mem_data";
|
|
status = "okay";
|
|
type = <2>;
|
|
mask = /bits/ 64 <0x00000003ffffffff>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_DATA>;
|
|
};
|
|
|
|
mdla {
|
|
compatible = "mediatek, mdla-rv";
|
|
core-num = <1>;
|
|
version = <0x68860305>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
mvpu {
|
|
compatible = "mediatek, mt6886-mvpu";
|
|
core-num = <1>;
|
|
version = <0x0>;
|
|
mask = /bits/ 64 <0x00000003ffffffff>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
apu_top_3: apu_top_3 {
|
|
compatible = "mt6886,apu_top_3";
|
|
reg = <0 0x1c000000 0 0x1000>, // sys_vlp
|
|
<0 0x1c001000 0 0x1000>, // sys_spm
|
|
<0 0x19020000 0 0x1000>, // apu_rcx
|
|
<0 0x190e0000 0 0x4000>, // apu_vcore
|
|
<0 0x190e1000 0 0x2000>, // apu_md32_mbox
|
|
<0 0x190f0000 0 0x1000>, // apu_rpc
|
|
<0 0x190f1000 0 0x1000>, // apu_pcu
|
|
<0 0x190f2000 0 0x1000>, // apu_ao_ctl
|
|
<0 0x190f3000 0 0x1000>, // apu_pll
|
|
<0 0x190f4000 0 0x1000>, // apu_acc
|
|
<0 0x190f6000 0 0x4000>, // apu_are
|
|
<0 0x19100000 0 0x40000>, // apu_acx0
|
|
<0 0x19140000 0 0x1000>; // apu_acx0_rpc_lite
|
|
reg-names =
|
|
"sys_vlp",
|
|
"sys_spm",
|
|
"apu_rcx",
|
|
"apu_vcore",
|
|
"apu_md32_mbox",
|
|
"apu_rpc",
|
|
"apu_pcu",
|
|
"apu_ao_ctl",
|
|
"apu_pll",
|
|
"apu_acc",
|
|
"apu_are",
|
|
"apu_acx0",
|
|
"apu_acx0_rpc_lite";
|
|
};
|
|
|
|
apusys-reviser@1903c000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek, rv-reviser-mt6886";
|
|
reg = <0 0x1903c000 0 0x1000>, /* apu_sctrl_reviser */
|
|
<0 0x02000000 0 0xc00000>, /* VLM */
|
|
<0 0x1d900000 0 0x000000>, /* TCM */
|
|
<0 0x19001000 0 0x1000>; /* apusys int */
|
|
//interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
|
|
default-dram = <0x0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
|
|
boundary = <0x0>;
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
touch: touch {
|
|
compatible = "mediatek,touch";
|
|
};
|
|
|
|
qos:qos@11bb00 {
|
|
compatible = "mediatek,mt6893-qos";
|
|
reg = <0 0x0011bb00 0 0x100>,
|
|
<0 0x0011b9C0 0 0x140>;
|
|
reg-names = "sram", "share_sram";
|
|
mediatek,enable = <1>;
|
|
};
|
|
|
|
fusb304: fusb304 {
|
|
compatible = "mediatek,fusb304";
|
|
status = "okay";
|
|
};
|
|
|
|
typec_mux_switch: typec_mux_switch {
|
|
compatible = "mediatek,typec_mux_switch";
|
|
status = "okay";
|
|
};
|
|
|
|
low_battery_throttling {
|
|
compatible = "mediatek,low_battery_throttling";
|
|
hv-thd-volt = <3300>;
|
|
lv1-thd-volt = <3150>;
|
|
lv2-thd-volt = <3000>;
|
|
};
|
|
|
|
pbm: pbm {
|
|
compatible = "mediatek,pbm";
|
|
};
|
|
|
|
mdpm: mdpm {
|
|
compatible = "mediatek,mt6886-mdpm";
|
|
};
|
|
|
|
cpu_power_throttling: cpu_power_throttling {
|
|
compatible = "mediatek,cpu-power-throttling";
|
|
lbat_cpu_limit = <900000 900000 1300000>;
|
|
oc_cpu_limit = <900000 900000 1300000>;
|
|
};
|
|
|
|
md_power_throttling: md_power_throttling {
|
|
compatible = "mediatek,md-power-throttling";
|
|
lbat_md_reduce_tx = <6>;
|
|
oc_md_reduce_tx = <6>;
|
|
};
|
|
|
|
bp_thl: bp_thl {
|
|
compatible = "mediatek,mtk-bp-thl";
|
|
soc_limit = <15>;
|
|
soc_limit_ext = <20>;
|
|
soc_limit_ext_release = <25>;
|
|
};
|
|
|
|
wifi: wifi@18000000 {
|
|
compatible = "mediatek,wifi";
|
|
reg = <0 0x18000000 0 0x700000>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
emi-addr = <0>;
|
|
emi-size = <0x1400000>;
|
|
emi-alignment = <0x1000000>;
|
|
emi-max-addr = <0xC0000000>;
|
|
};
|
|
|
|
opp_table_disp: opp-table-disp {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <208000000>;
|
|
opp-microvolt = <575000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <458000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <624000000>;
|
|
opp-microvolt = <725000>;
|
|
};
|
|
opp-4 {
|
|
opp-hz = /bits/ 64 <660000000>;
|
|
opp-microvolt = <750000>;
|
|
};
|
|
};
|
|
|
|
disp_sec {
|
|
compatible = "mediatek,disp_sec";
|
|
sw_sync_token_tzmp_disp_wait = <CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT>;
|
|
sw_sync_token_tzmp_disp_set = <CMDQ_SYNC_TOKEN_TZMP_DISP_SET>;
|
|
mboxes = <&gce_sec 8 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_4>;
|
|
};
|
|
|
|
opp_table_mdp: opp-table-mdp {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <229000000>;
|
|
opp-microvolt = <575000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <273000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <458000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <624000000>;
|
|
opp-microvolt = <725000>;
|
|
};
|
|
opp-4 {
|
|
opp-hz = /bits/ 64 <660000000>;
|
|
opp-microvolt = <750000>;
|
|
};
|
|
};
|
|
|
|
opp_table_venc: opp-table-venc {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
opp-microvolt = <575000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <312000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <458000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <624000000>;
|
|
opp-microvolt = <725000>;
|
|
};
|
|
opp-4 {
|
|
opp-hz = /bits/ 64 <624000001>;
|
|
opp-microvolt = <750000>;
|
|
};
|
|
};
|
|
|
|
opp_table_vdec: opp-table-vdec {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <218000000>;
|
|
opp-microvolt = <575000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <312000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <416000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <546000000>;
|
|
opp-microvolt = <725000>;
|
|
};
|
|
opp-4 {
|
|
opp-hz = /bits/ 64 <546000001>;
|
|
opp-microvolt = <750000>;
|
|
};
|
|
};
|
|
|
|
opp_table_cam: opp-table-cam {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <273000000>;
|
|
opp-microvolt = <550000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <416000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <546000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <624000000>;
|
|
opp-microvolt = <700000>;
|
|
};
|
|
};
|
|
|
|
opp_table_img: opp-table-img {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <264000000>;
|
|
opp-microvolt = <550000>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <416000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <546000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <660000000>;
|
|
opp-microvolt = <700000>;
|
|
};
|
|
};
|
|
|
|
opp_table_vote: opp-table-vote {
|
|
compatible = "operating-points-v2";
|
|
opp-0 {
|
|
opp-hz = /bits/ 64 <1>;
|
|
opp-microvolt = <1>;
|
|
};
|
|
opp-1 {
|
|
opp-hz = /bits/ 64 <2>;
|
|
opp-microvolt = <2>;
|
|
};
|
|
opp-2 {
|
|
opp-hz = /bits/ 64 <3>;
|
|
opp-microvolt = <3>;
|
|
};
|
|
opp-3 {
|
|
opp-hz = /bits/ 64 <4>;
|
|
opp-microvolt = <4>;
|
|
};
|
|
opp-4 {
|
|
opp-hz = /bits/ 64 <5>;
|
|
opp-microvolt = <5>;
|
|
};
|
|
};
|
|
|
|
mmdvfs_clk: mmdvfs-clk {
|
|
compatible = "mediatek,mtk-mmdvfs-v3";
|
|
mmdvfs-free-run;
|
|
#mmdvfs,clock-cells = <6>;
|
|
mediatek,mmdvfs-clocks =
|
|
<&mmdvfs_clk CLK_MMDVFS_DISP PWR_MMDVFS_VCORE 1
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_disp>,
|
|
<&mmdvfs_clk CLK_MMDVFS_MDP PWR_MMDVFS_VCORE 2
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_mdp>,
|
|
<&mmdvfs_clk CLK_MMDVFS_MML PWR_MMDVFS_VCORE 3
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_mdp>,
|
|
<&mmdvfs_clk CLK_MMDVFS_SMI_COMMON0 PWR_MMDVFS_VCORE 4
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_mdp>,
|
|
<&mmdvfs_clk CLK_MMDVFS_SMI_COMMON1 PWR_MMDVFS_VCORE 4
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_mdp>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VENC PWR_MMDVFS_VCORE 5
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_venc>,
|
|
<&mmdvfs_clk CLK_MMDVFS_JPEGENC PWR_MMDVFS_VCORE 6
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_venc>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VDEC PWR_MMDVFS_VCORE 7
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_vdec>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VFMT PWR_MMDVFS_VCORE 8
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_vdec>,
|
|
<&mmdvfs_clk CLK_MMDVFS_JPEGDEC PWR_MMDVFS_VMM 6
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_venc>,
|
|
<&mmdvfs_clk CLK_MMDVFS_IMG PWR_MMDVFS_VMM 9
|
|
IPI_MMDVFS_CCU SPEC_MMDVFS_DVFSRC &opp_table_img>,
|
|
<&mmdvfs_clk CLK_MMDVFS_IPE PWR_MMDVFS_VMM 9
|
|
IPI_MMDVFS_CCU SPEC_MMDVFS_DVFSRC &opp_table_img>,
|
|
<&mmdvfs_clk CLK_MMDVFS_CAM PWR_MMDVFS_VMM 10
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_cam>,
|
|
<&mmdvfs_clk CLK_MMDVFS_CCU PWR_MMDVFS_VMM 10
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_cam>,
|
|
<&mmdvfs_clk CLK_MMDVFS_AOV PWR_MMDVFS_VMM 11
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_cam>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VCORE PWR_MMDVFS_VCORE 12
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_vote>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VMM PWR_MMDVFS_VMM 13
|
|
IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_vote>;
|
|
mediatek,mmdvfs-clock-names =
|
|
"disp", "mdp", "mml", "smi_common0", "smi_common1",
|
|
"venc", "jpegenc", "vdec", "vfmt", "jpegdec",
|
|
"img", "ipe", "cam", "ccu", "aov", "vcore", "vmm";
|
|
mediatek,ccu-rproc = <&ccu_rproc>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mmdvfs_clk CLK_MMDVFS_VCORE>, <&mmdvfs_clk CLK_MMDVFS_VMM>;
|
|
clock-names = "pwr_vcore", "pwr_vmm";
|
|
};
|
|
|
|
mmdvfs-v3-start {
|
|
compatible = "mediatek,mmdvfs-v3-start";
|
|
};
|
|
|
|
mmdvfs-ccu {
|
|
compatible = "mediatek,mmdvfs-ccu";
|
|
};
|
|
|
|
mmdvfs {
|
|
compatible = "mediatek,mmdvfs";
|
|
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
operating-points-v2 = <&opp_table_disp>;
|
|
mediatek,support-mux = "disp0", "mdp0", "mminfra", "venc";
|
|
mediatek,mux-disp0 =
|
|
"UNIVPLL_D6_D2", "UNIVPLL_D5_D2", "MMPLL_D6", "UNIVPLL_D4", "IMGPLL_D2";
|
|
mediatek,mux-mdp0 =
|
|
"MMPLL_D6_D2", "MAINPLL_D4_D2", "MMPLL_D6", "UNIVPLL_D4", "IMGPLL_D2";
|
|
mediatek,mux-mminfra =
|
|
"MMPLL_D6_D2", "MAINPLL_D4_D2", "MMPLL_D6", "UNIVPLL_D4", "IMGPLL_D2";
|
|
mediatek,mux-venc =
|
|
"UNIVPLL_D5_D2", "UNIVPLL_D4_D2", "MMPLL_D6", "UNIVPLL_D4", "UNIVPLL_D4";
|
|
clocks = <&topckgen_clk CLK_TOP_DISP0_SEL>, /* 0 */
|
|
<&topckgen_clk CLK_TOP_MDP0_SEL>, /* 1 */
|
|
<&topckgen_clk CLK_TOP_MMINFRA_SEL>, /* 2 */
|
|
<&topckgen_clk CLK_TOP_VENC_SEL>, /* 3 */
|
|
<&topckgen_clk CLK_TOP_IMGPLL_D2>, /* 4 */
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D4>, /* 5 */
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D4_D2>, /* 6 */
|
|
<&topckgen_clk CLK_TOP_MMPLL_D6>, /* 7 */
|
|
<&topckgen_clk CLK_TOP_MMPLL_D6_D2>, /* 8*/
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 9*/
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D4_D2>, /* 10 */
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D5_D2>, /* 11 */
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>; /* 12 */
|
|
clock-names = "disp0", /* 0 */
|
|
"mdp0", /* 1 */
|
|
"mminfra", /* 2 */
|
|
"venc", /* 3 */
|
|
"IMGPLL_D2", /* 4 */
|
|
"MAINPLL_D4", /* 5 */
|
|
"MAINPLL_D4_D2", /* 6 */
|
|
"MMPLL_D6", /* 7 */
|
|
"MMPLL_D6_D2", /* 8 */
|
|
"UNIVPLL_D4", /* 9 */
|
|
"UNIVPLL_D4_D2", /* 10 */
|
|
"UNIVPLL_D5_D2", /* 11 */
|
|
"UNIVPLL_D6_D2"; /* 12 */
|
|
};
|
|
|
|
mmdvfs-debug {
|
|
compatible = "mediatek,mmdvfs-debug";
|
|
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
disp-dev = <&dispsys_config>;
|
|
force-step0 = <0>; /* 0:opp0, 1:opp1, ... */
|
|
release-step0 = <1>; /* 0:disable, 1:enable */
|
|
use-v3-pwr = <2>; /* OR operation of (1 << PWR_MMDVFS_XXX) */
|
|
clocks = <&mmdvfs_clk CLK_MMDVFS_VCORE>, <&mmdvfs_clk CLK_MMDVFS_VMM>;
|
|
clock-names = "vcore", "vmm";
|
|
vcore-supply = <&mt6363_vbuck5>;
|
|
vmm-pmic-supply = <&mt6319_6_vbuck3>;
|
|
fmeter-id = /bits/ 8 <5 6 7 52 53 64 65 66>;
|
|
fmeter-type = /bits/ 8 <2 2 2 2 2 2 2 2>;
|
|
};
|
|
|
|
ktf-mmdvfs-test {
|
|
compatible = "mediatek,ktf-mmdvfs-test";
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_E1_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_MC_EXT)
|
|
&mmqos SLAVE_COMMON(1)>;
|
|
interconnect-names = "mmdvfs_interconnect1",
|
|
"mmdvfs_interconnect2",
|
|
"mmdvfs_interconnect3";
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
drm: drm@1000d000 {
|
|
compatible = "mediatek,dbgtop-drm";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
ver = <2>;
|
|
dis_ddr_rsv_mode = <0>;
|
|
};
|
|
|
|
lkg: lkg@114400 {
|
|
compatible = "mediatek,mtk-lkg";
|
|
reg = <0 0x00114400 0 0xc00>;
|
|
};
|
|
|
|
performance: performance-controller@11bc00 {
|
|
compatible = "mediatek,cpufreq-hw";
|
|
reg = <0 0x0011bc10 0 0x120>,
|
|
<0 0x0011bd30 0 0x120>;
|
|
reg-names = "performance-domain0",
|
|
"performance-domain1";
|
|
#performance-domain-cells = <1>;
|
|
};
|
|
|
|
eas_info: eas_info {
|
|
compatible = "mediatek,eas-info";
|
|
csram-base = <0x0011bc00>;
|
|
/* L, B, CCI */
|
|
offs-thermal-limit = <0x1208 0x120c 0x1210>;
|
|
offs-cap = <0xfa0>;
|
|
};
|
|
|
|
cpu_mcucfg: mcusys_ao_cfg@c530000 {
|
|
reg = <0 0x0c000000 0 0x10000>; /* 64KB */
|
|
};
|
|
|
|
cpu_pll: mcusys_pll1u_top@1000c000 {
|
|
reg = <0 0x0c030000 0 0x1000>; /* 4KB */
|
|
};
|
|
|
|
dramc: dramc@10230000 {
|
|
compatible = "mediatek,mt6886-dramc",
|
|
"mediatek,common-dramc";
|
|
reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
|
|
<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
|
|
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
|
|
<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
|
|
<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
|
|
<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
|
|
<0 0x10236000 0 0x2000>, /* DDRPHY NAO CHA */
|
|
<0 0x10246000 0 0x2000>, /* DDRPHY NAO CHB */
|
|
<0 0x10006000 0 0x1000>; /* SLEEP BASE */
|
|
mr4_version = <0>;
|
|
mr4_rg = <0x0090 0x0000ffff 0>;
|
|
fmeter_version = <2>;
|
|
crystal_freq = <26>;
|
|
pll_id = <0x0cb4 0x00000100 8>;
|
|
shu_lv = <0x0cb4 0x00030000 16>;
|
|
shu_of = <0x700>;
|
|
sdmpcw = <0x0908 0x0007fff8 3>,
|
|
<0x0928 0x0007fff8 3>;
|
|
prediv = <0x090c 0x0000fffc 14>,
|
|
<0x092c 0x0000fffc 14>;
|
|
posdiv = <0x090c 0x00003800 11>,
|
|
<0x092c 0x00003800 11>;
|
|
ckdiv4 = <0x13ec 0x00000004 2>,
|
|
<0x13ec 0x00000004 2>;
|
|
pll_md = <0x0944 0x00000100 8>,
|
|
<0x0944 0x00000100 8>;
|
|
cldiv2 = <0x0f34 0x00000002 1>,
|
|
<0x0f34 0x00000002 1>;
|
|
fbksel = <0x0910 0x00000020 5>,
|
|
<0x0910 0x00000020 5>;
|
|
dqsopen = <0x0D94 0x02000000 25>,
|
|
<0x0D94 0x02000000 25>;
|
|
dqopen = <0x0D94 0x0001fffe 21>,
|
|
<0x0D94 0x0001fffe 21>;
|
|
ckdiv4_ca = <0x136c 0x00000004 2>,
|
|
<0x136c 0x00000004 2>;
|
|
};
|
|
|
|
fhctl: fhctl@1000ce00 {
|
|
compatible = "mediatek,mt6886-fhctl";
|
|
reg = <0 0x1000ce00 0 0x200>, //AP FHCTL base
|
|
<0 0x1000c000 0 0xe00>, //APMIX base
|
|
|
|
<0 0x13fa0100 0 0x030>, //GPU0 EN
|
|
<0 0x13fa0000 0 0x100>, //GPU APMIX
|
|
<0 0x13fa0900 0 0x030>,
|
|
<0 0x13fa0800 0 0x100>,
|
|
<0 0x13fa0d00 0 0x030>,
|
|
<0 0x13fa0c00 0 0x100>,
|
|
|
|
<0 0x0c030100 0 0x030>, //MCU0 EN
|
|
<0 0x0c030000 0 0x100>, //MCU APMIX
|
|
<0 0x0c030500 0 0x030>,
|
|
<0 0x0c030400 0 0x100>,
|
|
<0 0x0c030900 0 0x030>,
|
|
<0 0x0c030800 0 0x100>,
|
|
<0 0x0c034100 0 0x030>,
|
|
<0 0x0c034000 0 0x100>;
|
|
|
|
map0 {
|
|
domain = "top";
|
|
method = "fhctl-ap";
|
|
mpll {
|
|
fh-id = <6>;
|
|
pll-id = <999>;
|
|
perms = <0x18>;
|
|
};
|
|
mmpll {
|
|
fh-id = <7>;
|
|
pll-id = <999>;
|
|
};
|
|
mainpll {
|
|
fh-id = <8>;
|
|
pll-id = <999>;
|
|
};
|
|
msdcpll {
|
|
fh-id = <9>;
|
|
pll-id = <999>;
|
|
};
|
|
adsppll {
|
|
fh-id = <10>;
|
|
pll-id = <999>;
|
|
};
|
|
imgpll {
|
|
fh-id = <11>;
|
|
pll-id = <999>;
|
|
};
|
|
ufspll {
|
|
fh-id = <12>;
|
|
pll-id = <999>;
|
|
};
|
|
};
|
|
|
|
map5 {
|
|
domain = "gpu0";
|
|
method = "fhctl-gpueb";
|
|
mfgpll {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
};
|
|
};
|
|
|
|
map7 {
|
|
domain = "gpu2";
|
|
method = "fhctl-gpueb";
|
|
mfgpll2 {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
};
|
|
};
|
|
|
|
map8 {
|
|
domain = "gpu3";
|
|
method = "fhctl-gpueb";
|
|
mfgscpll {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
};
|
|
};
|
|
|
|
map9 {
|
|
domain = "mcu0";
|
|
method = "fhctl-mcupm";
|
|
ccipll {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
perms = <0x18>;
|
|
};
|
|
};
|
|
|
|
map10 {
|
|
domain = "mcu1";
|
|
method = "fhctl-mcupm";
|
|
armpll-ll {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
perms = <0x18>;
|
|
};
|
|
};
|
|
|
|
map11 {
|
|
domain = "mcu2";
|
|
method = "fhctl-mcupm";
|
|
armpll-bl {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
perms = <0x18>;
|
|
};
|
|
};
|
|
|
|
map12 {
|
|
domain = "mcu3";
|
|
method = "fhctl-mcupm";
|
|
ptppll {
|
|
fh-id = <0>;
|
|
pll-id = <999>;
|
|
perms = <0x18>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
apdma: dma-controller@11300A80 {
|
|
compatible = "mediatek,mt6779-uart-dma";
|
|
reg = <0 0x11300A80 0 0x80>,
|
|
<0 0x11300B00 0 0x80>,
|
|
<0 0x11300B80 0 0x80>,
|
|
<0 0x11300C00 0 0x80>;
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "apdma";
|
|
dma-requests = <4>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@11001000 {
|
|
compatible = "mediatek,mt6577-uart";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 0 &apdma 1>;
|
|
dma-names = "tx", "rx";
|
|
uart_line = <0>;
|
|
};
|
|
|
|
uart1: serial@11002000 {
|
|
compatible = "mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART1>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 2 &apdma 3>;
|
|
dma-names = "tx", "rx";
|
|
uart_line = <1>;
|
|
};
|
|
|
|
pwm@11008000 {
|
|
compatible = "mediatek,pwm";
|
|
reg = <0 0x11008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pericfg_ao_clk CLK_PERAO_PWM_FB1>,
|
|
<&pericfg_ao_clk CLK_PERAO_PWM_FB2>,
|
|
<&pericfg_ao_clk CLK_PERAO_PWM_FB3>,
|
|
<&pericfg_ao_clk CLK_PERAO_PWM_FB4>,
|
|
<&pericfg_ao_clk CLK_PERAO_PWM_H>,
|
|
<&pericfg_ao_clk CLK_PERAO_PWM_B>;
|
|
|
|
clock-names = "PWM1-main",
|
|
"PWM2-main",
|
|
"PWM3-main",
|
|
"PWM4-main",
|
|
"PWM-HCLK-main",
|
|
"PWM-main";
|
|
|
|
/* 1. pwm periclk control reg offset */
|
|
mediatek,pwm-topclk-ctl-reg = <0x24>;
|
|
/* 2. pwm bclk sw ctrl offset */
|
|
mediatek,pwm-bclk-sw-ctrl-offset = <12>;
|
|
/* 3. pwm_x bclk sw ctrl offset */
|
|
mediatek,pwm1-bclk-sw-ctrl-offset = <20>;
|
|
mediatek,pwm2-bclk-sw-ctrl-offset = <18>;
|
|
mediatek,pwm3-bclk-sw-ctrl-offset = <16>;
|
|
mediatek,pwm4-bclk-sw-ctrl-offset = <14>;
|
|
/* 4. pwm version */
|
|
mediatek,pwm-version = <0x2>;
|
|
|
|
pwmsrcclk = <&pericfg_ao_clk>;
|
|
};
|
|
|
|
irtx_pwm:irtx-pwm {
|
|
compatible = "mediatek,irtx-pwm";
|
|
pwm-ch = <2>; /* GPIO147 */
|
|
pwm-data-invert = <0>;
|
|
pwm-supply = "mt6368_vio28";
|
|
};
|
|
|
|
gpio: gpio@10005000 {
|
|
compatible = "mediatek,gpio";
|
|
reg = <0 0x10005000 0 0x1000>;
|
|
};
|
|
|
|
spi0: spi0@11010000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11010000 0 0x100>;
|
|
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI0_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi1: spi1@11011000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11011000 0 0x100>;
|
|
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI1_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi2: spi2@11012000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11012000 0 0x100>;
|
|
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI2_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi3: spi3@11013000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11013000 0 0x100>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI3_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi4: spi4@11014000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11014000 0 0x100>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI4_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi5: spi5@11015000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11015000 0 0x100>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI5_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi6: spi6@11016000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11016000 0 0x100>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI6_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi7: spi7@11017000 {
|
|
compatible = "mediatek,mt6985-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11017000 0 0x100>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_SPI7_B>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
goodix_fp: fingerprint {
|
|
compatible = "mediatek,goodix-fp";
|
|
};
|
|
|
|
pio: pinctrl {
|
|
compatible = "mediatek,mt6886-pinctrl";
|
|
reg = <0 0x10005000 0 0x1000>,
|
|
<0 0x11c20000 0 0x1000>,
|
|
<0 0x11d10000 0 0x1000>,
|
|
<0 0x11d30000 0 0x1000>,
|
|
<0 0x11d40000 0 0x1000>,
|
|
<0 0x11e10000 0 0x1000>,
|
|
<0 0x11ea0000 0 0x1000>,
|
|
<0 0x11eb0000 0 0x1000>;
|
|
reg-names = "gpio",
|
|
"iocfg_br",
|
|
"iocfg_lb",
|
|
"iocfg_bm",
|
|
"iocfg_bl",
|
|
"iocfg_lc",
|
|
"iocfg_rc",
|
|
"iocfg_rt";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pio 0 0 203>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
mediatek,eint = <&eint>;
|
|
};
|
|
|
|
devapc@10207000 {
|
|
compatible = "mediatek,mt6886-devapc";
|
|
reg = <0 0x10207000 0 0x1000>, /* infra pd */
|
|
<0 0x10274000 0 0x1000>, /* infra1 pd */
|
|
<0 0x11020000 0 0x1000>, /* peri pd */
|
|
<0 0x1c01c000 0 0x1000>, /* vlp pd */
|
|
<0 0x1e019000 0 0x1000>, /* adsp pd */
|
|
<0 0x1e826000 0 0x1000>, /* mminfra pd */
|
|
<0 0x1eca4000 0 0x1000>, /* mmup pd */
|
|
<0 0x10030000 0 0x1000>, /* infra ao */
|
|
<0 0x1103c000 0 0x1000>, /* fake peri ao */
|
|
<0 0x1c018000 0 0x1000>, /* vlp ao */
|
|
<0 0x1e01c000 0 0x1000>, /* adsp ao */
|
|
<0 0x1e820000 0 0x1000>, /* mminfra ao */
|
|
<0 0x1eca0000 0 0x1000>, /* mmup ao */
|
|
<0 0x1eca0000 0 0x1000>, /* fake gpu ao */
|
|
<0 0x1020e000 0 0x1000>, /* infracfg */
|
|
<0 0x10033000 0 0x1000>, /* swp */
|
|
<0 0x0010c000 0 0x1000>; /* sramrom */
|
|
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH 0>, /* infra irq */
|
|
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH 0>, /* fake peri irq */
|
|
<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH 0>, /* vlp irq */
|
|
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH 0>, /* adsp irq */
|
|
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH 0>, /* mminfra irq */
|
|
<GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH 0>, /* mmup irq */
|
|
<GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH 0>; /* fake gpu irq */
|
|
};
|
|
|
|
/*
|
|
* 217~242 append for instance middle reserved pin,
|
|
* Or eint driver can't control each instance pin
|
|
*/
|
|
eint: apirq@11ce0000 {
|
|
compatible = "mediatek,mt6983-eint";
|
|
reg = <0 0x11ce0000 0 0x1000>,
|
|
<0 0x11de0000 0 0x1000>,
|
|
<0 0x11e50000 0 0x1000>,
|
|
<0 0x11e90000 0 0x1000>,
|
|
<0 0x1c01e000 0 0x1000>;
|
|
reg-name = "eint-s", "eint-w", "eint-n", "eint-e", "eint-c";
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,instance-num = <5>;
|
|
mediatek,total-pin-number = <243>;
|
|
mediatek,pins = <0 2 8 0>,<1 2 9 0>,<2 2 10 0>,<3 2 11 0>,
|
|
<4 2 0 1>,<5 2 1 1>,<6 2 2 1>,<7 2 3 1>,
|
|
<8 2 12 0>,<9 2 13 0>,<10 2 14 0>,<11 2 15 0>,
|
|
<12 2 16 0>,<13 1 0 1>,<14 1 1 1>,<15 1 2 1>,
|
|
<16 3 0 1>,<17 3 1 1>,<18 3 24 0>,<19 3 25 0>,
|
|
<20 3 26 0>,<21 3 27 0>,<22 3 2 1>,<23 3 3 1>,
|
|
<47 1 16 0>,<48 1 17 0>,<53 1 18 0>,<64 1 19 0>,
|
|
<65 1 20 0>,<88 1 3 1>,<89 1 4 1>,<90 1 5 1>,
|
|
<91 1 6 1>,<92 1 7 1>,<93 1 8 1>,<94 1 9 1>,
|
|
<95 1 10 1>,<96 1 11 1>,<97 1 21 0>,<98 1 22 0>,
|
|
<99 1 23 0>,<100 1 24 0>,<101 1 25 0>,<102 1 26 0>,
|
|
<103 1 27 0>,<104 1 28 0>,<105 1 29 0>,<106 1 30 0>,
|
|
<107 1 31 0>,<108 1 32 0>,<109 1 33 0>,<110 1 34 0>,
|
|
<111 1 35 0>,<112 1 36 0>,<113 1 37 0>,<114 1 38 0>,
|
|
<115 1 39 0>,<116 1 40 0>,<117 1 41 0>,<118 1 42 0>,
|
|
<119 1 43 0>,<120 1 44 0>,<133 0 4 1>,<134 0 5 1>,
|
|
<135 0 12 0>,<136 0 13 0>,<137 0 14 0>,<138 0 15 0>,
|
|
<139 0 16 0>,<140 0 17 0>,<141 0 18 0>,<142 0 19 0>,
|
|
<143 0 20 0>,<144 0 21 0>,<145 0 22 0>,<146 0 23 0>,
|
|
<147 0 24 0>,<148 0 25 0>,<149 0 26 0>,<156 0 27 0>,
|
|
<157 0 28 0>,<158 0 0 1>,<159 0 1 1>,<160 0 2 1>,
|
|
<161 0 3 1>,<162 3 4 1>,<163 3 5 1>,<164 3 6 1>,
|
|
<165 3 7 1>,<166 3 8 1>,<167 3 9 1>,<168 3 28 0>,
|
|
<169 3 29 0>,<170 3 30 0>,<171 3 31 0>,<172 3 32 0>,
|
|
<173 3 33 0>,<180 3 34 0>,<181 3 35 0>,<182 3 10 1>,
|
|
<183 3 11 1>,<184 3 12 1>,<185 3 13 1>,<186 3 14 1>,
|
|
<187 3 15 1>,<188 3 36 0>,<189 3 37 0>,<203 4 0 0>,
|
|
<204 4 1 0>,<205 4 2 0>,<206 4 3 0>,<207 4 4 0>,
|
|
<208 4 5 0>,<209 4 6 0>,<210 4 7 0>,<211 4 12 0>,
|
|
<212 4 13 0>,<213 4 14 0>,<214 4 15 0>,<215 4 16 0>,
|
|
<216 4 17 0>,<217 0 6 0>,<218 0 7 0>,<219 0 8 0>,
|
|
<220 0 9 0>,<221 0 10 0>,<222 0 11 0>,<223 1 12 0>,
|
|
<224 1 13 0>,<225 1 14 0>,<226 1 15 0>,<227 2 4 0>,
|
|
<228 2 5 0>,<229 2 6 0>,<230 2 7 0>,<231 3 16 0>,
|
|
<232 3 17 0>,<233 3 18 0>,<234 3 19 0>,<235 3 20 0>,
|
|
<236 3 21 0>,<237 3 22 0>,<238 3 23 0>,<239 4 8 0>,
|
|
<240 4 9 0>,<241 4 10 0>,<242 4 11 0>;
|
|
};
|
|
|
|
dfd_mcu: dfd-mcu {
|
|
compatible = "mediatek,dfd_mcu";
|
|
enabled = <1>;
|
|
hw-version = <35>;
|
|
sw-version = <1>;
|
|
dfd-timeout = <0x7d0>; /* 1 sec */
|
|
buf-length = <0x280000>;
|
|
buf-addr-align = <0x400000>;
|
|
buf-addr-max = <0xffffffff>;
|
|
nr-max-core = <8>;
|
|
nr-big-core = <2>;
|
|
nr-rs-entry-little = <8>;
|
|
nr-rs-entry-big = <16>;
|
|
nr-header-row = <4>;
|
|
chip-id-offset = <0x38>;
|
|
check-pattern-offset = <0x20>;
|
|
dfd-disable-efuse = <25 11>;
|
|
dfd_cache: dfd-cache {
|
|
enabled = <1>;
|
|
dfd-timeout = <0x32c8>; /* 6.5 sec */
|
|
buf-length = <0x280000>;
|
|
tap-en = <0x200000>;
|
|
};
|
|
};
|
|
|
|
dfd_soc: dfd-soc {
|
|
compatible = "mediatek,dfd_soc";
|
|
enabled = <1>;
|
|
dfd-timeout = <0x1000>;
|
|
buf-length = <0x200000>;
|
|
buf-addr-align = <0x400000>;
|
|
buf-addr-max = <0xffffffff>;
|
|
};
|
|
|
|
adspsys: adspsys@1e000000 {
|
|
compatible = "mediatek,mt6886-adspsys";
|
|
status = "okay";
|
|
reg = <0 0x1e000000 0 0x6000>, /* CFG */
|
|
<0 0x1e00b000 0 0x5000>, /* CFG 2 */
|
|
<0 0x1e006000 0 0x100>, /* MBOX0 base */
|
|
<0 0x1e006100 0 0x4>, /* MBOX0 set */
|
|
<0 0x1e00610c 0 0x4>, /* MBOX0 clr */
|
|
<0 0x1e007000 0 0x100>, /* MBOX1 base */
|
|
<0 0x1e007100 0 0x4>, /* MBOX1 set */
|
|
<0 0x1e00710c 0 0x4>, /* MBOX1 clr */
|
|
<0 0x1e008000 0 0x100>, /* MBOX2 base */
|
|
<0 0x1e008100 0 0x4>, /* MBOX2 set */
|
|
<0 0x1e00810c 0 0x4>, /* MBOX2 clr */
|
|
<0 0x1e009000 0 0x100>, /* MBOX3 base */
|
|
<0 0x1e009100 0 0x4>, /* MBOX3 set */
|
|
<0 0x1e00910c 0 0x4>; /* MBOX3 clr */
|
|
reg-names = "cfg", "cfg2",
|
|
"mbox0_base", "mbox0_set", "mbox0_clr",
|
|
"mbox1_base", "mbox1_set", "mbox1_clr",
|
|
"mbox2_base", "mbox2_set", "mbox2_clr",
|
|
"mbox3_base", "mbox3_set", "mbox3_clr";
|
|
|
|
interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX0 */
|
|
<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX1 */
|
|
<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX2 */
|
|
<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX3 */
|
|
<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH 0>; /* DEBUG_CTRL */
|
|
interrupt-names = "mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"debug_ctrl";
|
|
#mbox-cells = <1>;
|
|
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ADSP_TOP_DORMANT>;
|
|
clocks = <&topckgen_clk CLK_TOP_ADSP_SEL>,
|
|
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
|
|
<&topckgen_clk CLK_TOP_ADSPPLL>;
|
|
clock-names = "clk_top_adsp_sel",
|
|
"clk_top_clk26m",
|
|
"clk_top_adsppll";
|
|
|
|
core-num = <1>; /* core number */
|
|
adsp-rsv-ipidma-a = <0x200000>;
|
|
adsp-rsv-ipidma-b = <0x0>;
|
|
adsp-rsv-logger-a = <0x80000>;
|
|
adsp-rsv-logger-b = <0x0>;
|
|
adsp-rsv-c2c = <0x0>;
|
|
adsp-rsv-dbg-dump-a = <0x80000>;
|
|
adsp-rsv-dbg-dump-b = <0x0>;
|
|
adsp-rsv-core-dump-a = <0x400>;
|
|
adsp-rsv-core-dump-b = <0x0>;
|
|
adsp-rsv-audio = <0x5c0000>;
|
|
};
|
|
|
|
adsp_core0: adsp-core0@1e020000 {
|
|
compatible = "mediatek,mt6886-adsp_core_0";
|
|
status = "okay";
|
|
reg = <0 0x1e050000 0 0x9000>, /* ITCM */
|
|
<0 0x1e020000 0 0x8000>; /* DTCM */
|
|
system = <0 0x50000000 0 0x900000>;
|
|
interrupts = <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mboxes = <&adspsys 0>, /*channel 0*/
|
|
<&adspsys 1>; /*channel 1*/
|
|
feature-control-bits = <0xffffffff>;
|
|
};
|
|
|
|
gpio_usage_mapping:gpio {
|
|
compatible = "mediatek,gpio_usage_mapping";
|
|
};
|
|
md1_sim1_hot_plug_eint:MD1-SIM1-HOT-PLUG-EINT {
|
|
};
|
|
md1_sim2_hot_plug_eint:MD1-SIM2-HOT-PLUG-EINT {
|
|
};
|
|
mrdump_ext_rst:mrdump_ext_rst {
|
|
compatible = "mediatek, mrdump_ext_rst-eint";
|
|
mode = "IRQ";
|
|
status = "okay";
|
|
};
|
|
subpmic_pmu_eint:subpmic_pmu_eint {
|
|
};
|
|
|
|
i2c0: i2c@11e00000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11e00000 0 0x1000>,
|
|
<0 0x11300200 0 0x80>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_w_clk CLK_IMPW_I2C0>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <43>;
|
|
sda-gpio-id = <44>;
|
|
};
|
|
|
|
i2c1: i2c@11e01000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11e01000 0 0x1000>,
|
|
<0 0x11300280 0 0x80>;
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_w_clk CLK_IMPW_I2C1>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <45>;
|
|
sda-gpio-id = <46>;
|
|
};
|
|
|
|
i2c2: i2c@11c70000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11c70000 0 0x1000>,
|
|
<0 0x11300300 0 0x100>;
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_es_clk CLK_IMPES_I2C2>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <150>;
|
|
sda-gpio-id = <151>;
|
|
};
|
|
|
|
i2c3: i2c@11e80000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11e80000 0 0x1000>,
|
|
<0 0x11300400 0 0x80>;
|
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_I2C3>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <174>;
|
|
sda-gpio-id = <175>;
|
|
};
|
|
|
|
i2c4: i2c@11c71000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11c71000 0 0x1000>,
|
|
<0 0x11300480 0 0x100>;
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_es_clk CLK_IMPES_I2C4>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <152>;
|
|
sda-gpio-id = <153>;
|
|
};
|
|
|
|
i2c5: i2c@11280000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11280000 0 0x1000>,
|
|
<0 0x11300580 0 0x80>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_c_clk CLK_IMPC_I2C5>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <49>;
|
|
sda-gpio-id = <50>;
|
|
};
|
|
|
|
i2c6: i2c@11281000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11281000 0 0x1000>,
|
|
<0 0x11300600 0 0x80>;
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_c_clk CLK_IMPC_I2C6>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <51>;
|
|
sda-gpio-id = <52>;
|
|
};
|
|
|
|
i2c7: i2c@11e81000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11e81000 0 0x1000>,
|
|
<0 0x11300680 0 0x100>;
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_I2C7>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <176>;
|
|
sda-gpio-id = <177>;
|
|
};
|
|
|
|
i2c8: i2c@11e82000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11e82000 0 0x1000>,
|
|
<0 0x11300780 0 0x100>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_e_clk CLK_IMPE_I2C8>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <178>;
|
|
sda-gpio-id = <179>;
|
|
};
|
|
|
|
i2c9: i2c@11c72000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11c72000 0 0x1000>,
|
|
<0 0x11300880 0 0x100>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_es_clk CLK_IMPES_I2C9>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <154>;
|
|
sda-gpio-id = <155>;
|
|
};
|
|
|
|
i2c10: i2c@11282000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11282000 0 0x1000>,
|
|
<0 0x11300980 0 0x80>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_c_clk CLK_IMPC_I2C10>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <106>;
|
|
sda-gpio-id = <107>;
|
|
};
|
|
|
|
i2c11: i2c@11283000 {
|
|
compatible = "mediatek,mt6983-i2c";
|
|
reg = <0 0x11283000 0 0x1000>,
|
|
<0 0x11300a00 0 0x80>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&imp_iic_wrap_c_clk CLK_IMPC_I2C11>,
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <1>;
|
|
scl-gpio-id = <108>;
|
|
sda-gpio-id = <109>;
|
|
};
|
|
|
|
mtk_leds: mtk_leds {
|
|
backlight {
|
|
label = "lcd-backlight";
|
|
max-brightness = <2047>;
|
|
min-brightness = <4>;
|
|
max-hw-brightness = <2047>;
|
|
};
|
|
};
|
|
|
|
dpmaif:dpmaif@10014000 {
|
|
compatible = "mediatek,dpmaif";
|
|
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
|
|
<0 0x1022d000 0 0x1000>, /*PD_UL*/
|
|
<0 0x1022c000 0 0x1000>, /*PD_MD_MISC*/
|
|
<0 0x1022e000 0 0x1000>; /*SRAM*/
|
|
/* rxq0 irq: 175 303 335 */
|
|
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH 0>; /* new rxq1 irq: 721 840 872 */
|
|
mediatek,dpmaif-ver = <3>;
|
|
mediatek,dpmaif-cap = <0x00000004>;
|
|
mediatek,plat-info = <6886>;
|
|
clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_RG_MMW_DPMAIF26M>;
|
|
clock-names = "infra-dpmaif-clk",
|
|
"infra-dpmaif-blk-clk",
|
|
"infra-dpmaif-rg-mmw-clk";
|
|
interconnects = <&dvfsrc MT6873_MASTER_NETSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
|
|
interconnect-names = "icc-mdspd-bw";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>;
|
|
net-spd-ver = <6>;
|
|
dpmaif-infracfg = <&infracfg_ao_clk>;
|
|
};
|
|
|
|
ccifdriver:ccifdriver@10209000 {
|
|
compatible = "mediatek,ccci_ccif";
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
mediatek,sram-size = <512>;
|
|
/* DTS/GIC_ID: CCIF0 288/320; CCIF0 289/321 */
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF5_MD>;
|
|
clock-names = "infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif4-md",
|
|
"infra-ccif5-md";
|
|
};
|
|
|
|
mddriver:mddriver {
|
|
compatible = "mediatek,mddriver";
|
|
/* bit0~3: CLDMA|CCIF|DPMAIF */
|
|
mediatek,mdhif-type = <6>;
|
|
mediatek,md-id = <0>;
|
|
mediatek,ap-plat-info = <6886>;
|
|
mediatek,md-generation = <6298>;
|
|
/* 0x44: epon offset; */
|
|
/* 0x06: once a value[1] exist, means in l2sram */
|
|
/* value[1] not exist means in mddbgsys. the value(6) has no meaningful */
|
|
mediatek,offset-epon-md1 = <0x44 0x06>;
|
|
mediatek,cldma-capability = <10>;
|
|
/* bit0:srcclkena|bit1:srclken_o1_on|bit2:revert_sequencer */
|
|
mediatek,power-flow-config = <0x4>;
|
|
/* srclken-o1 set value |= 1<<21 */
|
|
mediatek,srclken-o1 = <0>;
|
|
reg = <0 0x0d124000 0 0x2000>; /* l2sram base address */
|
|
/* DTS/GIC_ID: MDWDT 285/317; CCIF0 288/320; CCIF0 289/321 */
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MD>;
|
|
ccci-infracfg = <&infracfg_ao_clk>;
|
|
ccci-topckgen = <&topckgen_clk>;
|
|
/* ccci-spmsleep = <&sleep>; */
|
|
};
|
|
|
|
md_auxadc:md-auxadc {
|
|
compatible = "mediatek,md_auxadc";
|
|
/* io-channels = <&auxadc 2>; */
|
|
io-channel-names = "md-channel",
|
|
"md-battery";
|
|
};
|
|
|
|
ccci_scp:ccci-scp {
|
|
compatible = "mediatek,ccci_md_scp";
|
|
reg = <0 0x1023c000 0 0x1000>, /* AP_CCIF2_BASE */
|
|
<0 0x1023d000 0 0x1000>; /* MD_CCIF2_BASE */
|
|
clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>;
|
|
clock-names = "infra-ccif2-ap",
|
|
"infra-ccif2-md";
|
|
};
|
|
|
|
md-ccif4@1024d000 {
|
|
compatible = "mediatek,md_ccif4";
|
|
reg = <0 0x1024d000 0 0x1000>;
|
|
};
|
|
|
|
md-ccif5@1025d000 {
|
|
compatible = "mediatek,md_ccif5";
|
|
reg = <0 0x1025d000 0 0x1000>;
|
|
|
|
};
|
|
|
|
mtk_sec_dmaheap {
|
|
compatible = "mediatek,dmaheap-region-base";
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_HDR>;
|
|
};
|
|
|
|
mtk-sec-dmaheap-apu {
|
|
compatible = "mediatek,dmaheap-apu-region-base";
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
};
|
|
|
|
mtk_iommu_debug {
|
|
compatible = "mediatek,mt6886-iommu-debug";
|
|
};
|
|
|
|
mtk_dmabufheap_debug0: dmaheap_test0 {
|
|
compatible = "mediatek, mtk_dmabufheap, iommu0";
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
mtk_dmabufheap_debug1: dmaheap_test1 {
|
|
compatible = "mediatek, mtk_dmabufheap, iommu1";
|
|
iommus = <&disp_iommu M4U_PORT_L1_DISP_FAKE1>;
|
|
};
|
|
|
|
iommu_test {
|
|
compatible = "mediatek,ktf-iommu-test";
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
aov: aov@0 {
|
|
compatible = "mediatek,aov";
|
|
status = "okay";
|
|
op_mode = <0>;
|
|
};
|
|
|
|
camsys_power: camsys-power {
|
|
compatible = "mediatek,vmm_notifier";
|
|
pd-id = <2>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CAM_VCORE>;
|
|
};
|
|
|
|
imgsys_power: imgsys-power {
|
|
compatible = "mediatek,vmm_notifier";
|
|
pd-id = <3>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_VCORE>;
|
|
};
|
|
|
|
hcp: hcp@0 {
|
|
compatible = "mediatek,hcp7s";
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L15_VIPI_D1>;
|
|
};
|
|
|
|
imgsys_cmdq: imgsys_cmdq@0 {
|
|
compatible = "mediatek,imgsys-cmdq-7s";
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L15_VIPI_D1>;
|
|
};
|
|
imgsys_fw: imgsys_fw@15000000 {
|
|
compatible = "mediatek,imgsys-isp7s";
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
reg = <0 0x15000000 0 0x4000>, /* 0 IMGSYS_TOP */
|
|
<0 0x15700000 0 0x10000>, /* 1 IMGSYS_TRAW */
|
|
<0 0x15040000 0 0x10000>, /* 2 IMGSYS_LTRAW */
|
|
<0 0x15100000 0 0x10000>, /* 3 IMGSYS_DIP */
|
|
<0 0x15150000 0 0x10000>, /* 4 IMGSYS_DIP_NR */
|
|
<0 0x15160000 0 0x10000>, /* 5 IMGSYS_DIP_NR2 */
|
|
<0 0x15210000 0 0x10000>, /* 6 IMGSYS_PQDIP_A */
|
|
<0 0x15510000 0 0x10000>, /* 7 IMGSYS_PQDIP_B */
|
|
<0 0x15200000 0 0x10000>, /* 8 IMGSYS_WPE_EIS */
|
|
<0 0x15500000 0 0x10000>, /* 9 IMGSYS_WPE_TNR */
|
|
<0 0x15600000 0 0x10000>, /* 10 IMGSYS_WPE_LITE */
|
|
<0 0x15220000 0 0x00100>, /* 11 IMGSYS_WPE1_DIP1 */
|
|
<0 0x15320000 0 0x10000>, /* 12 IMGSYS_ME */
|
|
<0 0x00000000 0 0x01500>, /* 13 IMGSYS_ADL_A */
|
|
<0 0x00000000 0 0x01500>, /* 14 IMGSYS_ADL_B */
|
|
<0 0x15520000 0 0x00100>, /* 15 IMGSYS_WPE2_DIP1 */
|
|
<0 0x15620000 0 0x00100>, /* 16 IMGSYS_WPE3_DIP1 */
|
|
<0 0x15110000 0 0x00100>, /* 17 IMGSYS_DIP_TOP */
|
|
<0 0x15130000 0 0x00100>, /* 18 IMGSYS_DIP_TOP_NR */
|
|
<0 0x15170000 0 0x00100>, /* 19 IMGSYS_DIP_TOP_NR2 */
|
|
<0 0x15710000 0 0x00100>, /* 20 IMGSYS_TRAW_DIP1 */
|
|
<0 0x15330000 0 0x10000>; /* 21 IMGSYS_ME_MMG */
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
mediatek,hcp = <&hcp>;
|
|
mediatek,larbs = <&smi_larb9>,
|
|
<&smi_larb10>,
|
|
<&smi_larb11>,
|
|
<&smi_larb15>,
|
|
<&smi_larb22>,
|
|
<&smi_larb23>,
|
|
<&smi_larb28>,
|
|
<&smi_larb12>;
|
|
mediatek,imgsys_cmdq = <&imgsys_cmdq>;
|
|
iommus = <&disp_iommu M4U_PORT_L28_IMGI_TI_A>;
|
|
mboxes = <&gce_m 0 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 1 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 2 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 3 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 4 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 5 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 16 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 17 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 18 3000 CMDQ_THR_PRIO_2>,
|
|
<&gce_m 19 3000 CMDQ_THR_PRIO_1>,
|
|
<&gce_m 22 3000 CMDQ_THR_PRIO_1>,
|
|
<&gce_m 23 3000 CMDQ_THR_PRIO_1>,
|
|
<&gce_m_sec 10 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
<&gce_m_sec 12 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>;
|
|
traw_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0>;
|
|
traw_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_1>;
|
|
traw_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_2>;
|
|
traw_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_3>;
|
|
traw_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_4>;
|
|
traw_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_5>;
|
|
traw_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_6>;
|
|
traw_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_7>;
|
|
traw_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_8>;
|
|
traw_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_9>;
|
|
ltraw_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0>;
|
|
ltraw_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_1>;
|
|
ltraw_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_2>;
|
|
ltraw_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_3>;
|
|
ltraw_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_4>;
|
|
ltraw_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_5>;
|
|
ltraw_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_6>;
|
|
ltraw_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_7>;
|
|
ltraw_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_8>;
|
|
ltraw_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_9>;
|
|
dip_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_0>;
|
|
dip_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_1>;
|
|
dip_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_2>;
|
|
dip_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_3>;
|
|
dip_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_4>;
|
|
dip_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_5>;
|
|
dip_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_6>;
|
|
dip_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_7>;
|
|
dip_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_8>;
|
|
dip_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_9>;
|
|
pqa_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_0>;
|
|
pqa_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_1>;
|
|
pqa_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_2>;
|
|
pqa_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_3>;
|
|
pqa_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_4>;
|
|
pqa_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_5>;
|
|
pqa_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_6>;
|
|
pqa_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_7>;
|
|
pqa_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_8>;
|
|
pqa_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_9>;
|
|
pqb_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_0>;
|
|
pqb_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_1>;
|
|
pqb_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_2>;
|
|
pqb_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_3>;
|
|
pqb_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_4>;
|
|
pqb_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_5>;
|
|
pqb_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_6>;
|
|
pqb_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_7>;
|
|
pqb_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_8>;
|
|
pqb_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_9>;
|
|
wpe_eis_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_0>;
|
|
|
|
wpe_eis_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_1>;
|
|
wpe_eis_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_2>;
|
|
wpe_eis_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_3>;
|
|
wpe_eis_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_4>;
|
|
wpe_eis_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_5>;
|
|
wpe_eis_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_6>;
|
|
wpe_eis_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_7>;
|
|
wpe_eis_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_8>;
|
|
wpe_eis_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2_9>;
|
|
wpe_tnr_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_0>;
|
|
wpe_tnr_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_1>;
|
|
wpe_tnr_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_2>;
|
|
wpe_tnr_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_3>;
|
|
wpe_tnr_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_4>;
|
|
wpe_tnr_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_5>;
|
|
wpe_tnr_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_6>;
|
|
wpe_tnr_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_7>;
|
|
wpe_tnr_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_8>;
|
|
wpe_tnr_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_P2_9>;
|
|
wpe_lite_cq_thread0_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_0>;
|
|
wpe_lite_cq_thread1_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_1>;
|
|
wpe_lite_cq_thread2_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_2>;
|
|
wpe_lite_cq_thread3_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_3>;
|
|
wpe_lite_cq_thread4_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_4>;
|
|
wpe_lite_cq_thread5_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_5>;
|
|
wpe_lite_cq_thread6_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_6>;
|
|
wpe_lite_cq_thread7_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_7>;
|
|
wpe_lite_cq_thread8_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_8>;
|
|
wpe_lite_cq_thread9_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2_9>;
|
|
me_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE>;
|
|
adl_tile_done =
|
|
/bits/ 16 <CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT>;
|
|
wpe_eis_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS>;
|
|
wpe_tnr_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR>;
|
|
wpe_lite_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE>;
|
|
traw_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_TRAW>;
|
|
ltraw_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_LTRAW>;
|
|
dip_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_DIP>;
|
|
pqdip_a_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A>;
|
|
pqdip_b_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B>;
|
|
me_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IPESYS_ME>;
|
|
vss_traw_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW>;
|
|
vss_ltraw_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW>;
|
|
vss_dip_sync_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP>;
|
|
sw_sync_token_pool_1 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_1>;
|
|
sw_sync_token_pool_2 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_2>;
|
|
sw_sync_token_pool_3 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_3>;
|
|
sw_sync_token_pool_4 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_4>;
|
|
sw_sync_token_pool_5 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_5>;
|
|
sw_sync_token_pool_6 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_6>;
|
|
sw_sync_token_pool_7 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_7>;
|
|
sw_sync_token_pool_8 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_8>;
|
|
sw_sync_token_pool_9 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_9>;
|
|
sw_sync_token_pool_10 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_10>;
|
|
sw_sync_token_pool_11 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_11>;
|
|
sw_sync_token_pool_12 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_12>;
|
|
sw_sync_token_pool_13 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_13>;
|
|
sw_sync_token_pool_14 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_14>;
|
|
sw_sync_token_pool_15 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_15>;
|
|
sw_sync_token_pool_16 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_16>;
|
|
sw_sync_token_pool_17 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_17>;
|
|
sw_sync_token_pool_18 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_18>;
|
|
sw_sync_token_pool_19 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_19>;
|
|
sw_sync_token_pool_20 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_20>;
|
|
sw_sync_token_pool_21 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_21>;
|
|
sw_sync_token_pool_22 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_22>;
|
|
sw_sync_token_pool_23 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_23>;
|
|
sw_sync_token_pool_24 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_24>;
|
|
sw_sync_token_pool_25 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_25>;
|
|
sw_sync_token_pool_26 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_26>;
|
|
sw_sync_token_pool_27 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_27>;
|
|
sw_sync_token_pool_28 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_28>;
|
|
sw_sync_token_pool_29 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_29>;
|
|
sw_sync_token_pool_30 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_30>;
|
|
sw_sync_token_pool_31 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_31>;
|
|
sw_sync_token_pool_32 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_32>;
|
|
sw_sync_token_pool_33 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_33>;
|
|
sw_sync_token_pool_34 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_34>;
|
|
sw_sync_token_pool_35 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_35>;
|
|
sw_sync_token_pool_36 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_36>;
|
|
sw_sync_token_pool_37 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_37>;
|
|
sw_sync_token_pool_38 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_38>;
|
|
sw_sync_token_pool_39 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_39>;
|
|
sw_sync_token_pool_40 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_40>;
|
|
sw_sync_token_pool_41 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_41>;
|
|
sw_sync_token_pool_42 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_42>;
|
|
sw_sync_token_pool_43 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_43>;
|
|
sw_sync_token_pool_44 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_44>;
|
|
sw_sync_token_pool_45 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_45>;
|
|
sw_sync_token_pool_46 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_46>;
|
|
sw_sync_token_pool_47 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_47>;
|
|
sw_sync_token_pool_48 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_48>;
|
|
sw_sync_token_pool_49 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_49>;
|
|
sw_sync_token_pool_50 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_50>;
|
|
sw_sync_token_pool_51 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_51>;
|
|
sw_sync_token_pool_52 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_52>;
|
|
sw_sync_token_pool_53 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_53>;
|
|
sw_sync_token_pool_54 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_54>;
|
|
sw_sync_token_pool_55 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_55>;
|
|
sw_sync_token_pool_56 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_56>;
|
|
sw_sync_token_pool_57 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_57>;
|
|
sw_sync_token_pool_58 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_58>;
|
|
sw_sync_token_pool_59 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_59>;
|
|
sw_sync_token_pool_60 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_60>;
|
|
sw_sync_token_pool_61 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_61>;
|
|
sw_sync_token_pool_62 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_62>;
|
|
sw_sync_token_pool_63 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_63>;
|
|
sw_sync_token_pool_64 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_64>;
|
|
sw_sync_token_pool_65 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_65>;
|
|
sw_sync_token_pool_66 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_66>;
|
|
sw_sync_token_pool_67 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_67>;
|
|
sw_sync_token_pool_68 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_68>;
|
|
sw_sync_token_pool_69 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_69>;
|
|
sw_sync_token_pool_70 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_70>;
|
|
sw_sync_token_pool_71 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_71>;
|
|
sw_sync_token_pool_72 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_72>;
|
|
sw_sync_token_pool_73 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_73>;
|
|
sw_sync_token_pool_74 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_74>;
|
|
sw_sync_token_pool_75 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_75>;
|
|
sw_sync_token_pool_76 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_76>;
|
|
sw_sync_token_pool_77 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_77>;
|
|
sw_sync_token_pool_78 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_78>;
|
|
sw_sync_token_pool_79 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_79>;
|
|
sw_sync_token_pool_80 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_80>;
|
|
sw_sync_token_pool_81 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_81>;
|
|
sw_sync_token_pool_82 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_82>;
|
|
sw_sync_token_pool_83 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_83>;
|
|
sw_sync_token_pool_84 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_84>;
|
|
sw_sync_token_pool_85 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_85>;
|
|
sw_sync_token_pool_86 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_86>;
|
|
sw_sync_token_pool_87 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_87>;
|
|
sw_sync_token_pool_88 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_88>;
|
|
sw_sync_token_pool_89 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_89>;
|
|
sw_sync_token_pool_90 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_90>;
|
|
sw_sync_token_pool_91 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_91>;
|
|
sw_sync_token_pool_92 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_92>;
|
|
sw_sync_token_pool_93 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_93>;
|
|
sw_sync_token_pool_94 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_94>;
|
|
sw_sync_token_pool_95 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_95>;
|
|
sw_sync_token_pool_96 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_96>;
|
|
sw_sync_token_pool_97 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_97>;
|
|
sw_sync_token_pool_98 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_98>;
|
|
sw_sync_token_pool_99 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_99>;
|
|
sw_sync_token_pool_100 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_100>;
|
|
sw_sync_token_pool_101 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_101>;
|
|
sw_sync_token_pool_102 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_102>;
|
|
sw_sync_token_pool_103 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_103>;
|
|
sw_sync_token_pool_104 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_104>;
|
|
sw_sync_token_pool_105 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_105>;
|
|
sw_sync_token_pool_106 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_106>;
|
|
sw_sync_token_pool_107 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_107>;
|
|
sw_sync_token_pool_108 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_108>;
|
|
sw_sync_token_pool_109 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_109>;
|
|
sw_sync_token_pool_110 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_110>;
|
|
sw_sync_token_pool_111 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_111>;
|
|
sw_sync_token_pool_112 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_112>;
|
|
sw_sync_token_pool_113 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_113>;
|
|
sw_sync_token_pool_114 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_114>;
|
|
sw_sync_token_pool_115 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_115>;
|
|
sw_sync_token_pool_116 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_116>;
|
|
sw_sync_token_pool_117 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_117>;
|
|
sw_sync_token_pool_118 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_118>;
|
|
sw_sync_token_pool_119 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_119>;
|
|
sw_sync_token_pool_120 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_120>;
|
|
sw_sync_token_pool_121 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_121>;
|
|
sw_sync_token_pool_122 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_122>;
|
|
sw_sync_token_pool_123 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_123>;
|
|
sw_sync_token_pool_124 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_124>;
|
|
sw_sync_token_pool_125 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_125>;
|
|
sw_sync_token_pool_126 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_126>;
|
|
sw_sync_token_pool_127 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_127>;
|
|
sw_sync_token_pool_128 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_128>;
|
|
sw_sync_token_pool_129 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_129>;
|
|
sw_sync_token_pool_130 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_130>;
|
|
sw_sync_token_pool_131 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_131>;
|
|
sw_sync_token_pool_132 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_132>;
|
|
sw_sync_token_pool_133 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_133>;
|
|
sw_sync_token_pool_134 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_134>;
|
|
sw_sync_token_pool_135 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_135>;
|
|
sw_sync_token_pool_136 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_136>;
|
|
sw_sync_token_pool_137 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_137>;
|
|
sw_sync_token_pool_138 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_138>;
|
|
sw_sync_token_pool_139 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_139>;
|
|
sw_sync_token_pool_140 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_140>;
|
|
sw_sync_token_pool_141 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_141>;
|
|
sw_sync_token_pool_142 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_142>;
|
|
sw_sync_token_pool_143 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_143>;
|
|
sw_sync_token_pool_144 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_144>;
|
|
sw_sync_token_pool_145 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_145>;
|
|
sw_sync_token_pool_146 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_146>;
|
|
sw_sync_token_pool_147 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_147>;
|
|
sw_sync_token_pool_148 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_148>;
|
|
sw_sync_token_pool_149 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_149>;
|
|
sw_sync_token_pool_150 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_150>;
|
|
sw_sync_token_pool_151 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_151>;
|
|
sw_sync_token_pool_152 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_152>;
|
|
sw_sync_token_pool_153 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_153>;
|
|
sw_sync_token_pool_154 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_154>;
|
|
sw_sync_token_pool_155 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_155>;
|
|
sw_sync_token_pool_156 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_156>;
|
|
sw_sync_token_pool_157 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_157>;
|
|
sw_sync_token_pool_158 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_158>;
|
|
sw_sync_token_pool_159 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_159>;
|
|
sw_sync_token_pool_160 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_160>;
|
|
sw_sync_token_pool_161 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_161>;
|
|
sw_sync_token_pool_162 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_162>;
|
|
sw_sync_token_pool_163 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_163>;
|
|
sw_sync_token_pool_164 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_164>;
|
|
sw_sync_token_pool_165 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_165>;
|
|
sw_sync_token_pool_166 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_166>;
|
|
sw_sync_token_pool_167 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_167>;
|
|
sw_sync_token_pool_168 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_168>;
|
|
sw_sync_token_pool_169 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_169>;
|
|
sw_sync_token_pool_170 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_170>;
|
|
sw_sync_token_pool_171 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_171>;
|
|
sw_sync_token_pool_172 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_172>;
|
|
sw_sync_token_pool_173 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_173>;
|
|
sw_sync_token_pool_174 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_174>;
|
|
sw_sync_token_pool_175 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_175>;
|
|
sw_sync_token_pool_176 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_176>;
|
|
sw_sync_token_pool_177 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_177>;
|
|
sw_sync_token_pool_178 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_178>;
|
|
sw_sync_token_pool_179 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_179>;
|
|
sw_sync_token_pool_180 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_180>;
|
|
sw_sync_token_pool_181 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_181>;
|
|
sw_sync_token_pool_182 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_182>;
|
|
sw_sync_token_pool_183 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_183>;
|
|
sw_sync_token_pool_184 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_184>;
|
|
sw_sync_token_pool_185 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_185>;
|
|
sw_sync_token_pool_186 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_186>;
|
|
sw_sync_token_pool_187 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_187>;
|
|
sw_sync_token_pool_188 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_188>;
|
|
sw_sync_token_pool_189 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_189>;
|
|
sw_sync_token_pool_190 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_190>;
|
|
sw_sync_token_pool_191 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_191>;
|
|
sw_sync_token_pool_192 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_192>;
|
|
sw_sync_token_pool_193 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_193>;
|
|
sw_sync_token_pool_194 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_194>;
|
|
sw_sync_token_pool_195 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_195>;
|
|
sw_sync_token_pool_196 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_196>;
|
|
sw_sync_token_pool_197 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_197>;
|
|
sw_sync_token_pool_198 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_198>;
|
|
sw_sync_token_pool_199 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_199>;
|
|
sw_sync_token_pool_200 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_200>;
|
|
sw_sync_token_pool_201 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_201>;
|
|
sw_sync_token_pool_202 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_202>;
|
|
sw_sync_token_pool_203 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_203>;
|
|
sw_sync_token_pool_204 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_204>;
|
|
sw_sync_token_pool_205 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_205>;
|
|
sw_sync_token_pool_206 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_206>;
|
|
sw_sync_token_pool_207 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_207>;
|
|
sw_sync_token_pool_208 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_208>;
|
|
sw_sync_token_pool_209 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_209>;
|
|
sw_sync_token_pool_210 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_210>;
|
|
sw_sync_token_pool_211 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_211>;
|
|
sw_sync_token_pool_212 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_212>;
|
|
sw_sync_token_pool_213 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_213>;
|
|
sw_sync_token_pool_214 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_214>;
|
|
sw_sync_token_pool_215 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_215>;
|
|
sw_sync_token_pool_216 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_216>;
|
|
sw_sync_token_pool_217 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_217>;
|
|
sw_sync_token_pool_218 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_218>;
|
|
sw_sync_token_pool_219 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_219>;
|
|
sw_sync_token_pool_220 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_220>;
|
|
sw_sync_token_pool_221 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_221>;
|
|
sw_sync_token_pool_222 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_222>;
|
|
sw_sync_token_pool_223 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_223>;
|
|
sw_sync_token_pool_224 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_224>;
|
|
sw_sync_token_pool_225 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_225>;
|
|
sw_sync_token_pool_226 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_226>;
|
|
sw_sync_token_pool_227 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_227>;
|
|
sw_sync_token_pool_228 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_228>;
|
|
sw_sync_token_pool_229 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_229>;
|
|
sw_sync_token_pool_230 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_230>;
|
|
sw_sync_token_pool_231 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_231>;
|
|
sw_sync_token_pool_232 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_232>;
|
|
sw_sync_token_pool_233 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_233>;
|
|
sw_sync_token_pool_234 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_234>;
|
|
sw_sync_token_pool_235 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_235>;
|
|
sw_sync_token_pool_236 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_236>;
|
|
sw_sync_token_pool_237 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_237>;
|
|
sw_sync_token_pool_238 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_238>;
|
|
sw_sync_token_pool_239 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_239>;
|
|
sw_sync_token_pool_240 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_240>;
|
|
sw_sync_token_pool_241 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_241>;
|
|
sw_sync_token_pool_242 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_242>;
|
|
sw_sync_token_pool_243 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_243>;
|
|
sw_sync_token_pool_244 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_244>;
|
|
sw_sync_token_pool_245 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_245>;
|
|
sw_sync_token_pool_246 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_246>;
|
|
sw_sync_token_pool_247 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_247>;
|
|
sw_sync_token_pool_248 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_248>;
|
|
sw_sync_token_pool_249 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_249>;
|
|
sw_sync_token_pool_250 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_250>;
|
|
sw_sync_token_tzmp_isp_wait =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT>;
|
|
sw_sync_token_tzmp_isp_set =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_TZMP_ISP_SET>;
|
|
#if 0
|
|
sw_sync_token_camsys_pool_1 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_1>;
|
|
sw_sync_token_camsys_pool_2 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_2>;
|
|
sw_sync_token_camsys_pool_3 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_3>;
|
|
sw_sync_token_camsys_pool_4 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_4>;
|
|
sw_sync_token_camsys_pool_5 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_5>;
|
|
sw_sync_token_camsys_pool_6 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_6>;
|
|
sw_sync_token_camsys_pool_7 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_7>;
|
|
sw_sync_token_camsys_pool_8 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_8>;
|
|
sw_sync_token_camsys_pool_9 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_9>;
|
|
sw_sync_token_camsys_pool_10 =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_10>;
|
|
#endif
|
|
clocks = <&imgsys_main_clk CLK_IMG_TRAW0>,
|
|
<&imgsys_main_clk CLK_IMG_TRAW1>,
|
|
<&imgsys_main_clk CLK_IMG_VCORE_GALS>,
|
|
<&imgsys_main_clk CLK_IMG_DIP0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE0>,
|
|
<&imgsys_main_clk CLK_IMG_WPE1>,
|
|
<&imgsys_main_clk CLK_IMG_WPE2>,
|
|
<&imgsys_main_clk CLK_IMG_WPE2>,
|
|
<&imgsys_main_clk CLK_IMG_AVS>,
|
|
<&imgsys_main_clk CLK_IMG_GALS>,
|
|
<&dip_top_dip1_clk CLK_DIP_TOP_DIP1_DIP_TOP>,
|
|
<&dip_nr1_dip1_clk CLK_DIP_NR1_DIP1_LARB>,
|
|
<&dip_nr1_dip1_clk CLK_DIP_NR1_DIP1_DIP_NR1>,
|
|
<&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_DIP_NR>,
|
|
<&wpe1_dip1_clk CLK_WPE1_DIP1_WPE>,
|
|
<&wpe2_dip1_clk CLK_WPE2_DIP1_WPE>,
|
|
<&wpe3_dip1_clk CLK_WPE3_DIP1_WPE>,
|
|
<&traw_dip1_clk CLK_TRAW_DIP1_TRAW>,
|
|
<&imgsys_main_clk CLK_IMG_IPE>,
|
|
<&imgsys_main_clk CLK_IMG_ME>,
|
|
<&imgsys_main_clk CLK_IMG_MMG>,
|
|
<&mmdvfs_clk CLK_MMDVFS_IMG>;
|
|
clock-names = "IMGSYS_CG_IMG_TRAW0",
|
|
"IMGSYS_CG_IMG_TRAW1",
|
|
"IMGSYS_CG_IMG_VCORE_GALS",
|
|
"IMGSYS_CG_IMG_DIP0",
|
|
"IMGSYS_CG_IMG_WPE0",
|
|
"IMGSYS_CG_IMG_WPE1",
|
|
"IMGSYS_CG_IMG_WPE2",
|
|
"IMGSYS_CG_IMG_ADL_TOP0",
|
|
"IMGSYS_CG_IMG_AVS",
|
|
"IMGSYS_CG_IMG_GALS",
|
|
"DIP_TOP_DIP_TOP",
|
|
"DIP_NR1_DIP1_LARB",
|
|
"DIP_NR1_DIP_NR1",
|
|
"DIP_NR2_DIP_NR",
|
|
"WPE1_CG_DIP1_WPE",
|
|
"WPE2_CG_DIP1_WPE",
|
|
"WPE3_CG_DIP1_WPE",
|
|
"TRAW_CG_DIP1_TRAW",
|
|
"IMGSYS_CG_IMG_IPE",
|
|
"ME_CG",
|
|
"MMG_CG",
|
|
"mmdvfs_clk";
|
|
operating-points-v2 = <&opp_table_img>;
|
|
#if 0
|
|
dvfsrc-vmm-supply = <&vmm_proxy_label>;
|
|
#endif
|
|
mediatek,imgsys-qos-sc-motr = <1>;
|
|
mediatek,imgsys-qos-sc-nums = <4>;
|
|
mediatek,imgsys-qos-sc-id = <6 6 7 7>;
|
|
interconnects =
|
|
<&mmqos SLAVE_LARB(10)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos SLAVE_LARB(22)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos SLAVE_LARB(9)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos SLAVE_LARB(15)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"l10_common_r_0",
|
|
"l22_common_w_0",
|
|
"l9_common_r_1",
|
|
"l15_common_w_1";
|
|
};
|
|
|
|
aie: aie@15310000 {
|
|
compatible = "mediatek,aie-isp7s";
|
|
reg = <0 0x15310000 0 0x1000>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
mboxes = <&gce_m 20 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_m_sec 11 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>;
|
|
mediatek,larb = <&smi_larb12>;
|
|
mediatek,imgsys_fw = <&imgsys_fw>;
|
|
fdvt_frame_done = <CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE>;
|
|
sw_sync_token_tzmp_aie_wait = <CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT>;
|
|
sw_sync_token_tzmp_aie_set = <CMDQ_SYNC_TOKEN_TZMP_AIE_SET>;
|
|
iommus = <&disp_iommu M4U_PORT_L12_FDVT_RDA_0>,
|
|
<&disp_iommu M4U_PORT_L12_FDVT_WRA_0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_ISP_MAIN>;
|
|
clocks = <&imgsys_main_clk CLK_IMG_VCORE_GALS>,
|
|
<&imgsys_main_clk CLK_IMG_FDVT>,
|
|
<&imgsys_main_clk CLK_IMG_LARB12>,
|
|
<&imgsys_main_clk CLK_IMG_IPE>;
|
|
clock-names = "VCORE_GALS",
|
|
"IPE_FDVT",
|
|
"IPE_SMI_LARB12",
|
|
"IMG_IPE";
|
|
};
|
|
|
|
ipesys_me: ipesys_me@15320000 {
|
|
compatible = "mediatek,ipesys-me-isp7s";
|
|
reg = <0 0x15320000 0 0x10000>; /* 9 IMGSYS_ME */
|
|
#if 0
|
|
mediatek,larb = <&smi_larb12>;
|
|
iommus = <&mdp_iommu M4U_PORT_L12_IPE_ME_RDMA>,
|
|
<&mdp_iommu M4U_PORT_L12_IPE_ME_WDMA>;
|
|
clocks =
|
|
<&imgsys_main_clk CLK_IMGSYS_MAIN_IPE>,
|
|
<&ipesys_clk CLK_IPESYS_IPESYS_TOP>,
|
|
<&ipesys_clk CLK_IPESYS_ME>,
|
|
<&ipesys_clk CLK_IPESYS_SMI_LARB12>;
|
|
|
|
clock-names =
|
|
"ME_CG_IPE",
|
|
"ME_CG_IPE_TOP",
|
|
"ME_CG",
|
|
"ME_CG_LARB12";
|
|
#endif
|
|
};
|
|
|
|
apu_iommu0_bank1: iommu@19011000 {
|
|
compatible = "mediatek,common-apu-iommu0-bank1";
|
|
mediatek,bank-id = <1>;
|
|
reg = <0 0x19011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
apu_iommu0_bank2: iommu@19012000 {
|
|
compatible = "mediatek,common-apu-iommu0-bank2";
|
|
mediatek,bank-id = <2>;
|
|
reg = <0 0x19012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
apu_iommu0_bank3: iommu@19013000 {
|
|
compatible = "mediatek,common-apu-iommu0-bank3";
|
|
mediatek,bank-id = <3>;
|
|
reg = <0 0x19013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
apu_iommu0_bank4: iommu@19014000 {
|
|
compatible = "mediatek,common-apu-iommu0-bank4";
|
|
mediatek,bank-id = <4>;
|
|
reg = <0 0x19014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
apu_iommu0: iommu@19010000 {
|
|
compatible = "mediatek,mt6886-apu-iommu0";
|
|
reg = <0 0x19010000 0 0x1000>;
|
|
table_id = <1>;
|
|
mediatek,apu_power = <&apusys_rv>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_APU>;
|
|
mediatek,iommu_banks = <&apu_iommu0_bank1 &apu_iommu0_bank2
|
|
&apu_iommu0_bank3 &apu_iommu0_bank4>;
|
|
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
disp_iommu_bank1: iommu@1e803000 {
|
|
compatible = "mediatek,common-disp-iommu-bank1";
|
|
mediatek,bank-id = <1>;
|
|
reg = <0 0x1e803000 0 0x1000>;
|
|
interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
disp_iommu_bank2: iommu@1e804000 {
|
|
compatible = "mediatek,common-disp-iommu-bank2";
|
|
mediatek,bank-id = <2>;
|
|
reg = <0 0x1e804000 0 0x1000>;
|
|
interrupts = <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
disp_iommu_bank3: iommu@1e805000 {
|
|
compatible = "mediatek,common-disp-iommu-bank3";
|
|
mediatek,bank-id = <3>;
|
|
reg = <0 0x1e805000 0 0x1000>;
|
|
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
disp_iommu_bank4: iommu@1e806000 {
|
|
compatible = "mediatek,common-disp-iommu-bank4";
|
|
mediatek,bank-id = <4>;
|
|
reg = <0 0x1e806000 0 0x1000>;
|
|
interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
disp_iommu: iommu@1e802000 {
|
|
compatible = "mediatek,mt6886-disp-iommu";
|
|
reg = <0 0x1e802000 0 0x1000>;
|
|
table_id = <0>;
|
|
mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>,
|
|
<&smi_larb4 &smi_larb7 &smi_larb9>,
|
|
<&smi_larb10 &smi_larb11 &smi_larb12>,
|
|
<&smi_larb13 &smi_larb14 &smi_larb15>,
|
|
<&smi_larb16 &smi_larb17 &smi_larb19>,
|
|
<&smi_larb22 &smi_larb23 &smi_larb25>,
|
|
<&smi_larb26 &smi_larb27 &smi_larb28>,
|
|
<&smi_larb29 &smi_larb30 &smi_larb34>;
|
|
mediatek,iommu_banks = <&disp_iommu_bank1 &disp_iommu_bank2
|
|
&disp_iommu_bank3 &disp_iommu_bank4>;
|
|
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ssusb: usb0@11201000 {
|
|
compatible = "mediatek,mtu3";
|
|
reg = <0 0x11201000 0 0x2e00>,
|
|
<0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
vusb33-supply = <&mt6368_vusb>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
phy-cells = <1>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
|
<&u3port0 PHY_TYPE_USB3>;
|
|
clocks = <&pericfg_ao_clk CLK_PERAO_USB_SYS>,
|
|
<&pericfg_ao_clk CLK_PERAO_USB_XHCI>,
|
|
<&pericfg_ao_clk CLK_PERAO_USB_BUS>;
|
|
clock-names = "sys_ck", "host_ck", "mcu_ck";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
dr_mode = "otg";
|
|
maximum-speed = "high-speed";
|
|
mediatek,force-vbus;
|
|
mediatek,clk-mgr;
|
|
mediatek,usb3-drd;
|
|
mediatek,noise-still-tr;
|
|
mediatek,gen1-txdeemph;
|
|
mediatek,hwrscs-vers = <1>;
|
|
mediatek,syscon-wakeup = <&pericfg_ao_clk 0x200 104>;
|
|
wakeup-source;
|
|
usb-role-switch;
|
|
cdp-block;
|
|
port {
|
|
mtu3_drd_switch: endpoint {
|
|
remote-endpoint = <&usb_role>;
|
|
};
|
|
};
|
|
|
|
usb_host: xhci0@11200000 {
|
|
compatible = "mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x1000>;
|
|
reg-names = "mac";
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "sys_ck";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
u3phy: usb-phy0@11e40000 {
|
|
compatible = "mediatek,xsphy";
|
|
reg = <0 0x11e43000 0 0x200>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
u2port0: usb2-phy0@11e40000 {
|
|
reg = <0 0x11e40000 0 0x400>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
usb2jtag = <&vlpcfg_bus 2>;
|
|
nvmem-cells = <&u2_phy_data>, <&u2_phy_data>;
|
|
nvmem-cell-names = "intr_cal", "term_cal";
|
|
nvmem-cell-masks = <0x3f 0xf00>;
|
|
mediatek,efuse-intr = <0x23>;
|
|
mediatek,pll-fbksel = <0x0>;
|
|
mediatek,pll-posdiv = <0x0>;
|
|
mediatek,eye-vrt = <0x2>;
|
|
mediatek,rx-sqth = <0x5>;
|
|
mediatek,discth = <0x7>;
|
|
mediatek,lpm-parameter = <0x19 0x1e 0x1e>;
|
|
};
|
|
|
|
u3port0: usb3-phy0@11e43000 {
|
|
reg = <0 0x11e43400 0 0x500>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
scp_infra: scp_infra@10001000 {
|
|
compatible = "mediatek,scpinfra";
|
|
reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */
|
|
<0 0x10006000 0 0x1000>, /* spm */
|
|
<0 0x10000000 0 0x1000>; /* topckgen */
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
spmi: spmi@1c804000 {
|
|
compatible = "mediatek,mt6886-spmi";
|
|
reg = <0 0x1c804000 0 0x0008ff>,
|
|
<0 0x1c801000 0 0x000100>,
|
|
<0 0x0d0a0000 0 0x0000dc>;
|
|
reg-names = "pmif", "spmimst";
|
|
interrupts-extended = <&pio 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&gic GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "rcs_irq", "pmif_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
irq_event_en = <0x80000000 0x0 0x0 0x1f8 0x0>;
|
|
swinf_ch_start = <11>;
|
|
ap_swinf_no = <2>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
pmi_pmif_mpu: spmi_pmif_mpu@1c804900 {
|
|
compatible = "mediatek,mt6886-spmi_pmif_mpu";
|
|
reg = <0 0x1c804900 0 0x000500>;
|
|
reg-names = "pmif_mpu";
|
|
mediatek,pmic-all-rgn-en = <0x230078>;
|
|
mediatek,kernel-enable-time = <0x0>;
|
|
};
|
|
|
|
dvfsrc: dvfsrc@1c00f000 {
|
|
compatible = "mediatek,mt6886-dvfsrc";
|
|
reg = <0 0x1c00f000 0 0x1000>,
|
|
<0 0x1c001000 0 0x1000>;
|
|
reg-names = "dvfsrc", "spm";
|
|
#interconnect-cells = <1>;
|
|
|
|
dvfsrc_vcore: dvfsrc-vcore {
|
|
regulator-name = "dvfsrc-vcore";
|
|
regulator-min-microvolt = <575000>;
|
|
regulator-max-microvolt = <750000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dvfsrc_freq_opp7: opp7 {
|
|
opp-peak-KBps = <0>;
|
|
};
|
|
dvfsrc_freq_opp6: opp6 {
|
|
opp-peak-KBps = <2500000>;
|
|
};
|
|
dvfsrc_freq_opp5: opp5 {
|
|
opp-peak-KBps = <5100000>;
|
|
};
|
|
dvfsrc_freq_opp4: opp4 {
|
|
opp-peak-KBps = <5900000>;
|
|
};
|
|
dvfsrc_freq_opp3: opp3 {
|
|
opp-peak-KBps = <6800000>;
|
|
};
|
|
dvfsrc_freq_opp2: opp2 {
|
|
opp-peak-KBps = <9900000>;
|
|
};
|
|
dvfsrc_freq_opp1: opp1 {
|
|
opp-peak-KBps = <13600000>;
|
|
};
|
|
dvfsrc_freq_opp0: opp0 {
|
|
opp-peak-KBps = <17600000>;
|
|
};
|
|
|
|
dvfsrc-helper {
|
|
compatible = "mediatek,dvfsrc-helper";
|
|
vcore-supply = <&mt6363_vbuck5>;
|
|
rc-vcore-supply = <&dvfsrc_vcore>;
|
|
interconnects = <&dvfsrc MT6873_MASTER_DBGIF
|
|
&dvfsrc MT6873_SLAVE_DDR_EMI>,
|
|
<&dvfsrc MT6873_MASTER_DBGIF
|
|
&dvfsrc MT6873_SLAVE_DDR_EMI>,
|
|
<&dvfsrc MT6873_MASTER_HRT_DBGIF
|
|
&dvfsrc MT6873_SLAVE_HRT_DDR_EMI>;
|
|
interconnect-names = "icc-bw", "icc-perf-bw", "icc-hrt-bw";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>,
|
|
<&dvfsrc_freq_opp3>,
|
|
<&dvfsrc_freq_opp4>,
|
|
<&dvfsrc_freq_opp5>,
|
|
<&dvfsrc_freq_opp6>;
|
|
};
|
|
|
|
dvfsrc-met {
|
|
rc-vcore-supply = <&dvfsrc_vcore>;
|
|
interconnects = <&dvfsrc MT6873_MASTER_DBGIF
|
|
&dvfsrc MT6873_SLAVE_DDR_EMI>,
|
|
<&dvfsrc MT6873_MASTER_HRT_DBGIF
|
|
&dvfsrc MT6873_SLAVE_HRT_DDR_EMI>;
|
|
interconnect-names = "icc-bw", "icc-hrt-bw";
|
|
compatible = "mediatek,dvfsrc-met";
|
|
};
|
|
};
|
|
|
|
keypad: kp@1c00e000 {
|
|
compatible = "mediatek,kp";
|
|
reg = <0 0x1c00e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING 0>;
|
|
mediatek,key-debounce-ms = <1024>;
|
|
mediatek,hw-map-num = <72>;
|
|
mediatek,hw-init-map = <114 0 0 0 0 0 0 0 0 0 0 0 0
|
|
0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
|
0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
|
0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
|
0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
|
0 0 0>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "kpd";
|
|
};
|
|
|
|
regulator_vibrator: regulator-vibrator {
|
|
compatible = "regulator-vibrator";
|
|
label = "vibrator";
|
|
min-volt = <2800000>;
|
|
max-volt = <3500000>;
|
|
vib-supply = <&mt6368_vibr>;
|
|
};
|
|
|
|
u3fpgaphy: u3fpgaphy {
|
|
compatible = "mediatek,fpga-u3phy";
|
|
mediatek,ippc = <0x11203e00>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
fpga_i2c_physical_base = <0x11c70000>;
|
|
status = "disabled";
|
|
|
|
u3fpgaport0: u3fpgaport0 {
|
|
chip-id= <0xa60931a>;
|
|
port = <0>;
|
|
pclk_phase = <23>;
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt6886-mmc";
|
|
reg = <0 0x11240000 0 0x1000>,
|
|
<0 0x11d80000 0 0x1000>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
|
|
<&topckgen_clk CLK_TOP_MSDC_MACRO_SEL>,
|
|
<&pericfg_ao_clk CLK_PERAO_MSDC1_H>,
|
|
<&pericfg_ao_clk CLK_PERAO_MSDC1>;
|
|
clock-names = "source", "macro", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu_protected_memory_allocator: protected-memory-allocator@13c00000 {
|
|
compatible = "arm,protected-memory-allocator";
|
|
reg = <0 0x13c00000 0 0x30000>;
|
|
reg-names = "gpueb_base";
|
|
gpr-offset = <0x2fd1c>;
|
|
gpr-id = <6>;
|
|
gmpu-table-size = <0x0>;
|
|
protected-reserve-size = <0x800000>;
|
|
};
|
|
|
|
mali: mali@13000000 {
|
|
compatible = "mediatek,mali", "arm,mali-valhall";
|
|
reg = <0 0x13000000 0 0x480000>;
|
|
physical-memory-group-manager = <&mgm>;
|
|
interrupts =
|
|
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names =
|
|
"GPU",
|
|
"MMU",
|
|
"JOB",
|
|
"EVENT";
|
|
protected-memory-allocator = <&gpu_protected_memory_allocator>;
|
|
operating-points-v2 = <&gpu_mali_opp>;
|
|
#cooling-cells = <2>;
|
|
ged-supply = <&ged>;
|
|
firmware_idle_hytseresis_time_ms = <5>;
|
|
default-glb-pwroff-timeout-us = <300>;
|
|
|
|
};
|
|
|
|
gpu_mali_opp: opp-table0 {
|
|
compatible = "operating-points-v2";
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <1130000000>;
|
|
opp-microvolt = <850000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <1115000000>;
|
|
opp-microvolt = <850000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <1100000000>;
|
|
opp-microvolt = <843750>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <1085000000>;
|
|
opp-microvolt = <837500>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <1070000000>;
|
|
opp-microvolt = <831250>;
|
|
};
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <1055000000>;
|
|
opp-microvolt = <825000>;
|
|
};
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <1040000000>;
|
|
opp-microvolt = <818750>;
|
|
};
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <1025000000>;
|
|
opp-microvolt = <812500>;
|
|
};
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <1010000000>;
|
|
opp-microvolt = <806250>;
|
|
};
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <995000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp10 {
|
|
opp-hz = /bits/ 64 <980000000>;
|
|
opp-microvolt = <793750>;
|
|
};
|
|
opp11 {
|
|
opp-hz = /bits/ 64 <965000000>;
|
|
opp-microvolt = <787500>;
|
|
};
|
|
opp12 {
|
|
opp-hz = /bits/ 64 <950000000>;
|
|
opp-microvolt = <781250>;
|
|
};
|
|
opp13 {
|
|
opp-hz = /bits/ 64 <935000000>;
|
|
opp-microvolt = <775000>;
|
|
};
|
|
opp14 {
|
|
opp-hz = /bits/ 64 <920000000>;
|
|
opp-microvolt = <775000>;
|
|
};
|
|
opp15 {
|
|
opp-hz = /bits/ 64 <905000000>;
|
|
opp-microvolt = <768750>;
|
|
};
|
|
opp16 {
|
|
opp-hz = /bits/ 64 <890000000>;
|
|
opp-microvolt = <762500>;
|
|
};
|
|
opp17 {
|
|
opp-hz = /bits/ 64 <872000000>;
|
|
opp-microvolt = <756250>;
|
|
};
|
|
opp18 {
|
|
opp-hz = /bits/ 64 <854000000>;
|
|
opp-microvolt = <750000>;
|
|
};
|
|
opp19 {
|
|
opp-hz = /bits/ 64 <836000000>;
|
|
opp-microvolt = <737500>;
|
|
};
|
|
opp20 {
|
|
opp-hz = /bits/ 64 <818000000>;
|
|
opp-microvolt = <731250>;
|
|
};
|
|
opp21 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
opp-microvolt = <725000>;
|
|
};
|
|
opp22 {
|
|
opp-hz = /bits/ 64 <782000000>;
|
|
opp-microvolt = <718750>;
|
|
};
|
|
opp23 {
|
|
opp-hz = /bits/ 64 <764000000>;
|
|
opp-microvolt = <712500>;
|
|
};
|
|
opp24 {
|
|
opp-hz = /bits/ 64 <746000000>;
|
|
opp-microvolt = <706250>;
|
|
};
|
|
opp25 {
|
|
opp-hz = /bits/ 64 <728000000>;
|
|
opp-microvolt = <700000>;
|
|
};
|
|
opp26 {
|
|
opp-hz = /bits/ 64 <710000000>;
|
|
opp-microvolt = <693750>;
|
|
};
|
|
opp27 {
|
|
opp-hz = /bits/ 64 <692000000>;
|
|
opp-microvolt = <687500>;
|
|
};
|
|
opp28 {
|
|
opp-hz = /bits/ 64 <675000000>;
|
|
opp-microvolt = <675000>;
|
|
};
|
|
opp29 {
|
|
opp-hz = /bits/ 64 <655000000>;
|
|
opp-microvolt = <668750>;
|
|
};
|
|
opp30 {
|
|
opp-hz = /bits/ 64 <635000000>;
|
|
opp-microvolt = <662500>;
|
|
};
|
|
opp31 {
|
|
opp-hz = /bits/ 64 <615000000>;
|
|
opp-microvolt = <656250>;
|
|
};
|
|
opp32 {
|
|
opp-hz = /bits/ 64 <596000000>;
|
|
opp-microvolt = <650000>;
|
|
};
|
|
opp33 {
|
|
opp-hz = /bits/ 64 <576000000>;
|
|
opp-microvolt = <643750>;
|
|
};
|
|
opp34 {
|
|
opp-hz = /bits/ 64 <556000000>;
|
|
opp-microvolt = <637500>;
|
|
};
|
|
opp35 {
|
|
opp-hz = /bits/ 64 <537000000>;
|
|
opp-microvolt = <631250>;
|
|
};
|
|
opp36 {
|
|
opp-hz = /bits/ 64 <517000000>;
|
|
opp-microvolt = <625000>;
|
|
};
|
|
opp37 {
|
|
opp-hz = /bits/ 64 <497000000>;
|
|
opp-microvolt = <618750>;
|
|
};
|
|
opp38 {
|
|
opp-hz = /bits/ 64 <478000000>;
|
|
opp-microvolt = <612500>;
|
|
};
|
|
opp39 {
|
|
opp-hz = /bits/ 64 <458000000>;
|
|
opp-microvolt = <606250>;
|
|
};
|
|
opp40 {
|
|
opp-hz = /bits/ 64 <438000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp41 {
|
|
opp-hz = /bits/ 64 <419000000>;
|
|
opp-microvolt = <593750>;
|
|
};
|
|
opp42 {
|
|
opp-hz = /bits/ 64 <399000000>;
|
|
opp-microvolt = <587500>;
|
|
};
|
|
opp43 {
|
|
opp-hz = /bits/ 64 <379000000>;
|
|
opp-microvolt = <581250>;
|
|
};
|
|
opp44 {
|
|
opp-hz = /bits/ 64 <360000000>;
|
|
opp-microvolt = <575000>;
|
|
};
|
|
};
|
|
|
|
gpu-fdvfs@112000 {
|
|
compatible = "mediatek,gpu_fdvfs";
|
|
reg = <0 0x112000 0 0x400>;
|
|
fdvfs-policy-support = <0>;
|
|
gpu-freq-notify-support = <1>;
|
|
};
|
|
|
|
gpu_afs: gpu-afs {
|
|
compatible = "mediatek,gpu_afs";
|
|
afs-policy-support = <1>;
|
|
};
|
|
|
|
gpu_qos: gpu-qos {
|
|
compatible = "mediatek,gpu_qos";
|
|
qos-sysram-support = <1>;
|
|
};
|
|
|
|
gpueb: gpueb@13c00000 {
|
|
compatible = "mediatek,gpueb";
|
|
gpueb-support = <1>;
|
|
gpueb-logger-support = <0>;
|
|
mbox_count = <1>;
|
|
mbox_size = <160>; /* 160 slot * 4 = 640 byte */
|
|
slot_size = <4>; /* 1 slot = 4 bytes */
|
|
ts_mbox = <0>; /* mbox for timersync */
|
|
|
|
/* id, mbox, send_size */
|
|
send_table =
|
|
<0 0 4>,
|
|
<1 0 6>,
|
|
<2 0 3>,
|
|
<3 0 6>,
|
|
<4 0 9>,
|
|
<5 0 4>,
|
|
<6 0 6>,
|
|
<7 0 6>,
|
|
<8 0 1>,
|
|
<9 0 4>,
|
|
<10 0 3>;
|
|
send_name_table =
|
|
"IPI_ID_FAST_DVFS_EVENT",
|
|
"IPI_ID_GPUFREQ",
|
|
"IPI_ID_SLEEP",
|
|
"IPI_ID_TIMER",
|
|
"IPI_ID_FHCTL",
|
|
"IPI_ID_CCF",
|
|
"IPI_ID_GPUMPU",
|
|
"IPI_ID_FAST_DVFS",
|
|
"CH_IPIR_C_MET", /* = IPIS_C_MET on gpueb side */
|
|
"CH_IPIS_C_MET", /* = IPIR_C_MET on gpueb side */
|
|
"IPI_ID_BRISKET";
|
|
|
|
/* id, mbox, recv_size, recv_opt */
|
|
recv_table =
|
|
<0 0 4 0>,
|
|
<1 0 6 1>,
|
|
<2 0 1 0>,
|
|
<3 0 1 0>,
|
|
<4 0 1 1>,
|
|
<5 0 4 1>,
|
|
<6 0 1 1>,
|
|
<7 0 6 1>,
|
|
<8 0 4 0>,
|
|
<9 0 1 1>,
|
|
<10 0 3 1>;
|
|
recv_name_table =
|
|
"IPI_ID_FAST_DVFS_EVENT",
|
|
"IPI_ID_GPUFREQ",
|
|
"IPI_ID_SLEEP",
|
|
"IPI_ID_TIMER",
|
|
"IPI_ID_FHCTL",
|
|
"IPI_ID_CCF",
|
|
"IPI_ID_GPUMPU",
|
|
"IPI_ID_FAST_DVFS",
|
|
"CH_IPIR_C_MET", /* = IPIS_C_MET on gpueb side */
|
|
"CH_IPIS_C_MET", /* = IPIR_C_MET on gpueb side */
|
|
"IPI_ID_BRISKET";
|
|
|
|
reg = <0 0x13c00000 0 0x30000>,
|
|
<0 0x13c2fd1c 0 0x64>,
|
|
<0 0x13c60000 0 0x2000>,
|
|
<0 0x13c2fd80 0 0x280>,
|
|
<0 0x13c62004 0 0x4>,
|
|
<0 0x13c62074 0 0x4>,
|
|
<0 0x13c62000 0 0x4>,
|
|
<0 0x13c62078 0 0x4>;
|
|
reg-names = "gpueb_base",
|
|
"gpueb_gpr_base",
|
|
"gpueb_reg_base",
|
|
"mbox0_base",
|
|
"mbox0_set",
|
|
"mbox0_clr",
|
|
"mbox0_send",
|
|
"mbox0_recv";
|
|
|
|
interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "mbox0";
|
|
|
|
gpueb_mem_table =
|
|
<0 0x4000>, /* 16KB */
|
|
<1 0x180000>; /* 1.5MB */
|
|
|
|
gpueb_mem_name_table =
|
|
"MEM_ID_GPUFREQ", /* GPUFREQ */
|
|
"MEM_ID_LOG"; /* LOGGER */
|
|
};
|
|
|
|
gpufreq: gpufreq {
|
|
compatible = "mediatek,gpufreq";
|
|
reg =
|
|
<0 0x13fbf000 0 0x1000>, /* MFG_TOP_CONFIG */
|
|
<0 0x13fa0000 0 0x400>, /* MFG_PLL */
|
|
<0 0x13fa0400 0 0x400>, /* SENSOR_PLL */
|
|
<0 0x13fa0c00 0 0x400>, /* MFGSC_PLL */
|
|
<0 0x13f90000 0 0x10000>, /* MFG_RPC */
|
|
<0 0x1c001000 0 0x1000>, /* SLEEP */
|
|
<0 0x1021c000 0 0x1000>, /* NTH_EMICFG */
|
|
<0 0x10270000 0 0x1000>, /* NTH_EMICFG_AO_MEM */
|
|
<0 0x10001000 0 0x1000>, /* INFRACFG_AO */
|
|
<0 0x10023000 0 0x1000>, /* INFRA_AO_DEBUG_CTRL */
|
|
<0 0x1002b000 0 0x1000>, /* INFRA_AO1_DEBUG_CTRL */
|
|
<0 0x10042000 0 0x1000>, /* NTH_EMI_AO_DEBUG_CTRL */
|
|
<0 0x11e30000 0 0x1000>, /* EFUSE */
|
|
<0 0x13fb9c00 0 0x100>, /* MFG_CPE_CTRL_MCU */
|
|
<0 0x13fb6000 0 0x1000>, /* MFG_CPE_SENSOR */
|
|
<0 0x13fbc000 0 0x1000>, /* MFG_SECURE */
|
|
<0 0x1000d000 0 0x1000>, /* DRM_DEBUG */
|
|
<0 0x00118800 0 0x2000>; /* SYSRAM_MFG_HISTORY */
|
|
reg-names =
|
|
"mfg_top_config",
|
|
"mfg_pll",
|
|
"sensor_pll",
|
|
"mfgsc_pll",
|
|
"mfg_rpc",
|
|
"sleep",
|
|
"nth_emicfg",
|
|
"nth_emicfg_ao_mem",
|
|
"infracfg_ao",
|
|
"infra_ao_debug_ctrl",
|
|
"infra_ao1_debug_ctrl",
|
|
"nth_emi_ao_debug_ctrl",
|
|
"efuse",
|
|
"mfg_cpe_ctrl_mcu",
|
|
"mfg_cpe_sensor",
|
|
"mfg_secure",
|
|
"drm_debug",
|
|
"sysram_mfg_history";
|
|
vgpu-supply = <&mt6368_vbuck2>;
|
|
vsram-supply = <&mt6363_vsram_apu>;
|
|
gpufreq_wrapper-supply = <&gpufreq_wrapper>;
|
|
};
|
|
|
|
gpufreq_wrapper: gpufreq_wrapper {
|
|
compatible = "mediatek,gpufreq_wrapper";
|
|
gpufreq-version = <2>;
|
|
dual-buck = <0>;
|
|
gpueb-support = <1>;
|
|
gpufreq-bringup = <0>;
|
|
};
|
|
|
|
ged: ged {
|
|
compatible = "mediatek,ged";
|
|
gpufreq-supply = <&gpufreq>;
|
|
};
|
|
|
|
watchdog: watchdog@1c007000 {
|
|
compatible = "mediatek,mt6886-wdt",
|
|
"mediatek,mt6589-wdt",
|
|
"syscon", "simple-mfd";
|
|
reg = <0 0x1c007000 0 0x100>;
|
|
reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x24>;
|
|
mask = <0xf>;
|
|
mode-charger = <BOOT_CHARGER>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_BOOTLOADER>;
|
|
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
|
|
mode-kpoc = <BOOT_KPOC>;
|
|
mode-ddr-reserve = <BOOT_DDR_RSVD>;
|
|
mode-meta = <BOOT_META>;
|
|
mode-rpmbpk = <BOOT_RPMBPK>;
|
|
};
|
|
};
|
|
|
|
gce: gce@1e980000 {
|
|
compatible = "mediatek,mt6886-gce";
|
|
reg = <0 0x1e980000 0 0x4000>;
|
|
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <3>;
|
|
#gce-event-cells = <1>;
|
|
#gce-subsys-cells = <2>;
|
|
default-tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_HW_TRACE_LOCK>;
|
|
append-by-event;
|
|
mboxes = <&gce 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
|
|
<&gce 14 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_HIGHEST>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
mediatek,smi = <&smi_3X1_sub_common>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "gce","gce-timer";
|
|
dma-mask-bit = <35>;
|
|
prebuilt-enable;
|
|
error-irq-no-reboot;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_GCE_D_M>;
|
|
};
|
|
|
|
gce_sec: gce-mbox-sec@1e980000 {
|
|
compatible = "mediatek,mailbox-gce-sec";
|
|
reg = <0 0x1e980000 0 0x4000>;
|
|
#mbox-cells = <3>;
|
|
mboxes = <&gce 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>;
|
|
clock-names = "gce";
|
|
dma-mask-bit = <35>;
|
|
};
|
|
|
|
gce_m: gce@1e990000 {
|
|
compatible = "mediatek,mt6886-gce";
|
|
reg = <0 0x1e990000 0 0x4000>;
|
|
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#mbox-cells = <3>;
|
|
#gce-event-cells = <1>;
|
|
#gce-subsys-cells = <2>;
|
|
default-tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_HW_TRACE_LOCK>;
|
|
append-by-event;
|
|
mboxes = <&gce_m 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
|
|
<&gce_m 14 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_HIGHEST>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
mediatek,smi = <&smi_3X1_sub_common>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "gce","gce-timer";
|
|
dma-mask-bit = <35>;
|
|
prebuilt-enable;
|
|
error-irq-no-reboot;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_GCE_M_M>;
|
|
};
|
|
|
|
gce_m_sec: gce-mbox-m-sec@1e990000 {
|
|
compatible = "mediatek,mailbox-gce-sec";
|
|
reg = <0 0x1e990000 0 0x4000>;
|
|
#mbox-cells = <3>;
|
|
mboxes = <&gce_m 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>;
|
|
clock-names = "gce";
|
|
dma-mask-bit = <35>;
|
|
};
|
|
|
|
cmdq-test {
|
|
compatible = "mediatek,cmdq-test";
|
|
mediatek,gce = <&gce_m>;
|
|
mmsys-config = <&dispsys_config>;
|
|
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
|
|
mboxes = <&gce_m 12 0 CMDQ_THR_PRIO_1>,
|
|
<&gce 12 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_m_sec 9 0 CMDQ_THR_PRIO_1>;
|
|
token-user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
|
|
token-gpr-set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
|
|
};
|
|
|
|
mminfra-imax {
|
|
compatible = "mediatek,mminfra-imax";
|
|
reg = <0 0x14000000 0 0x1000>, /* dispsys */
|
|
<0 0x1f000000 0 0x1000>, /* mdpsys */
|
|
<0 0x14021000 0 0x1000>, /* disp_larb_0 */
|
|
<0 0x14022000 0 0x1000>, /* disp_larb_1 */
|
|
<0 0x1f002000 0 0x1000>; /* mdp_larb_0 */
|
|
disp-larb0-fake-port = <10>;
|
|
disp-larb1-fake-port = <5>;
|
|
mdp-larb0-fake-port = <4>;
|
|
|
|
mm-sram-base = <0x0f000000>;
|
|
|
|
reg-names = "dispsys",
|
|
"mdpsys",
|
|
"disp_larb_0",
|
|
"disp_larb_1",
|
|
"mdp_larb_0";
|
|
|
|
};
|
|
|
|
efuse: efuse@11e30000 {
|
|
compatible = "mediatek,devinfo";
|
|
reg = <0 0x11e30000 0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
efuse_segment: segment@78 {
|
|
reg = <0x78 0x4>;
|
|
};
|
|
|
|
u2_phy_data: u2-phy-data@318 {
|
|
reg = <0x318 0x4>;
|
|
};
|
|
|
|
lvts_e_data1: data1 {
|
|
reg = <0x1a0 0x40>;
|
|
};
|
|
|
|
lvts_e_data2: data2 {
|
|
reg = <0x2f8 0x18>;
|
|
};
|
|
|
|
cpu_version: cpu_data {
|
|
reg = <0x234 0x4>;
|
|
};
|
|
|
|
lkginfo: lkg {
|
|
reg = <0x218 0x18>;
|
|
};
|
|
|
|
csi_efuse0: csidata@0 {
|
|
reg = <0x31c 0x4>;
|
|
};
|
|
|
|
csi_efuse1: csidata@1 {
|
|
reg = <0x320 0x4>;
|
|
};
|
|
|
|
csi_efuse2: csidata@2 {
|
|
reg = <0x324 0x4>;
|
|
};
|
|
|
|
csi_efuse3: csidata@3 {
|
|
reg = <0x328 0x4>;
|
|
};
|
|
};
|
|
|
|
lvts: lvts@10315000 {
|
|
compatible = "mediatek,mt6886-lvts";
|
|
#thermal-sensor-cells = <1>;
|
|
reg = <0 0x10315000 0 0x1000>,
|
|
<0 0x10316000 0 0x1000>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
|
|
nvmem-cell-names = "e_data1","e_data2";
|
|
};
|
|
|
|
ufshci: ufshci@112b0000 {
|
|
compatible = "mediatek,mt8183-ufshci";
|
|
reg = <0 0x112b0000 0 0x2300>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
clocks =
|
|
<&ufscfg_ao_clk CLK_UFSAO_UNIPRO_TX_SYM>,
|
|
<&ufscfg_ao_clk CLK_UFSAO_UNIPRO_RX_SYM0>,
|
|
<&ufscfg_ao_clk CLK_UFSAO_UNIPRO_RX_SYM1>,
|
|
<&ufscfg_ao_clk CLK_UFSAO_UNIPRO_SYS>,
|
|
<&ufscfg_ao_clk CLK_UFSAO_UNIPRO_PHY_SAP>,
|
|
<&ufscfg_pdn_clk CLK_UFSPDN_UFSHCI_UFS>,
|
|
<&ufscfg_pdn_clk CLK_UFSPDN_UFSHCI_AES>,
|
|
<&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>,
|
|
<&topckgen_clk CLK_TOP_U_SEL>;
|
|
clock-names =
|
|
"unipro_tx_sym",
|
|
"unipro_rx_sym0",
|
|
"unipro_rx_sym1",
|
|
"unipro_sys",
|
|
"unipro_phy_sap",
|
|
"ufshci_ufs",
|
|
"ufshcd_aes",
|
|
"ufs_fde",
|
|
"ufs";
|
|
freq-table-hz =
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_UFS0_SHUTDOWN>;
|
|
|
|
/*
|
|
* In the same SoC,
|
|
* vcc-supply is for one kind of UFS and
|
|
* vcc_ufs2-supply & vcc_ufs3-supply are for ufs2/ufs3 co-load setting
|
|
*/
|
|
vcc-supply = <&mt6363_vemc>;
|
|
#if 0
|
|
vccq-supply = <&mt6363_vufs12>;
|
|
#endif
|
|
/*
|
|
* For LP5, mt6363_vufs used as IO_Power, so we can't power off it.
|
|
* For LP4, ufs2 use ext. buck as 1.8V and w`e can't control it.
|
|
*/
|
|
|
|
resets =
|
|
<&ufsaocfg_rst 0>,
|
|
<&ufspdncfg_rst 0>,
|
|
<&ufspdncfg_rst 1>;
|
|
|
|
reset-names =
|
|
"unipro_rst",
|
|
"crypto_rst",
|
|
"hci_rst";
|
|
|
|
bootmode = <&chosen>;
|
|
|
|
mediatek,ufs-qos;
|
|
};
|
|
|
|
mtkfb: mtkfb@0 {
|
|
compatible = "mediatek,mtkfb";
|
|
};
|
|
|
|
mgm: mgm {
|
|
compatible = "arm,physical-memory-group-manager";
|
|
};
|
|
|
|
mminfra-debug@0x1e827000 {
|
|
compatible = "mediatek,mminfra-debug";
|
|
reg = <0 0x1e827000 0 0x90>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_INFRA>;
|
|
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mminfra-bkrs = <1>;
|
|
init-clk-on;
|
|
clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
|
|
<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
|
|
clock-names = "clk0", "clk1", "clk2", "clk3";
|
|
};
|
|
|
|
|
|
disp_pwm: disp_pwm0@1100e000 {
|
|
compatible = "mediatek,disp_pwm0",
|
|
"mediatek,mt6886-disp-pwm";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&pericfg_ao_clk CLK_PERAO_DISP_PWM0>,
|
|
<&topckgen_clk CLK_TOP_DISP_PWM_SEL>,
|
|
<&topckgen_clk CLK_TOP_OSC_D4>;
|
|
clock-names = "main", "mm", "pwm_src";
|
|
};
|
|
|
|
dispsys_config: dispsys_config@14000000 {
|
|
compatible = "mediatek,mt6886-disp";
|
|
mediatek,mml = <&mmlsys_config>;
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL1_2L_0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE0>,
|
|
<&smi_larb1 M4U_PORT_L1_DISP_FAKE1>;
|
|
#clock-cells = <1>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_DISP>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>,
|
|
<&dispsys_config_clk CLK_MM_APB_BUS>,
|
|
<&dispsys_config_clk CLK_MM_SIG_EMI>,
|
|
<&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC3>,
|
|
<&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC3>;
|
|
clock-num = <5>;
|
|
operating-points-v2 = <&opp_table_disp>;
|
|
mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
interconnects = <&mmqos SLAVE_LARB(35) &mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "disp_hrt_qos";
|
|
pre-define-bw = <0xffffffff>, <0>, <0>, <0>;
|
|
/* define threads, see mt6886-gce.h */
|
|
mediatek,mailbox-gce = <&gce>;
|
|
mboxes = <&gce 0 0 CMDQ_THR_PRIO_4>,
|
|
<&gce 1 0 CMDQ_THR_PRIO_4>,
|
|
<&gce 2 0 CMDQ_THR_PRIO_4>,
|
|
<&gce 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
<&gce 5 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
<&gce 4 0 CMDQ_THR_PRIO_4>,
|
|
<&gce 6 0 CMDQ_THR_PRIO_3>;
|
|
// <&gce_sec 8 0 CMDQ_THR_PRIO_3>,
|
|
// <&gce_sec 9 0 CMDQ_THR_PRIO_3>,
|
|
// <&gce_sec 9 0 CMDQ_THR_PRIO_3>;
|
|
|
|
gce-client-names = "CLIENT_CFG0",
|
|
"CLIENT_CFG1",
|
|
"CLIENT_CFG2",
|
|
"CLIENT_TRIG_LOOP0",
|
|
"CLIENT_TRIG_LOOP1",
|
|
"CLIENT_SUB_CFG0",
|
|
"CLIENT_DSI_CFG0";
|
|
// "CLIENT_SEC_CFG0",
|
|
// "CLIENT_SEC_CFG1",
|
|
// "CLIENT_SEC_CFG2";
|
|
|
|
/* define subsys, see mt6886-gce.h */
|
|
gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
|
|
<&gce 0x14010000 SUBSYS_1401XXXX>,
|
|
<&gce 0x14020000 SUBSYS_1402XXXX>;
|
|
|
|
/* define subsys, see mt6886-gce.h */
|
|
gce-event-names = "disp_mutex0_eof",
|
|
//"disp_mutex1_eof",
|
|
"disp_token_stream_dirty0",
|
|
"disp_wait_dsi0_te",
|
|
"disp_token_stream_eof0",
|
|
"disp_dsi0_eof",
|
|
"disp_token_esd_eof0",
|
|
"disp_rdma0_eof0",
|
|
"disp_wdma0_eof0",
|
|
"disp_token_stream_block0",
|
|
"disp_token_cabc_eof0",
|
|
"disp_wdma0_eof2",
|
|
//"disp_wait_dp_intf0_te",
|
|
//"disp_dp_intf0_eof",
|
|
"disp_mutex2_eof",
|
|
"disp_wdma1_eof2",
|
|
"disp_dsi0_sof0",
|
|
"disp_token_vfp_period0",
|
|
"disp_token_disp_va_start0",
|
|
"disp_token_disp_va_end0",
|
|
"disp_token_disp_va_start2",
|
|
"disp_token_disp_va_end2",
|
|
"disp_gpio_te1";
|
|
|
|
gce-events = <&gce CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_0>,
|
|
// <&gce CMDQ_EVENT_MMSYS_DP_INTF0_FRAME_DONE>,
|
|
<&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY>,
|
|
<&gce CMDQ_EVENT_MMSYS_DSI0_TE_ENG_EVENT>,
|
|
<&gce CMDQ_SYNC_TOKEN_STREAM_EOF>,
|
|
<&gce CMDQ_EVENT_MMSYS_DSI0_FRAME_DONE>,
|
|
<&gce CMDQ_SYNC_TOKEN_ESD_EOF>,
|
|
<&gce CMDQ_EVENT_MMSYS_DISP_RDMA0_FRAME_DONE>,
|
|
<&gce CMDQ_EVENT_MMSYS_DISP_WDMA0_FRAME_DONE>,
|
|
<&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK>,
|
|
<&gce CMDQ_SYNC_TOKEN_CABC_EOF>,
|
|
<&gce CMDQ_EVENT_MMSYS_DISP_WDMA0_FRAME_DONE>,
|
|
// <&gce CMDQ_EVENT_MMSYS_DISP_DP_INTF0_SOF>,
|
|
// <&gce CMDQ_EVENT_MMSYS_DP_INTF0_FRAME_DONE>,
|
|
<&gce CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_2>,
|
|
<&gce CMDQ_EVENT_MMSYS_DISP_WDMA1_FRAME_DONE>,
|
|
<&gce CMDQ_EVENT_MMSYS_DISP_DSI0_SOF>,
|
|
<&gce CMDQ_SYNC_TOKEN_VFP_PERIOD>,
|
|
<&gce CMDQ_SYNC_TOKEN_DISP_VA_START>,
|
|
<&gce CMDQ_SYNC_TOKEN_DISP_VA_END>,
|
|
<&gce CMDQ_SYNC_TOKEN_DISP_VA_START>,
|
|
<&gce CMDQ_SYNC_TOKEN_DISP_VA_END>,
|
|
<&gce CMDQ_EVENT_GCE_EVENT_DSI1_TE_I>;
|
|
|
|
helper-name = "MTK_DRM_OPT_STAGE",
|
|
"MTK_DRM_OPT_USE_CMDQ",
|
|
"MTK_DRM_OPT_USE_M4U",
|
|
"MTK_DRM_OPT_MMQOS_SUPPORT",
|
|
"MTK_DRM_OPT_MMDVFS_SUPPORT",
|
|
"MTK_DRM_OPT_SODI_SUPPORT",
|
|
"MTK_DRM_OPT_IDLE_MGR",
|
|
"MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE",
|
|
"MTK_DRM_OPT_IDLEMGR_BY_REPAINT",
|
|
"MTK_DRM_OPT_IDLEMGR_ENTER_ULPS",
|
|
"MTK_DRM_OPT_IDLEMGR_KEEP_LP11",
|
|
"MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING",
|
|
"MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ",
|
|
"MTK_DRM_OPT_MET_LOG",
|
|
"MTK_DRM_OPT_USE_PQ",
|
|
"MTK_DRM_OPT_ESD_CHECK_RECOVERY",
|
|
"MTK_DRM_OPT_ESD_CHECK_SWITCH",
|
|
"MTK_DRM_OPT_PRESENT_FENCE",
|
|
"MTK_DRM_OPT_RDMA_UNDERFLOW_AEE",
|
|
"MTK_DRM_OPT_DSI_UNDERRUN_AEE",
|
|
"MTK_DRM_OPT_HRT",
|
|
"MTK_DRM_OPT_HRT_MODE",
|
|
"MTK_DRM_OPT_DELAYED_TRIGGER",
|
|
"MTK_DRM_OPT_OVL_EXT_LAYER",
|
|
"MTK_DRM_OPT_AOD",
|
|
"MTK_DRM_OPT_RPO",
|
|
"MTK_DRM_OPT_DUAL_PIPE",
|
|
"MTK_DRM_OPT_DC_BY_HRT",
|
|
"MTK_DRM_OPT_OVL_WCG",
|
|
"MTK_DRM_OPT_OVL_SBCH",
|
|
"MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK",
|
|
"MTK_DRM_OPT_MET",
|
|
"MTK_DRM_OPT_REG_PARSER_RAW_DUMP",
|
|
"MTK_DRM_OPT_VP_PQ",
|
|
"MTK_DRM_OPT_GAME_PQ",
|
|
"MTK_DRM_OPT_MMPATH",
|
|
"MTK_DRM_OPT_HBM",
|
|
"MTK_DRM_OPT_VDS_PATH_SWITCH",
|
|
"MTK_DRM_OPT_LAYER_REC",
|
|
"MTK_DRM_OPT_CLEAR_LAYER",
|
|
"MTK_DRM_OPT_LFR",
|
|
"MTK_DRM_OPT_SF_PF",
|
|
"MTK_DRM_OPT_DYN_MIPI_CHANGE",
|
|
"MTK_DRM_OPT_PRIM_DUAL_PIPE",
|
|
"MTK_DRM_OPT_MSYNC2_0",
|
|
"MTK_DRM_OPT_MML_PRIMARY",
|
|
"MTK_DRM_OPT_MML_SUPPORT_CMD_MODE",
|
|
"MTK_DRM_OPT_MML_PQ",
|
|
"MTK_DRM_OPT_MML_IR",
|
|
"MTK_DRM_OPT_DUAL_TE",
|
|
"MTK_DRM_OPT_VIRTUAL_DISP",
|
|
"MTK_DRM_OPT_RES_SWITCH",
|
|
"MTK_DRM_OPT_OVL_BW_MONITOR",
|
|
"MTK_DRM_OPT_GPU_CACHE",
|
|
"MTK_DRM_OPT_SPHRT";
|
|
|
|
helper-value = <0>, /*MTK_DRM_OPT_STAGE*/
|
|
<1>, /*MTK_DRM_OPT_USE_CMDQ*/
|
|
<1>, /*MTK_DRM_OPT_USE_M4U*/
|
|
<1>, /*MTK_DRM_OPT_MMQOS_SUPPORT*/
|
|
<1>, /*MTK_DRM_OPT_MMDVFS_SUPPORT*/
|
|
<1>, /*MTK_DRM_OPT_SODI_SUPPORT*/
|
|
<1>, /*MTK_DRM_OPT_IDLE_MGR*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/
|
|
<1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/
|
|
<1>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/
|
|
<1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/
|
|
<0>, /*MTK_DRM_OPT_MET_LOG*/
|
|
<1>, /*MTK_DRM_OPT_USE_PQ*/
|
|
<1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/
|
|
<1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/
|
|
<1>, /*MTK_DRM_OPT_PRESENT_FENCE*/
|
|
<0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/
|
|
<0>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/
|
|
<1>, /*MTK_DRM_OPT_HRT*/
|
|
<1>, /*MTK_DRM_OPT_HRT_MODE*/
|
|
<0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/
|
|
<1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/
|
|
<1>, /*MTK_DRM_OPT_AOD*/
|
|
<1>, /*MTK_DRM_OPT_RPO*/
|
|
<0>, /*MTK_DRM_OPT_DUAL_PIPE*/
|
|
<0>, /*MTK_DRM_OPT_DC_BY_HRT*/
|
|
<0>, /*MTK_DRM_OPT_OVL_WCG*/
|
|
<0>, /*MTK_DRM_OPT_OVL_SBCH*/
|
|
<1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/
|
|
<0>, /*MTK_DRM_OPT_MET*/
|
|
<0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/
|
|
<0>, /*MTK_DRM_OPT_VP_PQ*/
|
|
<0>, /*MTK_DRM_OPT_GAME_PQ*/
|
|
<0>, /*MTK_DRM_OPT_MMPATH*/
|
|
<0>, /*MTK_DRM_OPT_HBM*/
|
|
<0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/
|
|
<0>, /*MTK_DRM_OPT_LAYER_REC*/
|
|
<0>, /*MTK_DRM_OPT_CLEAR_LAYER*/
|
|
<1>, /*MTK_DRM_OPT_LFR*/
|
|
<0>, /*MTK_DRM_OPT_SF_PF*/
|
|
<1>, /*MTK_DRM_OPT_DYN_MIPI_CHANGE*/
|
|
<0>, /*MTK_DRM_OPT_PRIM_DUAL_PIPE*/
|
|
<1>, /*MTK_DRM_OPT_MSYNC2_0*/
|
|
<1>, /*MTK_DRM_OPT_MML_PRIMARY*/
|
|
<1>, /*MTK_DRM_OPT_MML_SUPPORT_CMD_MODE*/
|
|
<1>, /*MTK_DRM_OPT_MML_PQ*/
|
|
<1>, /*MTK_DRM_OPT_MML_IR*/
|
|
<0>, /*MTK_DRM_OPT_DUAL_TE*/
|
|
<1>, /*MTK_DRM_OPT_VIRTUAL_DISP*/
|
|
<0>, /*MTK_DRM_OPT_RES_SWITCH*/
|
|
<0>, /*MTK_DRM_OPT_OVL_BW_MONITOR*/
|
|
<0>, /*MTK_DRM_OPT_GPU_CACHE*/
|
|
<1>; /*MTK_DRM_OPT_SPHRT*/
|
|
};
|
|
|
|
disp_mutex0: disp_mutex@14001000 {
|
|
compatible = "mediatek,disp_mutex0",
|
|
"mediatek,mt6886-disp-mutex";
|
|
mediatek,mml = <&mmlsys_config>;
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>;
|
|
};
|
|
|
|
disp_ovl0: disp_ovl@14002000 {
|
|
compatible = "mediatek,disp_ovl0",
|
|
"mediatek,mt6886-disp-ovl";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_OVL0>;
|
|
mediatek,larb = <&smi_larb0 M4U_PORT_L0_DISP_OVL0_0>,
|
|
<&smi_larb1 M4U_PORT_L1_DISP_OVL0_1>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL0_0>,
|
|
<&disp_iommu M4U_PORT_L0_DISP_OVL0_HDR>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "DDP_COMPONENT_OVL0_qos",
|
|
"DDP_COMPONENT_OVL0_qos_other",
|
|
"DDP_COMPONENT_OVL0_fbdc_qos",
|
|
"DDP_COMPONENT_OVL0_hrt_qos",
|
|
"DDP_COMPONENT_OVL0_hrt_qos_other";
|
|
};
|
|
|
|
disp_ovl0_2l: disp_ovl@14003000 {
|
|
compatible = "mediatek,disp_ovl0_2l",
|
|
"mediatek,mt6886-disp-ovl";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_OVL0_2L>;
|
|
mediatek,larb = <&smi_larb0 M4U_PORT_L0_DISP_OVL0_2L_0>,
|
|
<&smi_larb1 M4U_PORT_L1_DISP_OVL0_2L_1>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_0>,
|
|
<&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_HDR>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "DDP_COMPONENT_OVL0_2L_qos",
|
|
"DDP_COMPONENT_OVL0_2L_qos_other",
|
|
"DDP_COMPONENT_OVL0_2L_fbdc_qos",
|
|
"DDP_COMPONENT_OVL0_2L_hrt_qos",
|
|
"DDP_COMPONENT_OVL0_2L_hrt_qos_other";
|
|
};
|
|
|
|
disp_ovl1_2l: disp_ovl@14004000 {
|
|
compatible = "mediatek,disp_ovl1_2l",
|
|
"mediatek,mt6886-disp-ovl";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_OVL1_2L>;
|
|
mediatek,larb = <&smi_larb0 M4U_PORT_L0_DISP_OVL1_2L_0>,
|
|
<&smi_larb1 M4U_PORT_L1_DISP_OVL1_2L_1>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL1_2L_0>,
|
|
<&disp_iommu M4U_PORT_L0_DISP_OVL1_2L_HDR>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "DDP_COMPONENT_OVL1_2L_qos",
|
|
"DDP_COMPONENT_OVL1_2L_qos_other",
|
|
"DDP_COMPONENT_OVL1_2L_fbdc_qos",
|
|
"DDP_COMPONENT_OVL1_2L_hrt_qos",
|
|
"DDP_COMPONENT_OVL1_2L_hrt_qos_other";
|
|
};
|
|
|
|
disp_rsz0: disp_rsz0@14005000 {
|
|
compatible = "mediatek,disp_rsz0",
|
|
"mediatek,mt6886-disp-rsz";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_RSZ0>;
|
|
};
|
|
|
|
inlinerot0: inlinerot@14020000 {
|
|
compatible = "mediatek,inlinerot",
|
|
"mediatek,mt6886-disp-inlinerotate";
|
|
clocks = <&dispsys_config_clk CLK_MM_INLINEROT0>;
|
|
reg = <0 0x14020000 0 0x1000>;
|
|
};
|
|
|
|
disp_y2r0: disp-y2r0@14000000 {
|
|
compatible = "mediatek,disp_y2r0",
|
|
"mediatek,mt6886-disp-y2r";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_Y2R0>;
|
|
};
|
|
|
|
disp_dlo_async3: disp-dlo-async3@14000000 {
|
|
compatible = "mediatek,disp_dlo_async3",
|
|
"mediatek,mt6886-disp-dlo-async3";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC3>;
|
|
};
|
|
|
|
disp_dli_async3: disp-dli-async3@14000000 {
|
|
compatible = "mediatek,disp_dli_async3",
|
|
"mediatek,mt6886-disp-dli-async3";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC3>;
|
|
};
|
|
|
|
disp_rdma0: disp_rdma@14006000 {
|
|
compatible = "mediatek,disp_rdma0",
|
|
"mediatek,mt6886-disp-rdma";
|
|
reg = <0 0x14006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_RDMA0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_RDMA0>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "DDP_COMPONENT_RDMA0_qos",
|
|
"DDP_COMPONENT_RDMA0_hrt_qos";
|
|
};
|
|
|
|
disp_c3d0: disp_c3d@14008000 {
|
|
compatible = "mediatek,disp_c3d0",
|
|
"mediatek,mt6886-disp-c3d";
|
|
reg = <0 0x14008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_C3D0>;
|
|
};
|
|
|
|
disp_color0: disp_color@14009000 {
|
|
compatible = "mediatek,disp_color0",
|
|
"mediatek,mt6886-disp-color";
|
|
reg = <0 0x14009000 0 0x1000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_COLOR0>;
|
|
|
|
};
|
|
|
|
disp_ccorr0_0: disp_ccorr@1400a000 {
|
|
compatible = "mediatek,disp_ccorr0",
|
|
"mediatek,mt6886-disp-ccorr";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_CCORR0>;
|
|
ccorr_bit = <13>;
|
|
ccorr_num_per_pipe = <2>;
|
|
ccorr_linear_per_pipe = <0x10>;
|
|
};
|
|
|
|
disp_ccorr0_1: disp_ccorr@1400b000 {
|
|
compatible = "mediatek,disp_ccorr0",
|
|
"mediatek,mt6886-disp-ccorr";
|
|
reg = <0 0x1400b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_CCORR1>;
|
|
};
|
|
|
|
disp_aal0: disp_aal@1400d000 {
|
|
compatible = "mediatek,disp_aal0",
|
|
"mediatek,mt6886-disp-aal";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_AAL0>;
|
|
mtk_aal_support = <1>;
|
|
mtk_dre30_support = <0>;
|
|
};
|
|
|
|
disp_gamma0: disp_gamma@1400e000 {
|
|
compatible = "mediatek,disp_gamma0",
|
|
"mediatek,mt6886-disp-gamma";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_GAMMA0>;
|
|
gamma_data_mode = <2>;
|
|
color_protect_red = <0>;
|
|
color_protect_green = <0>;
|
|
color_protect_blue = <0>;
|
|
color_protect_white = <0>;
|
|
color_protect_black = <0>;
|
|
color_protect_lsb = <0>;
|
|
};
|
|
|
|
disp_postmask0: disp_postmask0@1400f000 {
|
|
compatible = "mediatek,disp_postmask0",
|
|
"mediatek,mt6886-disp-postmask";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_POSTMASK0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK>;
|
|
};
|
|
|
|
|
|
disp_dither0: disp_dither@14010000 {
|
|
compatible = "mediatek,disp_dither0",
|
|
"mediatek,mt6886-disp-dither";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_DITHER0>;
|
|
pure_clr_det = <0>;
|
|
pure_clr_num = <7>;
|
|
pure_clr_rgb = <255 0 0
|
|
0 255 0
|
|
0 0 255
|
|
255 255 0
|
|
255 0 255
|
|
0 255 255
|
|
255 255 255>;
|
|
};
|
|
|
|
disp_chist0: disp_chist@14011000 {
|
|
compatible = "mediatek,disp_chist0",
|
|
"mediatek,mt6886-disp-chist";
|
|
reg = <0 0x14011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_CHIST0>;
|
|
};
|
|
|
|
disp_cm0: disp_cm@14013000 {
|
|
compatible = "mediatek,disp_cm0",
|
|
"mediatek,mt6886-disp-cm";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_CM0>;
|
|
};
|
|
|
|
disp_spr0: disp_spr@14014000 {
|
|
compatible = "mediatek,disp_spr0",
|
|
"mediatek,mt6886-disp-spr";
|
|
reg = <0 0x14014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_SPR0>;
|
|
};
|
|
|
|
disp_dsc0_wrap: disp_dsc_wrap@14015000 {
|
|
compatible = "mediatek,disp_dsc_wrap",
|
|
"mediatek,mt6886-disp-dsc";
|
|
reg = <0 0x14015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>;
|
|
};
|
|
|
|
dsi0: dsi@14017000 {
|
|
compatible = "mediatek,dsi0",
|
|
"mediatek,mt6886-dsi";
|
|
reg = <0 0x14017000 0 0x1000>;
|
|
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_FMM_DISP_DSI0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_DSI0>,
|
|
<&mipi_tx_config0>;
|
|
clock-names = "engine",
|
|
"digital",
|
|
"hs";
|
|
phys = <&mipi_tx_config0>;
|
|
phy-names = "dphy";
|
|
};
|
|
|
|
dsi_te: dsi_te {
|
|
compatible = "mediatek, dsi_te-eint";
|
|
status = "disabled";
|
|
};
|
|
|
|
disp_wdma0: disp_wdma0@14018000 {
|
|
compatible = "mediatek,disp_wdma0",
|
|
"mediatek,mt6886-disp-wdma";
|
|
reg = <0 0x14018000 0 0x1000>;
|
|
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_WDMA0>;
|
|
fifo-size-1plane = <905>;
|
|
fifo-size-uv-1plane = <29>;
|
|
fifo-size-2plane = <599>;
|
|
fifo-size-uv-2plane = <299>;
|
|
fifo-size-3plane = <596>;
|
|
fifo-size-uv-3plane = <148>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_WDMA0>;
|
|
};
|
|
|
|
disp_ufbc_wdma0@14019000 {
|
|
compatible = "mediatek,disp_ufbc_wdma0";
|
|
reg = <0 0x14019000 0 0x1000>;
|
|
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_UFBC_WDMA0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L0_DISP_UFBC_WDMA0>;
|
|
};
|
|
|
|
disp_rdma1: disp_rdma1@1401c000 {
|
|
compatible = "mediatek,disp_rdma1";
|
|
reg = <0 0x1401c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_RDMA1>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
mediatek,smi-id = <1>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L1_DISP_RDMA1>;
|
|
};
|
|
|
|
disp_wdma1: disp_wdma1@1401f000 {
|
|
compatible = "mediatek,disp_wdma1",
|
|
"mediatek,mt6886-disp-wdma";
|
|
reg = <0 0x1401f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&dispsys_config_clk CLK_MM_DISP_WDMA1>;
|
|
fifo-size-1plane = <464>;
|
|
fifo-size-uv-1plane = <29>;
|
|
fifo-size-2plane = <305>;
|
|
fifo-size-uv-2plane = <152>;
|
|
fifo-size-3plane = <303>;
|
|
fifo-size-uv-3plane = <74>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
mediatek,smi-id = <1>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L1_DISP_WDMA1>;
|
|
};
|
|
|
|
mipi_tx_config0: mipi_tx_config@11e60000 {
|
|
compatible = "mediatek,mipi_tx_config0",
|
|
"mediatek,mt6886-mipi-tx";
|
|
reg = <0 0x11e60000 0 0x1000>;
|
|
clocks = <&clk26m>;
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
clock-output-names = "mipi_tx0_pll";
|
|
};
|
|
|
|
srclken_rc: srclken-rc@1c00d000 {
|
|
compatible = "mediatek,srclken-rc";
|
|
reg = <0 0x1c00d000 0 0x100>,
|
|
<0 0x1c00d100 0 0x700>;
|
|
mediatek,subsys-ctl = "suspend", "md1", "md2",
|
|
"md3", "rf", "mmwave",
|
|
"gps", "bt", "wf",
|
|
"mcu", "coant", "nfc",
|
|
"spm", "ufs";
|
|
suspend-ctl = "XO_BBCK1";
|
|
md1-ctl = "XO_RFCK2A";
|
|
gps-ctl = "XO_RFCK2A";
|
|
mcu-ctl = "XO_BBCK2";
|
|
nfc-ctl = "XO_BBCK4";
|
|
ufs-ctl = "XO_BBCK3";
|
|
|
|
mediatek,srclken-rc-broadcast;
|
|
mediatek,enable;
|
|
};
|
|
|
|
mdpsys_config_clk: syscon@1f000000 {
|
|
compatible = "mediatek,mt6886-mdpsys", "syscon";
|
|
reg = <0 0x1f000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mdpsys_config: mdpsys-config@1f000000 {
|
|
compatible = "mediatek,mdpsys_config";
|
|
reg = <0 0x1f000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_APB_BUS>;
|
|
clock-names = "MDP_APB_BUS";
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
iommus = <&disp_iommu M4U_PORT_L2_MDP_RDMA0>,
|
|
<&disp_iommu M4U_PORT_L2_MDP_RDMA1>,
|
|
<&disp_iommu M4U_PORT_L2_MDP_WROT0>,
|
|
<&disp_iommu M4U_PORT_L2_MDP_WROT1>;
|
|
dma-mask-bit = <34>;
|
|
};
|
|
|
|
mdp: mdp@1f000000 {
|
|
compatible = "mediatek,mdp";
|
|
reg = <0 0x1f000000 0 0x1000>;
|
|
thread-count = <24>;
|
|
mboxes = <&gce 20 0 CMDQ_THR_PRIO_1>,
|
|
<&gce 21 0 CMDQ_THR_PRIO_1>;
|
|
mmsys-config = <&mdpsys_config>;
|
|
mm-mutex = <&mdp_mutex0>;
|
|
mdp-rdma1 = <&mdp_rdma1>;
|
|
mdp-rsz1 = <&mdp_rsz1>;
|
|
mdp-wrot1 = <&mdp_wrot1>;
|
|
mdp-tdshp1 = <&mdp_tdshp1>;
|
|
mdp-aal1 = <&mdp_aal1>;
|
|
mdp-color1 = <&mdp_color1>;
|
|
mdp-hdr1 = <&mdp_hdr1>;
|
|
mediatek,larb = <&smi_larb2>;
|
|
mdp-rdma1-sof = <CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SOF>;
|
|
mdp-fg1-sof = <CMDQ_EVENT_MDPSYS0_MDP_FG1_SOF>;
|
|
mdp-wrot1-sof = <CMDQ_EVENT_MDPSYS0_MDP_WROT1_SOF>;
|
|
mdp-tdshp1-sof = <CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_SOF>;
|
|
mdp-wrot1-write-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_WROT1_FRAME_DONE>;
|
|
mdp-tdshp1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_FRAME_DONE>;
|
|
mdp-rsz1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_RSZ1_FRAME_DONE>;
|
|
mdp-rdma1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_RDMA1_FRAME_DONE>;
|
|
mdp-hdr1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_HDR1_FRAME_DONE>;
|
|
mdp-fg1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_FG1_FRAME_DONE>;
|
|
mdp-color1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_COLOR1_FRAME_DONE>;
|
|
mdp-aal1-frame-done = <CMDQ_EVENT_MDPSYS0_MDP_AAL1_FRAME_DONE>;
|
|
stream-done-0 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_0>;
|
|
stream-done-1 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_1>;
|
|
stream-done-2 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_2>;
|
|
stream-done-3 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_3>;
|
|
stream-done-4 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_4>;
|
|
stream-done-5 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_5>;
|
|
stream-done-6 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_6>;
|
|
stream-done-7 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_7>;
|
|
stream-done-8 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_8>;
|
|
stream-done-9 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_9>;
|
|
stream-done-10 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_10>;
|
|
stream-done-11 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_11>;
|
|
stream-done-12 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_12>;
|
|
stream-done-13 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_13>;
|
|
stream-done-14 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_14>;
|
|
stream-done-15 = <CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_15>;
|
|
mdp-wrot1-rst-done = <CMDQ_EVENT_MDPSYS0_MDP_WROT1_SW_RST_DONE_ENG_EVENT>;
|
|
mdp-rdma1-rst-done = <CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names =
|
|
"mdp_rdma1",
|
|
"mdp_wrot1";
|
|
mdp-opp = <&opp_table_mdp>;
|
|
operating-points-v2 = <&opp_table_mdp>;
|
|
mdp-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
dre30-hist-sram-start = /bits/ 16 <1536>;
|
|
};
|
|
|
|
mdp_mutex0: mdp-mutex0@1f001000 {
|
|
compatible = "mediatek,mdp_mutex0";
|
|
reg = <0 0x1f001000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_MUTEX0>;
|
|
clock-names = "MDP_MUTEX0";
|
|
};
|
|
|
|
mdp_rdma1: mdp-rdma1@1f004000 {
|
|
compatible = "mediatek,mdp_rdma1";
|
|
reg = <0 0x1f004000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_RDMA1>;
|
|
clock-names = "MDP_RDMA1";
|
|
};
|
|
|
|
mdp_rsz1: mdp-rsz1@1f00a000 {
|
|
compatible = "mediatek,mdp_rsz1";
|
|
reg = <0 0x1f00a000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_RSZ1>;
|
|
clock-names = "MDP_RSZ1";
|
|
};
|
|
|
|
mdp_hdr1: mdp-hdr1@1f006000 {
|
|
compatible = "mediatek,mdp_hdr1",
|
|
"mediatek,mdp-tuning-mdp_hdr0";
|
|
reg = <0 0x1f006000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_HDR1>;
|
|
clock-names = "MDP_HDR1";
|
|
};
|
|
|
|
mdp_aal1: mdp-aal1@1f008000 {
|
|
compatible = "mediatek,mdp_aal1",
|
|
"mediatek,mdp-tuning-mdp_aal0";
|
|
reg = <0 0x1f008000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_AAL1>;
|
|
clock-names = "MDP_AAL1";
|
|
};
|
|
|
|
mdp_tdshp1: mdp-tdshp1@1f00c000 {
|
|
compatible = "mediatek,mdp_tdshp1",
|
|
"mediatek,mdp-tuning-mdp_tdshp0";
|
|
reg = <0 0x1f00c000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_TDSHP1>;
|
|
clock-names = "MDP_TDSHP1";
|
|
};
|
|
|
|
mdp_color1: mdp-color1@1f00e000 {
|
|
compatible = "mediatek,mdp_color1",
|
|
"mediatek,mdp-tuning-mdp_color0";
|
|
reg = <0 0x1f00e000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_COLOR1>;
|
|
clock-names = "MDP_COLOR1";
|
|
};
|
|
|
|
mdp_wrot1: mdp-wrot1@1f010000 {
|
|
compatible = "mediatek,mdp_wrot1";
|
|
reg = <0 0x1f010000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_WROT1>;
|
|
clock-names = "MDP_WROT1";
|
|
};
|
|
|
|
mml-test {
|
|
compatible = "mediatek,mml-test";
|
|
mediatek,mml = <&mmlsys_config>;
|
|
};
|
|
|
|
mml-ait {
|
|
compatible = "mediatek,mml-ait";
|
|
mediatek,mml = <&mmlsys_config>;
|
|
};
|
|
|
|
mmlsys_config: mmlsys-config@1f000000 {
|
|
compatible = "mediatek,mt6886-mml";
|
|
reg = <0 0x1f000000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_APB_BUS>,
|
|
<&mdpsys_config_clk CLK_MDP_DL_RELAY0>,
|
|
<&mdpsys_config_clk CLK_MDP_DLO_ASYNC0>;
|
|
clock-names = "apb_bus", "dli0", "dlo0";
|
|
/* as mml device */
|
|
comp-count = <MML_ENGINE_TOTAL>;
|
|
topology = "mt6886";
|
|
/* as mmlsys */
|
|
mboxes = <&gce 16 400 CMDQ_THR_PRIO_1>,
|
|
<&gce 17 500 CMDQ_THR_PRIO_1>,
|
|
<&gce 18 400 CMDQ_THR_PRIO_1>,
|
|
<&gce 19 500 CMDQ_THR_PRIO_1>;
|
|
comp-ids = <MML_MMLSYS>,
|
|
<MML_DLI0>,
|
|
<MML_DLO0>,
|
|
<MML_DLI0_SEL>,
|
|
<MML_DLO0_SOUT>;
|
|
comp-types = <MML_CT_SYS>,
|
|
<MML_CT_DL_IN>,
|
|
<MML_CT_DL_OUT>,
|
|
<MML_CT_PATH>,
|
|
<MML_CT_PATH>;
|
|
comp-names = "mmlsys",
|
|
"dli0",
|
|
"dlo0",
|
|
"dli0-sel",
|
|
"dlo0-sout";
|
|
mmlsys-clock-names = "apb_bus";
|
|
dli0-clock-names = "dli0";
|
|
dlo0-clock-names = "dlo0";
|
|
dli0-sel-clock-names = "rdma0";
|
|
/* as sys component */
|
|
mux-pins = /bits/ 16 <
|
|
0 MML_RDMA0 MML_DLI0_SEL MML_MUX_SLIN DLI0_SEL_IN
|
|
1 MML_DLI0 MML_DLI0_SEL MML_MUX_SLIN DLI0_SEL_IN
|
|
0 MML_DLI0_SEL MML_HDR0 MML_MUX_MOUT RDMA0_MOUT_EN
|
|
1 MML_DLI0_SEL MML_DLO0_SOUT MML_MUX_MOUT RDMA0_MOUT_EN
|
|
0 MML_DLI0_SEL MML_HDR0 MML_MUX_SLIN PQ0_SEL_IN
|
|
0 MML_DLI0_SEL MML_DLO0_SOUT MML_MUX_SLIN WROT0_SEL_IN
|
|
1 MML_COLOR0 MML_DLO0_SOUT MML_MUX_SLIN WROT0_SEL_IN
|
|
0 MML_COLOR0 MML_DLO0_SOUT MML_MUX_SOUT PQ0_SOUT_SEL
|
|
0 MML_DLO0_SOUT MML_WROT0 MML_MUX_SOUT DLO0_SOUT_SEL
|
|
1 MML_DLO0_SOUT MML_DLO0 MML_MUX_SOUT DLO0_SOUT_SEL
|
|
0 MML_RDMA0 MML_WROT0 MML_MUX_MOUT BYP0_MOUT_EN
|
|
2 MML_RDMA0 MML_DLI0_SEL MML_MUX_MOUT BYP0_MOUT_EN
|
|
0 MML_RDMA0 MML_WROT0 MML_MUX_SLIN BYP0_SEL_IN
|
|
1 MML_DLO0_SOUT MML_WROT0 MML_MUX_SLIN BYP0_SEL_IN>;
|
|
/* as dl component */
|
|
dli0-dl-relay = /bits/ 16 <DL_IN_RELAY0_SIZE>;
|
|
dlo0-dl-relay = /bits/ 16 <DL_OUT_RELAY0_SIZE>;
|
|
dbg-reg-names = "CG_CON0", "CG_SET0", "CG_CLR0",
|
|
"SW0_RST_B", "MOUT_RST", "EVENT_GCED_EN",
|
|
"IN_LINE_READY_SEL", "SMI_LARB_GREQ", "BYPASS_MUX_SHADOW",
|
|
"DLI0_SEL_IN",
|
|
"RDMA0_MOUT_EN",
|
|
"PQ0_SEL_IN",
|
|
"WROT0_SEL_IN",
|
|
"PQ0_SOUT_SEL",
|
|
"DLO0_SOUT_SEL",
|
|
"BYP0_MOUT_EN",
|
|
"BYP0_SEL_IN",
|
|
"MOUT_MASK0", "MOUT_MASK1", "MOUT_MASK2",
|
|
"DL_IN_RELAY0_SIZE",
|
|
"DL_OUT_RELAY0_SIZE",
|
|
"DLI_ASYNC0_STATUS0", "DLI_ASYNC0_STATUS1",
|
|
"DLI_ASYNC1_STATUS0", "DLI_ASYNC1_STATUS1",
|
|
"DLO_ASYNC0_STATUS0", "DLO_ASYNC0_STATUS1",
|
|
"DLO_ASYNC1_STATUS0", "DLO_ASYNC1_STATUS1",
|
|
"DL_VALID0", "DL_VALID1", "DL_READY0", "DL_READY1",
|
|
"RDMA0_AIDSEL", "WROT0_AIDSEL", "AID_SEL_MODE";
|
|
dbg-reg-offsets = <CG_CON0>, <CG_SET0>, <CG_CLR0>,
|
|
<SW0_RST_B>, <MOUT_RST>, <EVENT_GCED_EN>,
|
|
<IN_LINE_READY_SEL>, <SMI_LARB_GREQ>, <BYPASS_MUX_SHADOW>,
|
|
<DLI0_SEL_IN>,
|
|
<RDMA0_MOUT_EN>,
|
|
<PQ0_SEL_IN>,
|
|
<WROT0_SEL_IN>,
|
|
<PQ0_SOUT_SEL>,
|
|
<DLO0_SOUT_SEL>,
|
|
<BYP0_MOUT_EN>,
|
|
<BYP0_SEL_IN>,
|
|
<MOUT_MASK0>, <MOUT_MASK1>, <MOUT_MASK2>,
|
|
<DL_IN_RELAY0_SIZE>,
|
|
<DL_OUT_RELAY0_SIZE>,
|
|
<DLI_ASYNC0_STATUS0>, <DLI_ASYNC0_STATUS1>,
|
|
<DLI_ASYNC1_STATUS0>, <DLI_ASYNC1_STATUS1>,
|
|
<DLO_ASYNC0_STATUS0>, <DLO_ASYNC0_STATUS1>,
|
|
<DLO_ASYNC1_STATUS0>, <DLO_ASYNC1_STATUS1>,
|
|
<DL_VALID0>, <DL_VALID1>, <DL_READY0>, <DL_READY1>,
|
|
<RDMA0_AIDSEL>, <WROT0_AIDSEL>, <AID_SEL_MODE>;
|
|
operating-points-v2 = <&opp_table_mdp>;
|
|
mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
mediatek,larb = <&smi_larb2 MTK_M4U_TO_PORT(M4U_PORT_L2_DISP_FAKE0)>;
|
|
aid-sel-engine = <
|
|
MML_RDMA0 RDMA0_AIDSEL
|
|
MML_WROT0 WROT0_AIDSEL>;
|
|
racing-enable;
|
|
event-ir-mml-ready = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_IR_MML_READY>;
|
|
event-ir-disp-ready = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_IR_DISP_READY>;
|
|
event-ir-mml-stop = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_MML_STOP>;
|
|
event-ir-eof =
|
|
/bits/ 16 <CMDQ_EVENT_MMSYS_DISP_RDMA0_TARGET_LINE_ENG_EVENT>;
|
|
event-racing-pipe0 = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_PIPE0>;
|
|
/* sys register offset */
|
|
ready-sel = /bits/ 16 <IN_LINE_READY_SEL>;
|
|
};
|
|
|
|
mml-mutex0@1f001000 {
|
|
compatible = "mediatek,mt6886-mml_mutex";
|
|
reg = <0 0x1f001000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_MUTEX0>;
|
|
clock-names = "mutex0";
|
|
comp-ids = <MML_MUTEX>;
|
|
comp-names = "mutex0";
|
|
mutex-comps = "rdma0", "hdr0", "aal0",
|
|
"rsz0", "tdshp0", "color0",
|
|
"wrot0",
|
|
"dli-async0", "dlo-async0";
|
|
rdma0 = <MML_RDMA0 0 0>;
|
|
hdr0 = <MML_HDR0 0 2>;
|
|
aal0 = <MML_AAL0 0 4>;
|
|
rsz0 = <MML_RSZ0 0 6>;
|
|
tdshp0 = <MML_TDSHP0 0 8>;
|
|
color0 = <MML_COLOR0 0 10>;
|
|
wrot0 = <MML_WROT0 0 12>;
|
|
dli-async0 = <MML_DLI0 0 16>;
|
|
dlo-async0 = <MML_DLO0 0 18>;
|
|
/* rdma use mutex0, dli0 use mutex2 */
|
|
mutex-ids = <MML_RDMA0 0 MML_DLI0 2>;
|
|
};
|
|
|
|
mml-rdma0@1f003000 {
|
|
compatible = "mediatek,mt6886-mml_rdma";
|
|
reg = <0 0x1f003000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_RDMA0>;
|
|
clock-names = "rdma0";
|
|
mediatek,larb = <&smi_larb2 MTK_M4U_TO_PORT(M4U_PORT_L2_MDP_RDMA0)>;
|
|
comp-ids = <MML_RDMA0>;
|
|
comp-names = "rdma0";
|
|
event-sw-rst-done = /bits/ 16
|
|
<CMDQ_EVENT_MDPSYS0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT>;
|
|
event-frame-done = /bits/ 16
|
|
<CMDQ_EVENT_MDPSYS0_MDP_RDMA0_FRAME_DONE>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L2_MDP_RDMA0>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "mml_dma";
|
|
};
|
|
|
|
mml_hdr0: mml-hdr0@1f005000 {
|
|
compatible = "mediatek,mt6886-mml_hdr",
|
|
"mediatek,mml-tuning-mml_hdr0";
|
|
reg = <0 0x1f005000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_HDR0>;
|
|
clock-names = "hdr0";
|
|
comp-ids = <MML_HDR0>;
|
|
comp-names = "hdr0";
|
|
};
|
|
|
|
mml_aal0: mml-aal0@1f007000 {
|
|
compatible = "mediatek,mt6886-mml_aal",
|
|
"mediatek,mml-tuning-mml_aal0";
|
|
reg = <0 0x1f007000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_AAL0>;
|
|
clock-names = "aal0";
|
|
comp-ids = <MML_AAL0>;
|
|
comp-names = "aal0";
|
|
sram-curve-base = /bits/ 32 <4608>;
|
|
sram-his-base = /bits/ 32 <1536>;
|
|
};
|
|
|
|
mml_rsz0: mml-rsz0@1f009000 {
|
|
compatible = "mediatek,mt6886-mml_rsz";
|
|
reg = <0 0x1f009000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_RSZ0>;
|
|
clock-names = "rsz0";
|
|
comp-ids = <MML_RSZ0>;
|
|
comp-names = "rsz0";
|
|
};
|
|
|
|
mml_tdshp0: mml-tdshp0@1f00b000 {
|
|
compatible = "mediatek,mt6886-mml_tdshp",
|
|
"mediatek,mml-tuning-mml_tdshp0";
|
|
reg = <0 0x1f00b000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_TDSHP0>;
|
|
clock-names = "tdshp0";
|
|
comp-ids = <MML_TDSHP0>;
|
|
comp-names = "tdshp0";
|
|
};
|
|
|
|
mml_color0: mml-color0@1f00d000 {
|
|
compatible = "mediatek,mt6886-mml_color",
|
|
"mediatek,mml-tuning-mml_color0";
|
|
reg = <0 0x1f00d000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_COLOR0>;
|
|
clock-names = "color0";
|
|
comp-ids = <MML_COLOR0>;
|
|
comp-names = "color0";
|
|
};
|
|
|
|
mml_wrot0: mml-wrot0@1f00f000 {
|
|
compatible = "mediatek,mt6886-mml_wrot";
|
|
reg = <0 0x1f00f000 0 0x1000>;
|
|
clocks = <&mdpsys_config_clk CLK_MDP_WROT0>;
|
|
clock-names = "wrot0";
|
|
mediatek,larb = <&smi_larb2 MTK_M4U_TO_PORT(M4U_PORT_L2_MDP_WROT0)>;
|
|
comp-ids = <MML_WROT0>;
|
|
comp-names = "wrot0";
|
|
event-sw-rst-done = /bits/ 16
|
|
<CMDQ_EVENT_MDPSYS0_MDP_WROT0_SW_RST_DONE_ENG_EVENT>;
|
|
event-frame-done = /bits/ 16
|
|
<CMDQ_EVENT_MDPSYS0_MDP_WROT0_FRAME_DONE>;
|
|
event-bufa = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_BUFA>;
|
|
event-bufb = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_BUFB>;
|
|
event-buf-next = /bits/ 16 <CMDQ_SYNC_TOKEN_MML_BUF_NEXT>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L2_MDP_WROT0>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "mml_dma";
|
|
inlinerot = <&inlinerot0>;
|
|
};
|
|
};
|
|
|
|
connfem: connfem {
|
|
compatible = "mediatek,mt6886-connfem";
|
|
};
|
|
|
|
swpm: swpm {
|
|
compatible = "mediatek,mtk-swpm";
|
|
pmu-boundary-num = <0>;
|
|
pmu-dsu-support = <1>;
|
|
pmu-dsu-type = <10>;
|
|
};
|
|
|
|
gps: gps@18c00000 {
|
|
compatible = "mediatek,mt6886-gps";
|
|
reg = <0 0x18000000 0 0x100000>,
|
|
<0 0x18c00000 0 0x100000>,
|
|
<0 0x1c000000 0 0x4>,
|
|
<0 0x1c805028 0 0x4>,
|
|
<0 0x1c805030 0 0x4>,
|
|
<0 0x1c8050cc 0 0x28>;
|
|
reg-names = "conn_infra_base", "conn_gps_base",
|
|
"status_dummy_cr", "tia2_gps_on", "tia2_gps_rc_sel",
|
|
"tia2_gps_debug";
|
|
interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
emi-connac-ver = <2>;
|
|
emi-addr = <0>;
|
|
emi-size = <0x100000>;
|
|
emi-alignment = <0x100000>;
|
|
emi-max-addr = <0xc0000000>;
|
|
b13b14-status-addr = <0x1c000008>;
|
|
};
|
|
|
|
scp_clk_ctrl: scp-clk-ctrl@1c721000 {
|
|
compatible = "mediatek,scp-clk-ctrl", "syscon";
|
|
reg = <0 0x1c721000 0 0x1000>; /* scp clk */
|
|
};
|
|
|
|
scp-dvfs {
|
|
compatible = "mediatek,scp-dvfs";
|
|
/* scp-dvfs-disable; */
|
|
|
|
clocks = <&vlp_cksys_clk CLK_VLP_CK_SCP_VLP_SEL>,
|
|
<&topckgen_clk CLK_TOP_TCK_26M_MX9>,
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 624M */
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D3>,
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D3>, /* 728M */
|
|
<&topckgen_clk CLK_TOP_UNIVPLL_D6>,
|
|
<&topckgen_clk CLK_TOP_APLL1>,
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D4>,
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D7>,
|
|
<&topckgen_clk CLK_TOP_OSC_D10>;
|
|
|
|
clock-names = "clk_mux",
|
|
"clk_pll_0",
|
|
"clk_pll_1",
|
|
"clk_pll_2",
|
|
"clk_pll_3",
|
|
"clk_pll_4",
|
|
"clk_pll_5",
|
|
"clk_pll_6",
|
|
"clk_pll_7",
|
|
"clk_pll_8";
|
|
|
|
scp-cores = <1>;
|
|
vlp-support;
|
|
vlpck-support;
|
|
|
|
dvfs-opp =
|
|
/* vlp vsram dvfsrc_opp spm_vcore freq mux resource */
|
|
< 750000 750000 0xff 0xfff 175 0 0x0>,
|
|
< 750000 750000 0xff 0xfff 233 0 0x0>,
|
|
< 750000 750000 0xff 0xfff 350 0 0x0>,
|
|
< 750000 750000 0xff 0xfff 700 0 0x0>;
|
|
|
|
do-ulposc-cali;
|
|
fmeter-clksys = <&vlp_cksys_clk>;
|
|
ulposc-clksys = <&vlp_cksys_clk>;
|
|
scp-clk-ctrl = <&scp_clk_ctrl>;
|
|
scp-clk-hw-ver = "v1";
|
|
ulposc-cali-ver = "v2";
|
|
ulposc-cali-num = <1>;
|
|
ulposc-cali-target = <700>;
|
|
ulposc-cali-config =
|
|
/* con0 con1 con2 */
|
|
<0x071292c0 0x2400 0xc>;
|
|
clk-dbg-ver = "v2";
|
|
ccf-fmeter-support;
|
|
scp-dvfs-flag = "enable"; /* enable/disable */
|
|
};
|
|
|
|
vcu: vcu@16000000 {
|
|
compatible = "mediatek-vcu";
|
|
mediatek,vcuid = <0>;
|
|
mediatek,vcuname = "vcu";
|
|
mediatek,vcp-support = <3>;
|
|
reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */
|
|
<0 0x17020000 0 0x10000>, /* VENC_BASE */
|
|
<0 0x17820000 0 0x10000>, /* VENC_C1_BASE */
|
|
<0 0x14006000 0 0x1000>, /* DISP_WDMA0_BASE */
|
|
<0 0x14106000 0 0x1000>; /* DISP_WDMA1_BASE */
|
|
iommus = <&disp_iommu M4U_PORT_L4_HW_VDEC_MC_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_UFO_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PP_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_TILE_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_VLD_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_VLD2_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_MINI_MDP_R0_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_MINI_MDP_W0_EXT>;
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
//dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
};
|
|
|
|
vcu-iommu-venc {
|
|
compatible = "mediatek,vcu-io-venc";
|
|
mediatek,vcuid = <0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L7_VENC_RCPU>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REC>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_BSDNA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SV_COMV>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_RD_COMV>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA_LITE>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SUB_W_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA_LITE>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_CUR_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_CUR_CHROMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REF_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REF_CHROMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SUB_R_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_WDMA>;
|
|
};
|
|
|
|
vdec@16000000 {
|
|
compatible = "mediatek,mt6886-vcodec-dec";
|
|
mediatek,platform = "platform:mt6886";
|
|
mediatek,ipm = <1>;
|
|
reg = <0 0x16000000 0 0x1000>, /* VDEC_BASE */
|
|
<0 0x1602f000 0 0x1000>, /* VDEC_SYS */
|
|
<0 0x16020000 0 0x1000>, /* VDEC_VLD */
|
|
<0 0x16021000 0 0x1000>, /* VDEC_MC */
|
|
<0 0x16023000 0 0x1000>, /* VDEC_MV */
|
|
<0 0x16025000 0 0x4000>; /* VDEC_MISC */
|
|
reg-names =
|
|
"VDEC_BASE",
|
|
"VDEC_SYS",
|
|
"VDEC_VLD",
|
|
"VDEC_MC",
|
|
"VDEC_MV",
|
|
"VDEC_MISC";
|
|
iommus = <&disp_iommu M4U_PORT_L4_HW_VDEC_MC_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_UFO_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PP_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_TILE_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_VLD_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_VLD2_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_MINI_MDP_R0_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_MINI_MDP_W0_EXT>;
|
|
m4u-ports =
|
|
<M4U_PORT_L4_HW_VDEC_MC_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_UFO_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_PP_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_TILE_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_VLD_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_VLD2_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>,
|
|
<M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
|
|
<M4U_PORT_L36_VIDEO_uP>,
|
|
<M4U_PORT_L36_VIDEO_uP>;
|
|
m4u-port-names =
|
|
"M4U_PORT_VDEC_MC",
|
|
"M4U_PORT_VDEC_UFO",
|
|
"M4U_PORT_VDEC_PP",
|
|
"M4U_PORT_VDEC_PRED_RD",
|
|
"M4U_PORT_VDEC_PRED_WR",
|
|
"M4U_PORT_VDEC_PPWRAP",
|
|
"M4U_PORT_VDEC_TILE",
|
|
"M4U_PORT_VDEC_VLD",
|
|
"M4U_PORT_VDEC_VLD2",
|
|
"M4U_PORT_VDEC_AVC_MV",
|
|
"M4U_PORT_VDEC_RG_CTRL_DMA",
|
|
"M4U_PORT_VDEC_UFO_ENC",
|
|
"M4U_PORT_VDEC_VIDEO_UP_SEC",
|
|
"M4U_PORT_VDEC_VIDEO_UP_NOR";
|
|
mediatek,larbs = <&smi_larb4>;
|
|
interrupts = <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
//dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VDE0>;
|
|
mediatek,vcu = <&vcu>;
|
|
clocks =
|
|
<&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>;
|
|
clock-names =
|
|
"CORE_MT_CG_VDEC0";
|
|
mediatek,clock-parents = <4 3>;
|
|
operating-points-v2 = <&opp_table_vdec>;
|
|
//mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_MC_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PP_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_RD_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_WR_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PPWRAP_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_TILE_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD2_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_AVC_MV_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos SLAVE_LARB(4) &mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "path_vdec_mc", "path_vdec_ufo",
|
|
"path_vdec_pp", "path_vdec_pred_rd",
|
|
"path_vdec_pred_wr", "path_vdec_ppwrap",
|
|
"path_vdec_tile", "path_vdec_vld",
|
|
"path_vdec_vld2", "path_vdec_avc_mv",
|
|
"path_vdec_rg_ctrl_dma","path_vdec_ufo_c",
|
|
"path_larb4";
|
|
interconnect-num = <13>;
|
|
throughput-op-rate-thresh = <120>;
|
|
throughput-min = <218000000>;
|
|
throughput-normal-max = <416000000>;
|
|
profile-duration = <60 2000>;
|
|
profile-target = <15 25 30 50 60 90 120 150 180 240 480>;
|
|
max-op-rate-table =
|
|
<877088845 921600 30 3686400 30 8847360 15>, /* MPEG4 */
|
|
<826757197 921600 30 3686400 30 8847360 15>, /* MPEG1 */
|
|
<843534413 921600 30 3686400 30 8847360 15>, /* MPEG2 */
|
|
<859189832 921600 30 3686400 30 8847360 15>, /* H.263 */
|
|
<875967048 921600 30 3686400 30 8847360 15>, /* H.264 */
|
|
<826496577 921600 30 3686400 30 8847360 15>, /* H.264 */
|
|
<1129727304 921600 30 3686400 30 8847360 15>, /* HEVC */
|
|
<892744264 921600 30 3686400 30 8847360 15>, /* H.265 */
|
|
<1179206984 262144 550 2097152 550 8847360 550>, /* HEIF */
|
|
<808996950 921600 30 3686400 30 8847360 15>, /* VP8 */
|
|
<809062486 921600 30 3686400 30 8847360 15>, /* VP9 */
|
|
<808539713 921600 30 3686400 30 8847360 15>; /* AV1 */
|
|
throughput-table =
|
|
<877088845 0 478 478>, /* MPEG4 */
|
|
<826757197 0 417 417>, /* MPEG1 */
|
|
<843534413 0 417 417>, /* MPEG2 */
|
|
<859189832 0 478 478>, /* H.263 */
|
|
<875967048 0 298 298>, /* H.264 */
|
|
<826496577 0 298 298>, /* H.264 */
|
|
<1129727304 0 298 298>, /* HEVC */
|
|
<892744264 0 298 298>, /* H.265 */
|
|
<1179206984 0 550 550>, /* HEIF */
|
|
<808996950 0 417 417>, /* VP8 */
|
|
<809062486 0 298 298>, /* VP9 */
|
|
<808539713 0 298 298>; /* AV1 */
|
|
bandwidth-table =
|
|
<3 840>,
|
|
<3 70>,
|
|
<2 550>,
|
|
<5 10>,
|
|
<5 10>,
|
|
<5 0>,
|
|
<5 0>,
|
|
<0 26>,
|
|
<0 26>,
|
|
<5 26>,
|
|
<5 20>,
|
|
<3 66>,
|
|
<6 4>;
|
|
};
|
|
vdec_fmt: vdec-fmt@16080000 {
|
|
compatible = "mediatek-vdec-fmt";
|
|
mediatek,fmtname = "vdec-fmt";
|
|
reg = <0 0x16080000 0 0x1000>, /* mini_mdp0_rdma */
|
|
<0 0x16081000 0 0x1000>, /* mini_mdp0_wdma */
|
|
<0 0x1602f000 0 0x10000>; /* VDEC_SOC_GCON */
|
|
clocks = <&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_MINI_MDP_EN>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VFMT>;
|
|
clock-names = "MT_CG_VDEC", "MT_CG_MINI_MDP", "mmdvfs_clk";
|
|
mediatek,fmt-gce-th-num = <1>; /* FMT GCE HW THREAD NUM */
|
|
mediatek,fmt-qos-threshold = <30>; /* FMT MIN MMQoS BW Threshold*/
|
|
mboxes = <&gce_m 6 2000 CMDQ_THR_PRIO_1>,
|
|
<&gce_m 7 2000 CMDQ_THR_PRIO_1>;
|
|
/* rdma0_sw_rst_done_eng_event */
|
|
rdma0-sw-rst-done-eng =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP0_RDMA_SW_RST_DONE_ENG_EVENT>;
|
|
/* rdma0_tile_done */
|
|
rdma0-tile-done =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP0_RDMA_TILE_DONE>;
|
|
/* wdma0_sw_rst_done_eng_event */
|
|
wdma0-sw-rst-done-eng =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP0_WDMA_SW_RST_DONE_ENG_EVENT>;
|
|
/* wdma0_tile_done */
|
|
wdma0-tile-done =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP0_WDMA_TILE_DONE>;
|
|
/* rdma1_sw_rst_done_eng_event */
|
|
rdma1-sw-rst-done-eng =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP1_RDMA_SW_RST_DONE_ENG_EVENT>;
|
|
/* rdma1_tile_done */
|
|
rdma1-tile-done =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP1_RDMA_TILE_DONE>;
|
|
/* wdma1_sw_rst_done_eng_event */
|
|
wdma1-sw-rst-done-eng =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP1_WDMA_SW_RST_DONE_ENG_EVENT>;
|
|
/* wdma1_tile_done */
|
|
wdma1-tile-done =
|
|
/bits/ 16 <CMDQ_EVENT_VDEC_FMT_MDP1_WDMA_TILE_DONE>;
|
|
gce-gpr = <GCE_GPR_R10>;
|
|
iommus = <&disp_iommu M4U_PORT_L4_HW_MINI_MDP_R0_EXT>,
|
|
<&disp_iommu M4U_PORT_L4_HW_MINI_MDP_W0_EXT>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VDE0>;
|
|
mediatek,larbs = <&smi_larb4>;
|
|
operating-points-v2 = <&opp_table_vdec>;
|
|
interconnects =
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_MINI_MDP_R0_EXT) &mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_MINI_MDP_W0_EXT) &mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "path_mini_mdp_r0",
|
|
"path_mini_mdp_w0";
|
|
m4u-ports =
|
|
<M4U_PORT_L4_HW_MINI_MDP_R0_EXT>,
|
|
<M4U_PORT_L4_HW_MINI_MDP_W0_EXT>;
|
|
};
|
|
|
|
venc@17000000 {
|
|
compatible = "mediatek,mt6886-vcodec-enc";
|
|
mediatek,platform = "platform:mt6886";
|
|
mediatek,ipm = <1>;
|
|
reg = <0 0x17020000 0 0x6000>,
|
|
<0 0x17820000 0 0x20000>;
|
|
reg-names =
|
|
"VENC_SYS",
|
|
"VENC_C1_SYS";
|
|
iommus = <&disp_iommu M4U_PORT_L7_VENC_RCPU>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REC>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_BSDNA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SV_COMV>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_RD_COMV>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA_LITE>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SUB_W_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA_LITE>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_CUR_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_CUR_CHROMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REF_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_REF_CHROMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_SUB_R_LUMA>,
|
|
<&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_WDMA>;
|
|
mediatek,larbs = <&smi_larb7>;
|
|
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
//dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VEN0>;
|
|
mediatek,vcu = <&vcu>;
|
|
clocks = <&venc_gcon_clk CLK_VEN_CKE1_VENC>,
|
|
<&mmdvfs_clk CLK_MMDVFS_VENC>;
|
|
clock-names =
|
|
"MT_CG_VENC0",
|
|
"mmdvfs_clk";
|
|
port-arg-num = <3>;
|
|
|
|
port-def =<0 M4U_PORT_L7_VENC_RCPU 0>,
|
|
<0 M4U_PORT_L7_VENC_REC 0>,
|
|
<0 M4U_PORT_L7_VENC_BSDNA 0>,
|
|
<0 M4U_PORT_L7_VENC_SV_COMV 0>,
|
|
<0 M4U_PORT_L7_VENC_RD_COMV 0>,
|
|
<0 M4U_PORT_L7_VENC_NBM_RDMA 1>,
|
|
<0 M4U_PORT_L7_VENC_NBM_RDMA_LITE 1>,
|
|
<0 M4U_PORT_L7_JPGENC_Y_RDMA 0>,
|
|
<0 M4U_PORT_L7_JPGENC_C_RDMA 0>,
|
|
<0 M4U_PORT_L7_JPGENC_Q_TABLE 0>,
|
|
<0 M4U_PORT_L7_VENC_SUB_W_LUMA 0>,
|
|
<0 M4U_PORT_L7_VENC_FCS_NBM_RDMA 1>,
|
|
<0 M4U_PORT_L7_JPGENC_BSDMA 0>,
|
|
<0 M4U_PORT_L7_VENC_NBM_WDMA 1>,
|
|
<0 M4U_PORT_L7_VENC_NBM_WDMA_LITE 1>,
|
|
<0 M4U_PORT_L7_VENC_CUR_LUMA 0>,
|
|
<0 M4U_PORT_L7_VENC_CUR_CHROMA 0>,
|
|
<0 M4U_PORT_L7_VENC_REF_LUMA 0>,
|
|
<0 M4U_PORT_L7_VENC_REF_CHROMA 0>,
|
|
<0 M4U_PORT_L7_VENC_SUB_R_LUMA 0>,
|
|
<0 M4U_PORT_L7_VENC_FCS_NBM_WDMA 1>;
|
|
|
|
operating-points-v2 = <&opp_table_venc>;
|
|
mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDNA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA_LITE)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_W_LUMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_RDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA_LITE)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_R_LUMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_WDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos SLAVE_LARB(7) &mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "path_venc_rcpu", "path_venc_rec",
|
|
"path_venc_bsdma", "path_venc_sv_comv",
|
|
"path_venc_rd_comv", "path_venc_nbm_rdma",
|
|
"path_venc_nbm_rdma_lite", "path_venc_sub_w_luma",
|
|
"path_venc_fcs_nbm_rdma", "path_venc_nbm_wdma",
|
|
"path_venc_nbm_wdma_lite", "path_venc_cur_luma",
|
|
"path_venc_cur_chroma", "path_venc_ref_luma",
|
|
"path_venc_ref_chroma", "path_venc_sub_r_luma",
|
|
"path_venc_fcs_nbm_wdma", "path_larb7";
|
|
interconnect-num = <18>;
|
|
throughput-op-rate-thresh = <120>;
|
|
throughput-min = <250000000>;
|
|
throughput-normal-max = <458000000>;
|
|
throughput-config-offset = <2>;
|
|
throughput-table =
|
|
<875967048 3 974 974>, /* H.264 */
|
|
<875967048 4 860 860>, /* H.264 */
|
|
<875967048 5 766 766>,
|
|
<875967048 12 413 413>,
|
|
<875967048 13 2880 2880>,
|
|
<875967048 14 2545 2545>,
|
|
<1129727304 2 860 860>, /* HEVC low power*/
|
|
<1129727304 4 766 766>,
|
|
<1129727304 9 413 413>,
|
|
<1129727304 10 1016 1016>, /* HEVC high quality*/
|
|
<1129727304 11 932 932>,
|
|
<1129727304 16 435 435>,
|
|
<892744264 2 860 860>, /* H265 low power*/
|
|
<892744264 4 766 766>,
|
|
<892744264 9 413 413>,
|
|
<892744264 10 1016 1016>, /* H265 high quality*/
|
|
<892744264 11 932 932>,
|
|
<892744264 16 435 435>,
|
|
<1179206984 2 3500 3500>, /* HEIF*/
|
|
<1179206984 4 1720 1720>,
|
|
<1179206984 9 926 926>;
|
|
config-table =
|
|
/* H264 */
|
|
<875967048 108000 3 13>, /* 720p30 */
|
|
<875967048 244800 4 14>, /* 1080p30 */
|
|
<875967048 489600 5 14>, /* 1080p60 */
|
|
<875967048 4294967295 12 14>, /* 4K30 */
|
|
/* HEVC*/
|
|
<1129727304 244800 2 10>, /* 1080p30 */
|
|
<1129727304 489600 4 11>, /* 1080p60 */
|
|
<1129727304 4294967295 9 16>, /* 4K30 */
|
|
/* H265 */
|
|
<892744264 244800 2 10>,
|
|
<892744264 489600 4 11>,
|
|
<892744264 4294967295 9 16>,
|
|
/* HEIF */
|
|
<1179206984 244800 2 10>,
|
|
<1179206984 489600 4 11>,
|
|
<1179206984 4294967295 9 16>;
|
|
bandwidth-table =
|
|
<4 10>,
|
|
<3 282>,
|
|
<0 20>,
|
|
<5 4>,
|
|
<5 16>,
|
|
<5 0>,
|
|
<5 0>,
|
|
<5 47>,
|
|
<5 0>,
|
|
<5 0>,
|
|
<5 0>,
|
|
<1 188>,
|
|
<2 94>,
|
|
<1 188>,
|
|
<2 94>,
|
|
<3 47>,
|
|
<5 0>,
|
|
<6 7>;
|
|
};
|
|
|
|
|
|
jpgenc@17030000 {
|
|
compatible = "mediatek,mtk-jpgenc";
|
|
reg = <0 0x17030000 0 0x10000>;
|
|
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&venc_gcon_clk CLK_VEN_CKE2_JPGENC>;
|
|
clock-names = "jpgenc";
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_VEN0>;
|
|
mediatek,larb = <&smi_larb7>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L7_JPGENC_Y_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_JPGENC_C_RDMA>,
|
|
<&disp_iommu M4U_PORT_L7_JPGENC_Q_TABLE>,
|
|
<&disp_iommu M4U_PORT_L7_JPGENC_BSDMA>;
|
|
interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE)
|
|
&mmqos SLAVE_COMMON(0)>,
|
|
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA)
|
|
&mmqos SLAVE_COMMON(0)>;
|
|
interconnect-names = "path_jpegenc_y_rdma",
|
|
"path_jpegenc_c_rmda",
|
|
"path_jpegenc_q_table",
|
|
"path_jpegenc_bsdma";
|
|
operating-points-v2 = <&opp_table_venc>;
|
|
mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
|
|
};
|
|
|
|
vcp: vcp@1ec00000 {
|
|
compatible = "mediatek,vcp";
|
|
vcp-support = <1>;
|
|
status = "okay";
|
|
reg = <0 0x1ea00000 0 0x40000>, /* tcm */
|
|
<0 0x1ec24000 0 0x1000>, /* cfg */
|
|
<0 0x1ec30000 0 0x1000>, /* cfg core0 */
|
|
<0 0x1ec40000 0 0x1000>, /* cfg core1 */
|
|
<0 0x1ec52000 0 0x1000>, /* bus tracker dbg */
|
|
<0 0x1ec60000 0 0x40000>, /* llc dbg */
|
|
<0 0x1eca5000 0 0x4>, /* cfg_sec dbg */
|
|
<0 0x1e820000 0 0x4>, /* mmu dbg */
|
|
<0 0x1ecfb000 0 0x100>, /* mbox0 base */
|
|
<0 0x1ecfb100 0 0x4>, /* mbox0 set */
|
|
<0 0x1ecfb10c 0 0x4>, /* mbox0 clr */
|
|
<0 0x1eca5020 0 0x4>, /* mbox0 init */
|
|
<0 0x1ecfc000 0 0x100>, /* mbox1 base */
|
|
<0 0x1ecfc100 0 0x4>, /* mbox1 set */
|
|
<0 0x1ecfc10c 0 0x4>, /* mbox1 clr */
|
|
<0 0x1eca5024 0 0x4>, /* mbox1 init */
|
|
<0 0x1ecfd000 0 0x100>, /* mbox2 base */
|
|
<0 0x1ecfd100 0 0x4>, /* mbox2 set */
|
|
<0 0x1ecfd10c 0 0x4>, /* mbox2 clr */
|
|
<0 0x1eca5028 0 0x4>, /* mbox2 init */
|
|
<0 0x1ecfe000 0 0x100>, /* mbox3 base */
|
|
<0 0x1ecfe100 0 0x4>, /* mbox3 set */
|
|
<0 0x1ecfe10c 0 0x4>, /* mbox3 clr */
|
|
<0 0x1eca502c 0 0x4>, /* mbox3 init */
|
|
<0 0x1ecff000 0 0x100>, /* mbox4 base */
|
|
<0 0x1ecff100 0 0x4>, /* mbox4 set */
|
|
<0 0x1ecff10c 0 0x4>, /* mbox4 clr */
|
|
<0 0x1eca5030 0 0x4>; /* mbox4 init */
|
|
|
|
reg-names = "vcp_sram_base",
|
|
"vcp_cfgreg",
|
|
"vcp_cfgreg_core0",
|
|
"vcp_cfgreg_core1",
|
|
"vcp_bus_tracker",
|
|
"vcp_l1creg",
|
|
"vcp_cfgreg_sec",
|
|
"vcp_cfgreg_mmu",
|
|
"mbox0_base",
|
|
"mbox0_set",
|
|
"mbox0_clr",
|
|
"mbox0_init",
|
|
"mbox1_base",
|
|
"mbox1_set",
|
|
"mbox1_clr",
|
|
"mbox1_init",
|
|
"mbox2_base",
|
|
"mbox2_set",
|
|
"mbox2_clr",
|
|
"mbox2_init",
|
|
"mbox3_base",
|
|
"mbox3_set",
|
|
"mbox3_clr",
|
|
"mbox3_init",
|
|
"mbox4_base",
|
|
"mbox4_set",
|
|
"mbox4_clr",
|
|
"mbox4_init";
|
|
|
|
interrupts = <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interrupt-names = "wdt",
|
|
"reserved",
|
|
"mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4";
|
|
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_VIDEO_uP>;
|
|
mediatek,smi = <&mmsram_smi_2x1_sub_comm3 &smi_3X1_sub_common>;
|
|
|
|
core-0 = "enable";
|
|
vcp-sramSize = <0x00040000>;
|
|
vcp-dramSize = <0x00800000>;
|
|
core-nums = <1>; /* core number */
|
|
twohart = <1>; /* two hart arch */
|
|
femter-ck = <8>; /* clk table fmeter f_fmmup_ck */
|
|
mbox-count = <5>;
|
|
vcp-ee-enable = <1>;
|
|
emi-mpu-disable = <0>;
|
|
/* id, mbox, send_size*/
|
|
send-table =
|
|
< 0 0 18>,/* IPI_OUT_VDEC_1 */
|
|
< 2 1 2>,/* IPI_OUT_C_SLEEP_0 */
|
|
< 3 1 1>,/* IPI_OUT_TEST_0 */
|
|
< 9 1 2>,/* IPI_OUT_MMDVFS */
|
|
<11 1 4>,/* IPI_OUT_C_VCP_HWVOTER_DEBUG */
|
|
<12 2 18>,/* IPI_OUT_VENC_0 */
|
|
<14 2 4>,/* IPI_OUT_VCP_MPOOL_0 */
|
|
<16 3 2>,/* IPI_OUT_C_SLEEP_1 */
|
|
<17 3 1>,/* IPI_OUT_TEST_1 */
|
|
<18 3 6>,/* IPI_OUT_LOGGER_CTRL */
|
|
<19 3 2>,/* IPI_OUT_VCPCTL_1 */
|
|
<24 4 4>;/* IPI_OUT_VCP_MPOOL_1 */
|
|
|
|
/* id, mbox, recv_size, recv_opt */
|
|
recv-table =
|
|
< 1 0 18 0>,/* IPI_IN_VDEC_1 */
|
|
< 2 1 1 1>,/* IPI_OUT_C_SLEEP_0 */
|
|
< 4 1 10 0>,/* IPI_IN_VCP_ERROR_INFO_0 */
|
|
< 5 1 1 0>,/* IPI_IN_VCP_READY_0 */
|
|
< 6 1 2 0>,/* IPI_IN_VCP_RAM_DUMP_0 */
|
|
<10 1 2 0>,/* IPI_IN_MMDVFS */
|
|
<11 1 4 1>,/* IPI_OUT_C_VCP_HWVOTER_DEBUG */
|
|
<13 2 18 0>,/* IPI_IN_VENC_0 */
|
|
<15 2 4 0>,/* IPI_IN_VCP_MPOOL_0 */
|
|
<16 3 1 1>,/* IPI_OUT_C_SLEEP_1 */
|
|
<20 3 10 0>,/* IPI_IN_VCP_ERROR_INFO_1 */
|
|
<21 3 6 0>,/* IPI_IN_LOGGER_CTRL */
|
|
<22 3 1 0>,/* IPI_IN_VCP_READY_1 */
|
|
<23 3 2 0>,/* IPI_IN_VCP_RAM_DUMP_1 */
|
|
<25 4 4 0>;/* IPI_IN_VCP_MPOOL_1 */
|
|
|
|
vcp-secure-dump = <1>; /* enable dump via secure world*/
|
|
vcp-secure-dump-size = <0x200000>;
|
|
vcp-secure-dump-offset = <0x600000>;
|
|
vcp-sec-dump-key = "mediatek,me_vcp_reserved";
|
|
|
|
memorydump = <0x40000>, /* l2tcm */
|
|
<0x020000>, /* l1c */
|
|
<0x003f00>, /* regdump */
|
|
<0x000400>, /* trace buffer */
|
|
<0x160000>; /* dram */
|
|
|
|
vcp-mem-tbl = <0 0x78000>, /* VDEC_MEM_ID 480KB */
|
|
<1 0x8000>, /* VENC_MEM_ID 32KB */
|
|
<2 0x180000>, /* LOGGER 1MB 512KB*/
|
|
<3 0x400>, /* VDEC_SET_PROP_MEM_ID 1KB */
|
|
<4 0x400>, /* VENC_SET_PROP_MEM_ID 1KB */
|
|
<5 0x400>, /* VDEC_VCP_LOG_INFO_ID 1KB */
|
|
<6 0x400>, /* VENC_VCP_LOG_INFO_ID 1KB */
|
|
<7 0x100000>, /* GCE_MEM_ID 256*4KB */
|
|
<8 0x1000>, /* MMDVFS_MEM_ID 4KB */
|
|
<9 0x0>; /* secure dump, its size is in secure_dump_size */
|
|
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_MM_PROC_DORMANT>;
|
|
clocks = <&topckgen_clk CLK_TOP_MMUP_SEL>,
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D3>,
|
|
<&topckgen_clk CLK_TOP_TCK_26M_MX9>;
|
|
clock-names = "mmup-sel", "mmup-clk", "mmup-26m";
|
|
};
|
|
|
|
vcp-iommu-vdec {
|
|
vcp-support = <2>;
|
|
compatible = "mediatek,vcp-io-vdec";
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_VIDEO_uP>;
|
|
};
|
|
|
|
vcp-iommu-venc {
|
|
vcp-support = <3>;
|
|
compatible = "mediatek,vcp-io-venc";
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_VIDEO_uP>;
|
|
};
|
|
|
|
vcp-iommu-work {
|
|
vcp-support = <4>;
|
|
compatible = "mediatek,vcp-io-work";
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_VIDEO_uP>;
|
|
};
|
|
|
|
vcp-iommu-sec {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
vcp-support = <7>;
|
|
compatible = "mediatek,vcp-io-sec";
|
|
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
|
|
iommus = <&disp_iommu M4U_PORT_L36_VIDEO_uP>;
|
|
};
|
|
|
|
mcupm: mcupm@0c070000 {
|
|
compatible = "mediatek,mcupm";
|
|
reg = <0 0x0c070000 0 0x50000>,
|
|
<0 0x0c0bfb00 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfba0 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfc40 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfce0 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfd80 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfe20 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bfec0 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>,
|
|
<0 0x0c0bff60 0 0xa0>,
|
|
<0 0x0c072004 0 0x4>,
|
|
<0 0x0c072018 0 0x4>,
|
|
<0 0x0c072000 0 0x4>,
|
|
<0 0x0c072010 0 0x4>;
|
|
reg-names = "mcupm_base",
|
|
"mbox0_base",
|
|
"mbox0_set",
|
|
"mbox0_clr",
|
|
"mbox0_send",
|
|
"mbox0_recv",
|
|
"mbox1_base",
|
|
"mbox1_set",
|
|
"mbox1_clr",
|
|
"mbox1_send",
|
|
"mbox1_recv",
|
|
"mbox2_base",
|
|
"mbox2_set",
|
|
"mbox2_clr",
|
|
"mbox2_send",
|
|
"mbox2_recv",
|
|
"mbox3_base",
|
|
"mbox3_set",
|
|
"mbox3_clr",
|
|
"mbox3_send",
|
|
"mbox3_recv",
|
|
"mbox4_base",
|
|
"mbox4_set",
|
|
"mbox4_clr",
|
|
"mbox4_send",
|
|
"mbox4_recv",
|
|
"mbox5_base",
|
|
"mbox5_set",
|
|
"mbox5_clr",
|
|
"mbox5_send",
|
|
"mbox5_recv",
|
|
"mbox6_base",
|
|
"mbox6_set",
|
|
"mbox6_clr",
|
|
"mbox6_send",
|
|
"mbox6_recv",
|
|
"mbox7_base",
|
|
"mbox7_set",
|
|
"mbox7_clr",
|
|
"mbox7_send",
|
|
"mbox7_recv";
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4",
|
|
"mbox5",
|
|
"mbox6",
|
|
"mbox7";
|
|
};
|
|
|
|
spmtwam: spmtwam@1c006000 {
|
|
compatible = "mediatek,spmtwam";
|
|
reg = <0 0x1c006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
|
|
spm_twam_con = <0xfa0>;
|
|
spm_twam_window_len = <0xfa4>;
|
|
spm_twam_idle_sel = <0xfa8>;
|
|
spm_irq_mask = <0xb4>;
|
|
spm_irq_sta = <0x128>;
|
|
spm_twam_last_sta0 = <0xfac>;
|
|
spm_twam_last_sta1 = <0xfb0>;
|
|
spm_twam_last_sta2 = <0xfb4>;
|
|
spm_twam_last_sta3 = <0xfb8>;
|
|
};
|
|
|
|
sleep@1c001000 {
|
|
compatible = "mediatek,sleep";
|
|
reg = <0 0x1c001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
mtk_lpm: mtk-lpm {
|
|
compatible = "mediatek,mtk-lpm";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
lpm-kernel-suspend = <0>;
|
|
suspend-method = "enable";
|
|
|
|
logger-enable-states = "mcusysoff-l", "mcusysoff-b", "system-mem",
|
|
"system-pll", "system-bus", "system-vcore";
|
|
|
|
irq-remain = <&edge_keypad>,
|
|
<&level_btif_tx &level_btif_rx &level_bt>,
|
|
<&level_usb_host &level_ufshci>,
|
|
<&level_apusys_rv_mbox0 &level_apusys_rv_mbox1>;
|
|
|
|
resource-ctrl = <&bus26m &infra &syspll>,
|
|
<&dram_s0 &dram_s1 &spm_vcore>;
|
|
constraints = <&rc_vcore &rc_bus26m &rc_syspll>,
|
|
<&rc_dram &rc_cpu_buck_ldo>;
|
|
spm-cond = <&spm_cond_cg &spm_cond_pll>;
|
|
cg-shift = <0>; /* cg blocking index */
|
|
pll-shift = <16>; /* pll blocking index */
|
|
|
|
power-gs = <0>;
|
|
|
|
mcusys-cnt-chk = <1>;
|
|
|
|
cpupm_sysram: cpupm-sysram@11b000 {
|
|
compatible = "mediatek,cpupm-sysram";
|
|
reg = <0 0x0011b000 0 0x500>;
|
|
};
|
|
|
|
mcusys_ctrl: mcusys-ctrl@c040000 {
|
|
compatible = "mediatek,mcusys-ctrl";
|
|
reg = <0 0x0c040000 0 0x1000>;
|
|
};
|
|
|
|
lpm_sysram: lpm-sysram@11b500 {
|
|
compatible = "mediatek,lpm-sysram";
|
|
reg = <0 0x0011b500 0 0x300>;
|
|
};
|
|
|
|
|
|
irq-remain-list {
|
|
edge_keypad: edge-keypad {
|
|
target = <&keypad>;
|
|
value = <1 0 0 0x04>;
|
|
};
|
|
level_bt: level-bt {
|
|
target = <&bt>;
|
|
value = <0 0 0 0>;
|
|
};
|
|
level_btif_tx: level-btif-tx {
|
|
target = <&btif>;
|
|
value = <0 1 0 0>;
|
|
};
|
|
level_btif_rx: level-btif-rx {
|
|
target = <&btif>;
|
|
value = <0 2 0 0>;
|
|
};
|
|
level_usb_host: level-usb-host {
|
|
target = <&usb_host>;
|
|
value = <0 0 0 0>;
|
|
};
|
|
level_ufshci: level-ufshci {
|
|
target = <&ufshci>;
|
|
value = <0 0 0 0>;
|
|
};
|
|
level_apusys_rv_mbox0: level-apusys-rv-mbox0 {
|
|
target = <&apusys_rv>;
|
|
value = <0 1 0 0>;
|
|
};
|
|
level_apusys_rv_mbox1: level-apusys-rv-mbox1 {
|
|
target = <&apusys_rv>;
|
|
value = <0 2 0 0>;
|
|
};
|
|
};
|
|
|
|
resource-ctrl-list {
|
|
bus26m: bus26m {
|
|
id = <0x00000000>;
|
|
value = <0>;
|
|
};
|
|
infra: infra {
|
|
id = <0x00000001>;
|
|
value = <0>;
|
|
};
|
|
syspll: syspll {
|
|
id = <0x00000002>;
|
|
value = <0>;
|
|
};
|
|
dram_s0: dram-s0 {
|
|
id = <0x00000003>;
|
|
value = <0>;
|
|
};
|
|
dram_s1: dram-s1 {
|
|
id = <0x00000004>;
|
|
value = <0>;
|
|
};
|
|
spm_vcore: spm-vcore {
|
|
id = <0x00000005>;
|
|
value = <0>;
|
|
};
|
|
|
|
};
|
|
constraint-list {
|
|
rc_vcore: rc-vcore {
|
|
rc-name = "vcore";
|
|
id = <0x00000000>;
|
|
value = <1>;
|
|
cond-info = <1>;
|
|
};
|
|
rc_bus26m: rc-bus26m {
|
|
rc-name = "bus26m";
|
|
id = <0x00000001>;
|
|
value = <1>;
|
|
cond-info = <1>;
|
|
};
|
|
rc_syspll: rc-syspll {
|
|
rc-name = "syspll";
|
|
id = <0x00000002>;
|
|
value = <1>;
|
|
cond-info = <1>;
|
|
};
|
|
rc_dram: rc-dram {
|
|
rc-name = "dram";
|
|
id = <0x00000003>;
|
|
value = <1>;
|
|
cond-info = <1>;
|
|
};
|
|
rc_cpu_buck_ldo: rc-cpu-buck-ldo{
|
|
rc-name = "cpu-buck-ldo";
|
|
id = <0x00000004>;
|
|
value = <1>;
|
|
cond-info = <0>;
|
|
};
|
|
};
|
|
|
|
spm-cond-list {
|
|
spm_cond_cg: spm-cond-cg {
|
|
cg-name = "MTCMOS_0",
|
|
"INFRA_0",
|
|
"INFRA_1",
|
|
"INFRA_2",
|
|
"INFRA_3",
|
|
"INFRA_4",
|
|
"INFRA_5",
|
|
"PERI_0",
|
|
"PERI_1",
|
|
"PERI_2";
|
|
};
|
|
spm_cond_pll: spm-cond-pll {
|
|
pll-name = "UNIVPLL",
|
|
"MFGPLL",
|
|
"MFGSCPLL",
|
|
"SENSONPLL",
|
|
"MSDCPLL",
|
|
"UFSPLL",
|
|
"MMPLL",
|
|
"IMGPLL",
|
|
"ADSPPLL",
|
|
"APLL1",
|
|
"APLL2";
|
|
};
|
|
};
|
|
|
|
power-gs-list {
|
|
};
|
|
};
|
|
|
|
fm: fm@18000000 {
|
|
compatible = "mediatek,fm";
|
|
family-id = <0x6983>;
|
|
host-id = <0x6886>;
|
|
conn-id = <0x0205>;
|
|
interrupts = <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
btif: btif@1100c000 {
|
|
compatible = "mediatek,btif";
|
|
reg = <0 0x1100c000 0 0x100>, /*btif base*/
|
|
<0 0x11300c80 0 0x80>,/*btif tx dma base*/
|
|
<0 0x11300d00 0 0x80>,/*btif rx dma base*/
|
|
<0 0x1103615c 0 0x80>,/*peri2infra axi debug */
|
|
<0 0x11036a84 0 0x80>;/*btif dma idle en addr*/
|
|
/*btif irq, IRQS_Sync ID, btif_irq_b*/
|
|
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
/*btif tx dma irq*/
|
|
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
/*btif rx dma irq*/
|
|
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&pericfg_ao_clk CLK_PERAO_BTIF_B>,
|
|
/*btif clock*/
|
|
<&pericfg_ao_clk CLK_PERAO_APDMA>;
|
|
/*ap dma clock*/
|
|
clock-names = "btifc","apdmac";
|
|
};
|
|
|
|
consys: consys@18000000 {
|
|
compatible = "mediatek,mt6886-consys-atf";
|
|
#thermal-sensor-cells = <0>;
|
|
reg = <0 0x10001000 0 0xee4>, /* 0. 0x1000_1000 infracfg_ao, sz=0xee4 */
|
|
<0 0x10005000 0 0xa7c>, /* 1. 0x1000_5000 GPIO, sz=0xa7c */
|
|
<0 0x11eb0000 0 0xa04>, /* 2. 0x11eb_0000 IOCFG_RT, sz=0xa04 */
|
|
<0 0x18000000 0 0x470>, /* 3. 0x1800_0000 conn_infra_rgu_on, sz=0x470 */
|
|
<0 0x18001000 0 0x658>, /* 4. 0x1800_1000 conn_infra_cfg_on, sz=0x658 */
|
|
<0 0x18003000 0 0x204>, /* 5. 0x1800_3000 conn_wt_slp_ctl_reg, sz=0x204 */
|
|
<0 0x1800e000 0 0x118>, /* 6. 0x1800_e000 conn_infra_bus_cr_on, sz=0x118*/
|
|
<0 0x18011000 0 0x138>, /* 7. 0x1801_1000 conn_infra_cfg, sz=0x138 */
|
|
<0 0x18012000 0 0x98>, /* 8. 0x1801_2000 conn_infra_clkgen_top,sz=0x98 */
|
|
<0 0x18020000 0 0x4c>, /* 9. 0x1802_0000 conn_von_bus_bcrm, sz=0x4c */
|
|
<0 0x18023000 0 0xe28>, /* 10. 0x1802_3000 conn_dbg_ctl, sz=0xe28 */
|
|
<0 0x1803b000 0 0x18>, /* 11. 0x1803_b000 conn_infra_on_bus_bcrm,sz=0x18 */
|
|
<0 0x18040000 0 0x2c>, /* 12. 0x1804_0000 conn_therm_ctl, sz=0x2c */
|
|
<0 0x18041000 0 0x140>, /* 13. 0x1804_1000 conn_afe_ctl, sz=0x140 */
|
|
<0 0x18042000 0 0x324>, /* 14. 0x1804_2000 conn_rf_spi_mst_reg, sz=0x324 */
|
|
<0 0x1804b000 0 0x414>, /* 15. 0x1804_b000 conn_infra_bus_cr, sz=0x414 */
|
|
<0 0x1804d000 0 0x41c>, /* 16. 0x1804_d000 conn_infra_off_debug_ctrl_ao */
|
|
<0 0x1804f000 0 0x148>, /* 17. 0x1804_f000 conn_infra_off_bus_bcrm,0x148 */
|
|
<0 0x18053800 0 0x1000>,/* 18. 0x1805_3800 conn_infra_sysram_sw_cr,0x1000*/
|
|
<0 0x18060000 0 0xbf8>, /* 19. 0x1806_0000 conn_host_csr_top, sz=0xbf8 */
|
|
<0 0x18070000 0 0x8004>,/* 20. 0x1807_0000 conn_semaphore, sz=0x8004 */
|
|
<0 0x1c001000 0 0xfd0>, /* 21. 0x1c00_1000 spm, sz=0xfd0 */
|
|
<0 0x1c007000 0 0x51c>, /* 22. 0x1c00_7000 top_rgu, sz=0x51c */
|
|
<0 0x1803c000 0 0x34>, /* 23. 0x1803_c000 wf2ap_conn_infra_on_ccif4 */
|
|
<0 0x1803e000 0 0x34>; /* 24. 0x1803_e000 bgf2ap_conn_infra_on_ccif4 */
|
|
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_CONN>;
|
|
emi-addr = <0>;
|
|
emi-size = <0x0c00000>;
|
|
emi-alignment = <0x100000>;
|
|
emi-max-addr = <0x90000000>;
|
|
scp-shm-addr = <0>;
|
|
scp-shm-size = <0x20000>;
|
|
scp-remap-offset = <0x2100000>;
|
|
scp-remap-size = <0x20000>;
|
|
|
|
pinctrl-names = "default", "conninfra_tcxo_set", "conninfra_tcxo_clr";
|
|
pinctrl-0 = <&conninfra_pins_default>;
|
|
pinctrl-1 = <&conninfra_pins_tcxo_set>;
|
|
pinctrl-2 = <&conninfra_pins_tcxo_clr>;
|
|
status = "okay";
|
|
};
|
|
|
|
pmic-oc-debug {
|
|
compatible = "mediatek,mt6879-oc-debug";
|
|
interrupt-parent = <&main_pmic>;
|
|
interrupts = <54 IRQ_TYPE_NONE>, <55 IRQ_TYPE_NONE>;
|
|
interrupt-names = "LVSYS_R", "LVSYS_F";
|
|
status = "okay";
|
|
};
|
|
smart_pa: smart_pa {
|
|
};
|
|
|
|
afe: mt6886-afe-pcm@11050000 {
|
|
compatible = "mediatek,mt6886-sound";
|
|
reg = <0 0x11050000 0 0x2000>;
|
|
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
topckgen = <&topckgen_clk>;
|
|
apmixedsys = <&apmixedsys_clk>;
|
|
infracfg = <&infracfg_ao_clk>;
|
|
power-domains = <&scpsys MT6886_POWER_DOMAIN_AUDIO>;
|
|
clocks = <&afe_clk CLK_AFE_AFE>,
|
|
<&afe_clk CLK_AFE_DAC>,
|
|
<&afe_clk CLK_AFE_DAC_PREDIS>,
|
|
<&afe_clk CLK_AFE_ADC>,
|
|
<&afe_clk CLK_AFE_ADDA6_ADC>,
|
|
<&afe_clk CLK_AFE_22M>,
|
|
<&afe_clk CLK_AFE_24M>,
|
|
<&afe_clk CLK_AFE_APLL_TUNER>,
|
|
<&afe_clk CLK_AFE_APLL2_TUNER>,
|
|
<&afe_clk CLK_AFE_TDM>,
|
|
<&afe_clk CLK_AFE_ADDA6_ADC>,
|
|
<&afe_clk CLK_AFE_NLE>,
|
|
<&afe_clk CLK_AFE_DAC_HIRES>,
|
|
<&afe_clk CLK_AFE_ADC_HIRES>,
|
|
<&afe_clk CLK_AFE_ADC_HIRES_TML>,
|
|
<&afe_clk CLK_AFE_ADDA6_ADC_HIRES>,
|
|
<&afe_clk CLK_AFE_3RD_DAC>,
|
|
<&afe_clk CLK_AFE_3RD_DAC_PREDIS>,
|
|
<&afe_clk CLK_AFE_3RD_DAC_TML>,
|
|
<&afe_clk CLK_AFE_3RD_DAC_HIRES>,
|
|
<&apmixedsys_clk CLK_APMIXED_APLL1>,
|
|
<&apmixedsys_clk CLK_APMIXED_APLL2>,
|
|
<&topckgen_clk CLK_TOP_AUDIO_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
|
|
<&topckgen_clk CLK_TOP_MAINPLL_D4_D4>,
|
|
<&topckgen_clk CLK_TOP_AUD_1_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL1>,
|
|
<&topckgen_clk CLK_TOP_AUD_2_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL2>,
|
|
<&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL1_D4>,
|
|
<&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL2_D4>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S3_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S7_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S8_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S9_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV3>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIVB>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV7>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV8>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV9>,
|
|
<&topckgen_clk CLK_TOP_AUDIO_H_SEL>,
|
|
<&topckgen_clk CLK_TOP_TCK_26M_MX9>;
|
|
|
|
clock-names = "aud_afe_clk",
|
|
"aud_dac_clk",
|
|
"aud_dac_predis_clk",
|
|
"aud_adc_clk",
|
|
"aud_adda6_adc_clk",
|
|
"aud_apll22m_clk",
|
|
"aud_apll24m_clk",
|
|
"aud_apll1_tuner_clk",
|
|
"aud_apll2_tuner_clk",
|
|
"aud_tdm_clk",
|
|
"aud_tml_clk",
|
|
"aud_nle",
|
|
"aud_dac_hires_clk",
|
|
"aud_adc_hires_clk",
|
|
"aud_adc_hires_tml",
|
|
"aud_adda6_adc_hires_clk",
|
|
"aud_3rd_dac_clk",
|
|
"aud_3rd_dac_predis_clk",
|
|
"aud_3rd_dac_tml",
|
|
"aud_3rd_dac_hires_clk",
|
|
"aud_clk_apmixed_apll1",
|
|
"aud_clk_apmixed_apll2",
|
|
"top_mux_audio",
|
|
"top_mux_audio_int",
|
|
"top_mainpll_d4_d4",
|
|
"top_mux_aud_1",
|
|
"top_apll1_ck",
|
|
"top_mux_aud_2",
|
|
"top_apll2_ck",
|
|
"top_mux_aud_eng1",
|
|
"top_apll1_d4",
|
|
"top_mux_aud_eng2",
|
|
"top_apll2_d4",
|
|
"top_i2s0_m_sel",
|
|
"top_i2s1_m_sel",
|
|
"top_i2s2_m_sel",
|
|
"top_i2s3_m_sel",
|
|
"top_i2s4_m_sel",
|
|
"top_i2s5_m_sel",
|
|
"top_i2s6_m_sel",
|
|
"top_i2s7_m_sel",
|
|
"top_i2s8_m_sel",
|
|
"top_i2s9_m_sel",
|
|
"top_apll12_div0",
|
|
"top_apll12_div1",
|
|
"top_apll12_div2",
|
|
"top_apll12_div3",
|
|
"top_apll12_div4",
|
|
"top_apll12_divb",
|
|
"top_apll12_div5",
|
|
"top_apll12_div6",
|
|
"top_apll12_div7",
|
|
"top_apll12_div8",
|
|
"top_apll12_div9",
|
|
"top_mux_audio_h",
|
|
"top_clk26m_clk";
|
|
pinctrl-names = "aud-clk-mosi-off",
|
|
"aud-clk-mosi-on",
|
|
"aud-dat-mosi-off",
|
|
"aud-dat-mosi-on",
|
|
"aud-dat-mosi-ch34-off",
|
|
"aud-dat-mosi-ch34-on",
|
|
"aud-dat-miso0-off",
|
|
"aud-dat-miso0-on",
|
|
"aud-dat-miso1-off",
|
|
"aud-dat-miso1-on",
|
|
"aud-dat-miso2-off",
|
|
"aud-dat-miso2-on",
|
|
"vow-dat-miso-off",
|
|
"vow-dat-miso-on",
|
|
"vow-clk-miso-off",
|
|
"vow-clk-miso-on",
|
|
"aud-gpio-i2s0-off",
|
|
"aud-gpio-i2s0-on",
|
|
"aud-gpio-i2s3-off",
|
|
"aud-gpio-i2s3-on";
|
|
pinctrl-0 = <&aud_clk_mosi_off>;
|
|
pinctrl-1 = <&aud_clk_mosi_on>;
|
|
pinctrl-2 = <&aud_dat_mosi_off>;
|
|
pinctrl-3 = <&aud_dat_mosi_on>;
|
|
pinctrl-4 = <&aud_dat_mosi_ch34_off>;
|
|
pinctrl-5 = <&aud_dat_mosi_ch34_on>;
|
|
pinctrl-6 = <&aud_dat_miso0_off>;
|
|
pinctrl-7 = <&aud_dat_miso0_on>;
|
|
pinctrl-8 = <&aud_dat_miso1_off>;
|
|
pinctrl-9 = <&aud_dat_miso1_on>;
|
|
pinctrl-10 = <&aud_dat_miso2_off>;
|
|
pinctrl-11 = <&aud_dat_miso2_on>;
|
|
pinctrl-12 = <&vow_dat_miso_off>;
|
|
pinctrl-13 = <&vow_dat_miso_on>;
|
|
pinctrl-14 = <&vow_clk_miso_off>;
|
|
pinctrl-15 = <&vow_clk_miso_on>;
|
|
pinctrl-16 = <&aud_gpio_i2s0_off>;
|
|
pinctrl-17 = <&aud_gpio_i2s0_on>;
|
|
pinctrl-18 = <&aud_gpio_i2s3_off>;
|
|
pinctrl-19 = <&aud_gpio_i2s3_on>;
|
|
};
|
|
|
|
audio_sram@11052000 {
|
|
compatible = "mediatek,audio_sram";
|
|
reg = <0 0x11052000 0 0x18000>;
|
|
prefer_mode = <0>;
|
|
mode_size = <0x12000 0x18000>;
|
|
block_size = <0x1000>;
|
|
};
|
|
|
|
snd_scp_ultra: snd-scp-ultra {
|
|
compatible = "mediatek,snd-scp-ultra";
|
|
scp-ultra-dl-memif-id = <0x7>;
|
|
scp-ultra-ul-memif-id = <0x10>;
|
|
};
|
|
|
|
btcvsd_snd: mtk-btcvsd-snd@18830000 {
|
|
compatible = "mediatek,mtk-btcvsd-snd";
|
|
reg=<0 0x18830000 0 0x2000>, /*PKV_PHYSICAL_BASE*/
|
|
<0 0x18840000 0 0x20000>; /*SRAM_BANK2*/
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
mediatek,infracfg = <&infracfg_ao_clk>;
|
|
/*INFRA MISC, conn_bt_cvsd_mask*/
|
|
/*cvsd_mcu_read, write, packet_indicator*/
|
|
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
|
|
disable-write-silence = <1>;
|
|
enable-secure-write = <1>;
|
|
};
|
|
|
|
sound: sound {
|
|
compatible = "mediatek,mt6886-mt6368-sound";
|
|
/* mediatek,snd_audio_dsp = <&snd_audio_dsp>; */
|
|
mediatek,headset-codec = <&accdet>;
|
|
mediatek,platform = <&afe>;
|
|
};
|
|
|
|
infracfg_ao_mem@10270000 {
|
|
compatible = "mediatek,infracfg_ao_mem";
|
|
reg = <0 0x10270000 0 0x1000>;
|
|
};
|
|
|
|
slbc: slbc@113e00 {
|
|
compatible = "mediatek,mtk-slbc";
|
|
reg = <0 0x00113e00 0 0x200>;
|
|
slbc-enable = <1>;
|
|
apu = <2097152>;
|
|
};
|
|
|
|
scp: scp@1c700000 {
|
|
compatible = "mediatek,scp";
|
|
status = "okay";
|
|
reg = <0 0x1c400000 0 0x100000>, /* tcm */
|
|
<0 0x1c724000 0 0x1000>, /* cfg */
|
|
<0 0x1c721000 0 0x1000>, /* clk*/
|
|
<0 0x1c730000 0 0x2000>, /* cfg core0 */
|
|
<0 0x1c740000 0 0x1000>, /* cfg core1 */
|
|
<0 0x1c752000 0 0x1000>, /* bus tracker */
|
|
<0 0x1c760000 0 0x40000>, /* llc */
|
|
<0 0x1c7a5000 0 0x4>, /* cfg_sec */
|
|
<0 0x1c7fb000 0 0x100>, /* mbox0 base */
|
|
<0 0x1c7fb100 0 0x4>, /* mbox0 set */
|
|
<0 0x1c7fb10c 0 0x4>, /* mbox0 clr */
|
|
<0 0x1c7a5020 0 0x4>, /* mbox0 init */
|
|
<0 0x1c7fc000 0 0x100>, /* mbox1 base */
|
|
<0 0x1c7fc100 0 0x4>, /* mbox1 set */
|
|
<0 0x1c7fc10c 0 0x4>, /* mbox1 clr */
|
|
<0 0x1c7a5024 0 0x4>, /* mbox1 init */
|
|
<0 0x1c7fd000 0 0x100>, /* mbox2 base */
|
|
<0 0x1c7fd100 0 0x4>, /* mbox2 set */
|
|
<0 0x1c7fd10c 0 0x4>, /* mbox2 clr */
|
|
<0 0x1c7a5028 0 0x4>, /* mbox2 init */
|
|
<0 0x1c7fe000 0 0x100>, /* mbox3 base */
|
|
<0 0x1c7fe100 0 0x4>, /* mbox3 set */
|
|
<0 0x1c7fe10c 0 0x4>, /* mbox3 clr */
|
|
<0 0x1c7a502c 0 0x4>, /* mbox3 init */
|
|
<0 0x1c7ff000 0 0x100>, /* mbox4 base */
|
|
<0 0x1c7ff100 0 0x4>, /* mbox4 set */
|
|
<0 0x1c7ff10c 0 0x4>, /* mbox4 clr */
|
|
<0 0x1c7a5030 0 0x4>; /* mbox4 init */
|
|
|
|
reg-names = "scp_sram_base",
|
|
"scp_cfgreg",
|
|
"scp_clkreg",
|
|
"scp_cfgreg_core0",
|
|
"scp_cfgreg_core1",
|
|
"scp_bus_tracker",
|
|
"scp_l1creg",
|
|
"scp_cfgreg_sec",
|
|
"mbox0_base",
|
|
"mbox0_set",
|
|
"mbox0_clr",
|
|
"mbox0_init",
|
|
"mbox1_base",
|
|
"mbox1_set",
|
|
"mbox1_clr",
|
|
"mbox1_init",
|
|
"mbox2_base",
|
|
"mbox2_set",
|
|
"mbox2_clr",
|
|
"mbox2_init",
|
|
"mbox3_base",
|
|
"mbox3_set",
|
|
"mbox3_clr",
|
|
"mbox3_init",
|
|
"mbox4_base",
|
|
"mbox4_set",
|
|
"mbox4_clr",
|
|
"mbox4_init";
|
|
|
|
interrupts = <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
|
interrupt-names = "ipc0",
|
|
"ipc1",
|
|
"mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4";
|
|
|
|
core_0 = "enable";
|
|
scp-hwvoter = "enable";
|
|
scp_sramSize = <0x00100000>;
|
|
core_nums = <1>; /* core number */
|
|
twohart = <1>; /* two hart arch */
|
|
mbox_count = <5>;
|
|
/* id, mbox, send_size*/
|
|
send_table =
|
|
< 0 0 11>,/* IPI_OUT_AUDIO_VOW_1 */
|
|
<14 0 1>,/* IPI_OUT_DVFS_SET_FREQ_1 */
|
|
<15 0 2>,/* IPI_OUT_C_SLEEP_1 */
|
|
<16 0 1>,/* IPI_OUT_TEST_1 */
|
|
//<24 0 6>,/* IPI_OUT_SCP_MPOOL_1 */
|
|
<17 1 6>,/* IPI_OUT_LOGGER_CTRL */
|
|
<18 1 2>,/* IPI_OUT_SCPCTL_1 */
|
|
< 4 2 1>,/* IPI_OUT_DVFS_SET_FREQ_0 */
|
|
< 5 2 2>,/* IPI_OUT_C_SLEEP_0 */
|
|
< 6 2 1>,/* IPI_OUT_TEST_0 */
|
|
//<11 2 6>,/* IPI_OUT_SCP_MPOOL_0 */
|
|
<33 2 16>,/* IPI_OUT_SCP_CONNSYS */
|
|
< 3 3 4>,/* IPI_OUT_APCCCI_0 */
|
|
<37 3 1>,/* IPI_OUT_SCP_AOD */
|
|
<26 3 9>,/* IPI_OUT_AUDIO_ULTRA_SND_0 */
|
|
<35 3 2>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */
|
|
<29 4 16>,/* IPI_OUT_SENSOR_CTRL */
|
|
<31 4 7>;/* IPI_OUT_SENSOR_NOTIFY */
|
|
|
|
/* id, mbox, recv_size, recv_opt */
|
|
recv_table =
|
|
< 1 0 2 0>,/* IPI_IN_AUDIO_VOW_ACK_1 */
|
|
< 2 0 26 0>,/* IPI_IN_AUDIO_VOW_1 */
|
|
<36 0 1 0>,/* IPI_IN_AUDIO_ACDDET_1 */
|
|
<15 0 1 1>,/* IPI_OUT_C_SLEEP_1 */
|
|
//<25 0 6 0>,/* IPI_IN_SCP_MPOOL_1 */
|
|
<20 1 10 0>,/* IPI_IN_SCP_ERROR_INFO_1 */
|
|
<21 1 6 0>,/* IPI_IN_LOGGER_CTRL */
|
|
<22 1 1 0>,/* IPI_IN_SCP_READY_1 */
|
|
< 5 2 1 1>,/* IPI_OUT_C_SLEEP_0 */
|
|
< 8 2 10 0>,/* IPI_IN_SCP_ERROR_INFO_0 */
|
|
//<12 2 6 0>,/* IPI_IN_SCP_MPOOL_0 */
|
|
<34 2 16 0>,/* IPI_IN_SCP_CONNSYS */
|
|
< 7 3 2 0>,/* IPI_IN_APCCCI_0 */
|
|
<38 3 1 0>,/* IPI_IN_SCP_AOD */
|
|
<28 3 5 0>,/* IPI_IN_AUDIO_ULTRA_SND_0 */
|
|
<27 3 2 0>,/* IPI_IN_AUDIO_ULTRA_SND_ACK_0 */
|
|
<35 3 4 1>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */
|
|
<30 4 2 0>,/* IPI_IN_SENSOR_CTRL */
|
|
<32 4 7 0>;/* IPI_IN_SENSOR_NOTIFY */
|
|
|
|
//legacy_table =<11>, /* out_id_0 IPI_OUT_SCP_MPOOL_0 */
|
|
// <24>, /* out_id_1 IPI_OUT_SCP_MPOOL_1 */
|
|
// <12>, /* in_id_0 IPI_IN_SCP_MPOOL_0 */
|
|
// <12>, /* in_id_1 IPI_IN_SCP_MPOOL_0 */
|
|
// <6>, /* out_size */
|
|
// <6>; /* in_size */
|
|
|
|
/* feature, frequecy, coreid */
|
|
scp_feature_tbl =
|
|
< 0 5 0>, /* vow */
|
|
< 1 350 0>, /* sensor */
|
|
< 2 26 0>, /* flp */
|
|
< 3 0 0>, /* rtos */
|
|
< 4 200 0>, /* speaker */
|
|
< 5 0 0>, /* vcore */
|
|
< 6 135 0>, /* barge in */
|
|
< 7 10 0>, /* vow dump */
|
|
< 8 80 0>, /* vow vendor M */
|
|
< 9 43 0>, /* vow vendor A */
|
|
<10 22 0>, /* vow vendor G */
|
|
<11 20 0>, /* vow dual mic */
|
|
<12 100 0>, /* vow dual mic barge in */
|
|
<13 200 0>; /* ultrasound */
|
|
|
|
debug_dumptimeout = "enable"; /*core dump timeout debug*/
|
|
|
|
scp-dram-region = "enable"; /* enable scp dram region manage */
|
|
scp-protect = "enable"; /* enable scp protections */
|
|
secure_dump = "enable"; /* enable dump via secure world */
|
|
secure_dump_size = <0x280000>;
|
|
|
|
scp_mem_key = "mediatek,reserve-memory-scp_share";
|
|
|
|
/* feature ID, size, alignment */
|
|
scp-mem-tbl = <0 0x0 0x0>, /* secure dump, its size is in secure_dump_size */
|
|
<1 0xca700 0x0>, /* vow */
|
|
<2 0x100000 0x0>, /* sensor main*/
|
|
<3 0x180000 0x0>, /* logger */
|
|
<4 0x19000 0x0>, /* audio */
|
|
<5 0xa000 0x0>, /* vow bargein */
|
|
<7 0x19000 0x0>, /* ultrasound*/
|
|
<8 0x10000 0x0>, /* sensor supper*/
|
|
<9 0x1000 0x0>, /* sensor list */
|
|
<10 0x2000 0x0>, /* sensor debug */
|
|
<11 0x100 0x0>, /* sensor custom writer */
|
|
<12 0x100 0x0>; /* sensor custom reader */
|
|
|
|
memorydump = <0x100000>, /* l2tcm */
|
|
<0x03c000>, /* l1c */
|
|
<0x003c00>, /* regdump */
|
|
<0x000400>, /* trace buffer */
|
|
<0x100000>; /* dram */
|
|
|
|
scp-resource-dump = "enable"; /* enable dump scp related resource */
|
|
/* regulator */
|
|
scp-supply-num = <1>; /* total number of scp related regulator */
|
|
vscp0-supply = <&mt6363_vbuck4>;
|
|
|
|
/* dump register */
|
|
/* cell means register info (address,size), not total reg num */
|
|
scp-resource-reg-dump-cell = <2>;
|
|
scp-resource-reg-dump = <0x1C013008 0x4>,
|
|
<0x1C001908 0x4>,
|
|
<0x1C001818 0x4>;
|
|
};
|
|
|
|
extcon_usb: extcon-usb {
|
|
compatible = "mediatek,extcon-usb";
|
|
vbus-supply = <&mt6375_otg_vbus>;
|
|
vbus-voltage = <5000000>;
|
|
vbus-current = <1800000>;
|
|
charger = <&mt6375_chg>;
|
|
tcpc = "type_c_port0";
|
|
mediatek,bypss-typec-sink = <1>;
|
|
port {
|
|
usb_role: endpoint {
|
|
remote-endpoint = <&mtu3_drd_switch>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rt-pd-manager {
|
|
compatible = "mediatek,rt-pd-manager";
|
|
/* wd0_enable : use it for enable wd0 function */
|
|
//wd0_enable;
|
|
};
|
|
|
|
pd_adapter: pd_adapter {
|
|
compatible = "mediatek,pd_adapter";
|
|
boot_mode = <&chosen>;
|
|
adapter_name = "pd_adapter";
|
|
force_cv;
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
|
|
flashlight_core: flashlight-core {
|
|
compatible = "mediatek,flashlight_core";
|
|
};
|
|
|
|
mtk_composite_v4l2_1: mtk-composite-v4l2-1 {
|
|
compatible = "mediatek,mtk_composite_v4l2_1";
|
|
};
|
|
|
|
mtk_composite_v4l2_2: mtk-composite-v4l2-2 {
|
|
compatible = "mediatek,mtk_composite_v4l2_2";
|
|
};
|
|
|
|
mtk_ctd: mtk_ctd {
|
|
compatible = "mediatek,mtk_ctd";
|
|
bc12 = <&mt6375_chg>;
|
|
bc12_sel = <0>;
|
|
};
|
|
|
|
usb_meta: usb-meta {
|
|
compatible = "mediatek,usb-meta";
|
|
udc = <&ssusb>;
|
|
};
|
|
|
|
usb_boost: usb-boost-manager {
|
|
compatible = "mediatek,usb-boost", "mediatek,mt6886-usb-boost";
|
|
interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>;
|
|
interconnect-names = "icc-bw";
|
|
required-opps = <&dvfsrc_freq_opp0>;
|
|
usb-audio;
|
|
small-core = <1250000>;
|
|
};
|
|
|
|
clock_buffer_ctrl: clock_buffer_ctrl {
|
|
compatible = "mediatek,clock_buffer_ctrl";
|
|
mediatek,xo-buf-hwbblpm-mask = <1 0 0 0 0>,
|
|
<0 0 0>,
|
|
<0 0 0>,
|
|
<0 0>;
|
|
mediatek,xo-buf-hwbblpm-bypass = <0 0 0 0 0>,
|
|
<0 0 0>,
|
|
<0 0 0>,
|
|
<0 0>;
|
|
mediatek,xo-bbck4 = <0>;
|
|
|
|
mediatek,enable;
|
|
|
|
pmif = <&spmi 0>;
|
|
pmif_version = <2>;
|
|
srclken_rc = <&srclken_rc>;
|
|
consys = <&consys>;
|
|
// pcie = <&pcie_ckm_xtal_ck>;
|
|
};
|
|
|
|
bt: bt@18000000 {
|
|
compatible = "mediatek,bt";
|
|
/* flavor_bin = "b"; */
|
|
/* conn_infra_rgu */
|
|
reg = <0 0x18000000 0 0x1000>,
|
|
/* conn_infra_cfg */
|
|
<0 0x18001000 0 0x1000>,
|
|
/* sys ram */
|
|
<0 0x18051000 0 0x1000>,
|
|
/* conn_host_csr_top */
|
|
<0 0x18060000 0 0x1000>,
|
|
/* bgfsys base */
|
|
<0 0x18800000 0 0x1000>,
|
|
/* bgfsys hw info base */
|
|
<0 0x18812000 0 0x1000>,
|
|
/* coninfra cfg ao */
|
|
<0 0x10001000 0 0x1000>;
|
|
/* coninfra ccif base */
|
|
/* <0 0x10003300 0 0x100>, */
|
|
/* bgf2md base */
|
|
/* <0 0x1025c000 0 0x100>; */
|
|
/* Rx Interrupt */
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
/* Assert & FW log interrupt */
|
|
<GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
};
|
|
|
|
met {
|
|
met_emi: met-emi {
|
|
compatible = "mediatek,met_emi";
|
|
emi-num = <1>;
|
|
dram-num = <2>;
|
|
dramc-ver = <2>;
|
|
/*0: dram ebg, 1:emi_freq, 2: DRAMC_DCM_CTRL 3:chn_emi_low_effi 4:SLC*/
|
|
met-emi-support-list = <0x13>;
|
|
cen-emi-reg-base = <0x10219000 0x1021d000>;
|
|
cen-emi-reg-size = <0x1000>;
|
|
chn-emi-reg-base = <0x10235000 0x10245000 0x10255000 0x10265000>;
|
|
chn-emi-reg-size = <0xa90>;
|
|
dramc-nao-reg-base = <0x10234000 0x10244000 0x10254000 0x10264000>;
|
|
dramc-nao-reg-size = <0x76c>;
|
|
dramc-ao-reg-base = <0x10230000 0x10240000 0x10250000 0x10260000>;
|
|
dramc-ao-reg-size = <0x2000>;
|
|
ddrphy-ao-reg-base = <0x10238000 0x10248000 0x10258000 0x10268000>;
|
|
ddrphy-ao-reg-size = <0x1650>;
|
|
ddrphy-ao-misc-cg-ctrl0 = <0x70c>;
|
|
ddrphy-ao-misc-cg-ctrl2 = <0x714>;
|
|
dram-freq-default = <6400>;
|
|
ddr-ratio-default = <8>;
|
|
dram-type-default = <8>;
|
|
apmixedsys-reg-base = <0x1000c000>;
|
|
apmixedsys-reg-size = <0x410>;
|
|
slc-pmu-reg-base = <0x10342000 0x10343000>;
|
|
slc-pmu-reg-size = <0x1000>;
|
|
};
|
|
|
|
met-res-ram {
|
|
compatible = "mediatek,met_res_ram";
|
|
|
|
met-res-ram-sspm {
|
|
size = <0x400000>; /* 4M: only reserve on userdebug/eng load */
|
|
start = <0x0>; /* start addr of reserved ram*/
|
|
};
|
|
|
|
met-res-ram-mcupm {
|
|
size = <0x400000>; /* 4M: only reserve on userdebug/eng load */
|
|
start = <0x0>; /* start addr of reserved ram*/
|
|
};
|
|
|
|
met-res-ram-gpueb {
|
|
size = <0x400000>; /* 4M: only reserve on userdebug/eng load */
|
|
start = <0x0>; /* start addr of reserved ram*/
|
|
};
|
|
};
|
|
|
|
mcupm_rts_header:mcupm-rts-header {
|
|
node-0 = "MCUPM_MET_UNIT_TEST", "test";
|
|
|
|
node-1 = "__MCUPM_MET_L3CTL__", "op_policy,ct_portion,nct_portion,\
|
|
cpuqos_mode,dnth0,dnth1,upth0,upth1";
|
|
node-2 = "__MCUPM_MET_TEST__", "taskId,isrId,dvfs";
|
|
};
|
|
|
|
sspm_rts_header:sspm-rts-header {
|
|
node-0 = "SSPM_PTPOD",
|
|
"_id,voltage";
|
|
|
|
node-1 = "SSPM_MET_UNIT_TEST",
|
|
"test";
|
|
|
|
node-2 = "SSPM_QOS_BOUND_STATE",
|
|
"ver,apu_num,idx,state,num,event,emibw_mon_total,",
|
|
"emibw_mon_cpu,emibw_mon_gpu,emibw_mon_mm,",
|
|
"emibw_mon_md,smibw_mon_gpu,smibw_mon_apu,",
|
|
"apubw_mon_vpu0,apubw_mon_vpu1,apubw_mon_mdla0,",
|
|
"apubw_mon_mdla1,apubw_mon_mdla2,apubw_mon_mdla3,",
|
|
"apubw_mon_edma0,apubw_mon_edma1,",
|
|
"apulat_mon_vpu0,apulat_mon_vpu1,apulat_mon_mdla0,",
|
|
"apulat_mon_mdla1,apulat_mon_mdla2,apulat_mon_mdla3,",
|
|
"apulat_mon_edma0,apulat_mon_edma1";
|
|
|
|
node-3 = "SSPM_CM_MGR_NON_WFX",
|
|
"non_wfx_0,non_wfx_1,non_wfx_2,non_wfx_3,",
|
|
"non_wfx_4,non_wfx_5,non_wfx_6,non_wfx_7";
|
|
|
|
node-4 = "SSPM_CM_MGR_LOADING",
|
|
"ratio,cps";
|
|
|
|
node-5 = "SSPM_CM_MGR_POWER",
|
|
"c_up_array_0,c_up_array_1,c_down_array_0,c_down_array_1,",
|
|
"c_up_0,c_up_1,c_down_0,c_down_1,c_up,c_down,",
|
|
"v_up,v_down,v2f_0,v2f_1";
|
|
|
|
node-6 = "SSPM_CM_MGR_OPP",
|
|
"v_dram_opp,v_dram_opp_cur,c_opp_cur_0,c_opp_cur_1,",
|
|
"d_times_up,d_times_down";
|
|
|
|
node-7 = "SSPM_CM_MGR_RATIO",
|
|
"ratio_0,ratio_1,ratio_2,ratio_3,ratio_4,",
|
|
"ratio_5,ratio_6,ratio_7";
|
|
|
|
node-8 = "SSPM_CM_MGR_BW",
|
|
"total_bw";
|
|
|
|
node-9 = "SSPM_CM_MGR_CP_RATIO",
|
|
"up0,up1,up2,up3,up4,up5,up6,down0,down1,down2,down3,down4,",
|
|
"down5,down6";
|
|
|
|
node-10 = "SSPM_CM_MGR_VP_RATIO",
|
|
"up0,up1,up2,up3,up4,up5,up6,down0,down1,down2,down3,down4,",
|
|
"down5,down6";
|
|
|
|
node-11 = "SSPM_CM_MGR_DE_TIMES",
|
|
"up0,up1,up2,up3,up4,up5,up6,down0,down1,down2,down3,down4,",
|
|
"down5,down6,reset";
|
|
|
|
node-12 = "SSPM_CM_MGR_DSU_DVFS_PWR",
|
|
"up_L,up_B,up_DSU,cur_L,cur_B,cur_DSU,down_L,down_B,",
|
|
"down_DSU,total_up,total_cur,total_down";
|
|
|
|
node-13 = "SSPM_CM_MGR_DSU_DVFS_ACT_STALL_PWR",
|
|
"up_L_a,up_B_a,cur_L_a,cur_B_a,",
|
|
"down_L_a,down_B_a,",
|
|
"up_L_s,up_B_s,cur_L_s,cur_B_s,",
|
|
"down_L_s,down_B_s";
|
|
|
|
node-14 = "SSPM_CM_MGR_DSU_DVFS_STALL",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,l3_bw_val";
|
|
|
|
node-15 = "SSPM_CM_MGR_DSU_DVFS_ACTIVE",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-16 = "SSPM_CM_MGR_DSU_DVFS_OPP",
|
|
"map_opp_50,map_opp_70,final,",
|
|
"orig,L3_vote_opp,debounce_up,debounce_down";
|
|
|
|
node-17 = "SSPM_CM_MGR_DSU_DVFS_THRESHOLD_FLAG",
|
|
"up_L,up_B,down_L,down_B,",
|
|
"up_L_flag,up_B_flag,",
|
|
"down_L_flag,down_B_flag";
|
|
|
|
node-18 = "SSPM_SWPM_CPU__CORE_ACTIVE_RATIO",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-19 = "SSPM_SWPM_CPU__CORE_IDLE_RATIO",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-20 = "SSPM_SWPM_CPU__CORE_OFF_RATIO",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-21 = "SSPM_SWPM_CPU__CORE_STALL_RATIO",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-22 = "SSPM_SWPM_CPU__CORE_PMU_L3DC",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-23 = "SSPM_SWPM_CPU__CORE_PMU_INST_SPEC",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-24 = "SSPM_SWPM_CPU__CORE_PMU_CYCLES",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-25 = "SSPM_SWPM_CPU__CORE_NON_WFX_CTR",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
|
|
node-26 = "SSPM_SWPM_CPU__DSU_STATE_RATIO",
|
|
"active,idle,dormant,off";
|
|
|
|
node-27 = "SSPM_SWPM_CPU__DSU_L3_BW",
|
|
"L3_BW";
|
|
|
|
node-28 = "SSPM_SWPM_CPU__MCUSYS_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-29 = "SSPM_SWPM_CPU__MCUSYS_EMI_BW",
|
|
"cpu_emi_bw";
|
|
|
|
node-30 = "SSPM_SWPM_CPU__DVFS",
|
|
"cpuL_proc,cpuB_proc,cci_proc,",
|
|
"cpuL_freq,cpuB_freq,cci_freq,",
|
|
"cpuL_opp,cpuB_opp,cci_opp";
|
|
|
|
node-31 = "SSPM_SWPM_CPU__LKG_POWER",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,dsu";
|
|
|
|
node-32 = "SSPM_SWPM_CPU__POWER",
|
|
"cpu_L,cpu_B,dsu,mcusys";
|
|
|
|
node-33 = "SSPM_SWPM_GPU__GPU_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-34 = "SSPM_SWPM_GPU__LOADING",
|
|
"top_loading,stack_loading";
|
|
|
|
node-35 = "SSPM_SWPM_GPU__DVFS",
|
|
"top_freq,stack_freq,vgpu,vcore,mtcmos,top_ratio,stack_ratio";
|
|
|
|
node-36 = "SSPM_SWPM_GPU__URATE",
|
|
"alu_fma,alu_cvt,alu_sfu,tex,lsc,l2c,vary,tiler,rast";
|
|
|
|
node-37 = "SSPM_SWPM_GPU__THERMAL",
|
|
"thermal,top_lkg,stack_lkg";
|
|
|
|
node-38 = "SSPM_SWPM_GPU__COUNTER",
|
|
"GPU_ACTIVE,EXEC_CORE_ACTIVE,EXEC_INSTR_FMA,EXEC_INSTR_CVT,EXEC_INSTR_SFU,",
|
|
"TEX,VARY_SLOT,L20,L21,L22,L23,ITERATOR_ACTIVE";
|
|
|
|
node-39 = "SSPM_SWPM_GPU__POWER",
|
|
"gpu";
|
|
node-40 = "SSPM_SWPM_CORE__CAM_STATE_RATIO",
|
|
"RAW_A_active,RAW_B_active,RAW_C_active,idle,off";
|
|
|
|
node-41 = "SSPM_SWPM_CORE__IMG_STATE_RATIO",
|
|
"P2_active,P2_idle,MFB_active,WPE_active,off";
|
|
|
|
node-42 = "SSPM_SWPM_CORE__IPE_STATE_RATIO",
|
|
"FDVT_active,DVP_active,DVS_active,DV_idle,off";
|
|
|
|
node-43 = "SSPM_SWPM_CORE__MDP_STATE_RATIO",
|
|
"active,off";
|
|
|
|
node-44 = "SSPM_SWPM_CORE__DISP_STATE_RATIO",
|
|
"active,off";
|
|
|
|
node-45 = "SSPM_SWPM_CORE__ADSP_STATE_RATIO",
|
|
"active,off";
|
|
|
|
node-46 = "SSPM_SWPM_CORE__VENC_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-47 = "SSPM_SWPM_CORE__VDEC_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-48 = "SSPM_SWPM_CORE__INFRA_STATE_RATIO",
|
|
"dact,cact,idle,dcm";
|
|
|
|
node-49 = "SSPM_SWPM_CORE__VDO_CODING_TYPE",
|
|
"venc,vdec";
|
|
|
|
node-50 = "SSPM_SWPM_CORE__DVFS",
|
|
"vcore,ddr_freq,vcore_opp,ddr_opp";
|
|
|
|
node-51 = "SSPM_SWPM_CORE__POWER",
|
|
"dramc,infra_top,aphy_vcore";
|
|
|
|
node-52 = "SSPM_SWPM_CORE__LKG_POWER",
|
|
"infra_top,dramc,thermal";
|
|
|
|
node-53 = "SSPM_SWPM_DRAM__MEM_IDX",
|
|
"read_bw,write_bw,",
|
|
"srr_pct,ssr_pct,pdir_pct,",
|
|
"phr_pct,util,",
|
|
"trans,mr4,ddr_freq,ddr_opp";
|
|
|
|
node-54 = "SSPM_SWPM_DRAM__DVFS",
|
|
"ddr_freq";
|
|
|
|
node-55 = "SSPM_SWPM_DRAM__POWER",
|
|
"aphy_vddq_0p6v,aphy_vm_0p75v,aphy_vio_1p2v,dram_vddq_0p6v,",
|
|
"dram_vdd2l_0p9v,dram_vdd2h_1p05v,dram_vdd1_1p8v";
|
|
|
|
node-56 = "SSPM_SWPM_ME__POWER",
|
|
"disp,mdp,venc,vdec";
|
|
|
|
node-57 = "SSPM_SWPM_ME__IDX",
|
|
"vdec_fps,venc_fps,disp_fps,disp_resolution";
|
|
|
|
node-58 = "SSPM_SWPM_VPU__VPU0_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-59 = "SSPM_SWPM_VPU__VPU1_STATE_RATIO",
|
|
"active,idle,off";
|
|
|
|
node-60 = "__SSPM_GPU_APU_SSC_CNT__",
|
|
"APU_0_R,APU_0_W,GPU_0_R,GPU_0_W,",
|
|
"APU_1_R,APU_1_W,GPU_1_R,",
|
|
"GPU_1_W";
|
|
node-61 = "SSPM_SLBC_SLOT",
|
|
"enable,force,done,buffer_used,f_buffer,cached_used,force_size";
|
|
node-62 = "SSPM_SLBC_REF",
|
|
"venc,mml,ainr,disp";
|
|
node-63 = "SSPM_SLBC_BW",
|
|
"mm,apu,mm_est";
|
|
node-64 = "SSPM_SLBC_PMU",
|
|
"hit,miss,apu_r,apu_w,mm_r,mm_w";
|
|
node-65 = "SSPM_SLBC_WAY",
|
|
"venc,mml,ainr,disp,slb,cpu,gpu,slc,left";
|
|
node-66 = "SSPM_SWPM_CPU__DSU_PMU",
|
|
"dsu_cycles";
|
|
node-67 = "SSPM_SWPM_CPU__CORE_TEMP",
|
|
"cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7";
|
|
node-68 = "SSPM_SWPM_SOC__SMAP",
|
|
"i2max,imax";
|
|
node-69 = "SSPM_SWPM_CPU__PMU_TIMES",
|
|
"idx_cnt,lock,idx_rechk,lock_rechk,valid,off_hint,diff_us";
|
|
node-70 = "SSPM_SWPM_CORE__MEM_RAW_IDX",
|
|
"diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,",
|
|
"wact,bcnt,",
|
|
"dcm_ctrl,",
|
|
"stb_0_0,stb_0_1,stb_1_0,stb_1_1,",
|
|
"pd_0_0,pd_0_1,pd_1_0,pd_1_1";
|
|
node-71 = "SSPM_SPM_RES__DDREN_REQ",
|
|
"md,scp,sspm";
|
|
node-72 = "SSPM_SPM_RES__APSRC_REQ",
|
|
"md,scp,sspm";
|
|
node-73 = "SSPM_SPM_DBG__PWR_OFF",
|
|
"dsu,mcu,gpu,venc,vdec,mdp,disp,cam,img,mmup,mminfra";
|
|
node-74 = "SSPM_SPM_DBG__PWR_ACT",
|
|
"scp,adsp";
|
|
node-75 = "SSPM_SPM_DBG__SYS_STA",
|
|
"s1";
|
|
node-76 = "SSPM_SWPM_DRAM__MEM_RAW_IDX",
|
|
"diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,",
|
|
"wact,bact,bcnt,tact,",
|
|
"pgh_0,pgh_1,",
|
|
"pgm_0,pgm_1,",
|
|
"intb_0,intb_1,",
|
|
"stb_0_0,stb_0_1,stb_1_0,stb_1_1,",
|
|
"mr4_idx_0_0,mr4_idx_0_1,mr4_idx_1_0,mr4_idx_1_1";
|
|
};
|
|
|
|
gpueb_rts_header:gpueb-rts-header {
|
|
node-0 = "GPUEB_MET_UNIT_TEST", "test";
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&spmi {
|
|
pmic@4 {
|
|
mt6363_dynamic_loading_throttling: mtk-dynamic-loading-throttling {
|
|
compatible = "mediatek,mt6363-dynamic_loading_throttling";
|
|
/* charger: mtk_charger_thread */
|
|
mediatek,charger = <&lk_charger>;
|
|
/* 2000~2900mV, one gear per 100mV */
|
|
uvlo-level = <2600>;
|
|
vbb-uvlo-level = <2600>;
|
|
io-channels = <&mt6375_auxadc MT6375_AUXADC_IMP>,
|
|
<&mt6375_auxadc MT6375_AUXADC_IMIX_R>,
|
|
<&mt6375_auxadc MT6375_AUXADC_BATSNS>;
|
|
io-channel-names = "pmic_ptim",
|
|
"pmic_imix_r",
|
|
"pmic_batadc";
|
|
bootmode = <&chosen>;
|
|
};
|
|
};
|
|
|
|
mt6319_6: mt6319@6 {
|
|
compatible = "mediatek,mt6319";
|
|
reg = <0x6 SPMI_USID>;
|
|
|
|
extbuck-debug {
|
|
compatible = "mediatek,spmi-pmic-debug";
|
|
};
|
|
mt6319_6_regulator: mt6319-6-regulator {
|
|
compatible = "mediatek,mt6315_6-regulator";
|
|
buck-size = <3>;
|
|
buck1-modeset-mask = <0x3>;
|
|
|
|
mt6319_6_vbuck1: 6-vbuck1 {
|
|
regulator-compatible = "vbuck1";
|
|
regulator-name = "6_vbuck1";
|
|
regulator-min-microvolt = <300000>;
|
|
regulator-max-microvolt = <1193750>;
|
|
regulator-enable-ramp-delay = <256>;
|
|
regulator-allowed-modes = <0 1 2>;
|
|
regulator-always-on;
|
|
};
|
|
mt6319_6_vbuck3: 6-vbuck3 {
|
|
regulator-compatible = "vbuck3";
|
|
regulator-name = "6_vbuck3";
|
|
regulator-min-microvolt = <300000>;
|
|
regulator-max-microvolt = <1193750>;
|
|
regulator-enable-ramp-delay = <256>;
|
|
regulator-allowed-modes = <0 1 2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
clock-frequency = <1000000>;
|
|
mt6375: mt6375@34 {
|
|
compatible = "mediatek,mt6375";
|
|
reg = <0x34>;
|
|
status = "okay";
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <145 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
wakeup-source;
|
|
mt6375_adc: adc {
|
|
compatible = "mediatek,mt6375-adc";
|
|
#io-channel-cells = <1>;
|
|
interrupts = <MT6375_ADC_DONEI>;
|
|
interrupt-names = "adc_donei";
|
|
};
|
|
mt6375_chg: chg {
|
|
compatible = "mediatek,mt6375-chg";
|
|
interrupts = <MT6375_FL_PWR_RDY>, <MT6375_FL_DETACH>,
|
|
<MT6375_FL_VBUS_OV>, <MT6375_FL_CHG_TOUT>,
|
|
<MT6375_FL_WDT>, <MT6375_FL_BC12_DN>,
|
|
<MT6375_FL_AICC_DONE>, <MT6375_FL_PE_DONE>,
|
|
<MT6375_FL_BATPRO_DONE>,
|
|
<MT6375_ADC_VBAT_MON_OV>;
|
|
interrupt-names = "fl_pwr_rdy", "fl_detach",
|
|
"fl_vbus_ov", "fl_chg_tout",
|
|
"fl_wdt", "fl_bc12_dn",
|
|
"fl_aicc_done", "fl_pe_done",
|
|
"fl_batpro_done", "adc_vbat_mon_ov";
|
|
io-channels = <&mt6375_adc MT6375_ADC_CHGVIN>,
|
|
<&mt6375_adc MT6375_ADC_VSYS>,
|
|
<&mt6375_adc MT6375_ADC_VBAT>,
|
|
<&mt6375_adc MT6375_ADC_IBUS>,
|
|
<&mt6375_adc MT6375_ADC_IBAT>,
|
|
<&mt6375_adc MT6375_ADC_TEMPJC>,
|
|
<&mt6375_adc MT6375_ADC_USBDP>,
|
|
<&mt6375_adc MT6375_ADC_USBDM>;
|
|
chg_name = "primary_chg";
|
|
aicr = <500>;
|
|
mivr = <4400>;
|
|
cv = <4200>;
|
|
ichg = <2000>;
|
|
ieoc = <150>;
|
|
wdt = <40000>;
|
|
/* wdt_en; */
|
|
te_en;
|
|
vbus_ov = <14500>;
|
|
vrec = <100>;
|
|
otg_lbp = <2800>;
|
|
ircmp_r = <16700>;
|
|
ircmp_v = <32>;
|
|
chg_tmr = <10>;
|
|
chg_tmr_en;
|
|
dcdt_sel = <600>;
|
|
bc12_sel = <&mtk_ctd>;
|
|
boot_mode = <&chosen>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
phy-names = "usb2-phy";
|
|
usb = <&ssusb>;
|
|
pmic-uvlo = <&mt6363_dynamic_loading_throttling>;
|
|
//usb_killer_detect;
|
|
mt6375_otg_vbus: otg {
|
|
regulator-compatible = "mt6375,otg-vbus";
|
|
regulator-name = "usb-otg-vbus";
|
|
regulator-min-microvolt = <4850000>;
|
|
regulator-max-microvolt = <5500000>;
|
|
regulator-min-microamp = <500000>;
|
|
regulator-max-microamp = <2400000>;
|
|
};
|
|
};
|
|
mt6375_typec: tcpc {
|
|
compatible = "mediatek,mt6375-tcpc";
|
|
interrupts = <MT6375_PD_EVT>;
|
|
interrupt-names = "pd_evt";
|
|
/* tcpc_device's name */
|
|
tcpc,name = "type_c_port0";
|
|
/* 0: Unknown, 1: SNK, 2: SRC, 3: DRP, 4: Try.SRC, 5: Try.SNK */
|
|
tcpc,role_def = <5>;
|
|
/* 0: Default, 1: 1.5, 2: 3.0 */
|
|
tcpc,rp_level = <1>;
|
|
/* 0: Never, 1: Always, 2: EMarkOnly, 3: StartOnly */
|
|
tcpc,vconn_supply = <1>;
|
|
io-channels = <&mt6375_adc MT6375_ADC_SBU1>,
|
|
<&mt6375_adc MT6375_ADC_SBU2>;
|
|
charger = <&mt6375_chg>;
|
|
tcpc,en_wd;
|
|
tcpc,en_wd_sbu_polling;
|
|
tcpc,en_wd_polling_only;
|
|
tcpc,en_ctd;
|
|
tcpc,en_fod;
|
|
tcpc,en_typec_otp;
|
|
//tcpc,en_floatgnd;
|
|
wd,sbu_calib_init = <1200>; /* mV */
|
|
wd,sbu_pl_bound = <200>; /* mV */
|
|
wd,sbu_pl_lbound_c2c = <1100>; /* mV */
|
|
wd,sbu_pl_ubound_c2c = <2600>; /* mV */
|
|
wd,sbu_ph_auddev = <100>; /* mV */
|
|
wd,sbu_ph_lbound = <888>; /* mV */
|
|
wd,sbu_ph_lbound1_c2c = <2850>; /* mV */
|
|
wd,sbu_ph_ubound1_c2c = <3150>; /* mV */
|
|
wd,sbu_ph_ubound2_c2c = <3800>; /* mV */
|
|
wd,sbu_aud_ubound = <1600>; /* mV */
|
|
/* 0:16x, 1:128x, 2:512x, 3:1024x */
|
|
wd,wd0_tsleep = <1>;
|
|
/* 0:400us, 1:1ms, 2:2ms, 3:4ms, 4:10ms, 5:40ms, 6:100ms, 7:400ms */
|
|
wd,wd0_tdet = <3>;
|
|
/* example wd0_tsleep = 512x, wd0_tdet = 4ms, wd0 polling time = 512*4ms */
|
|
pd-data {
|
|
pd,vid = <0x29cf>;
|
|
pd,pid = <0x6375>;
|
|
pd,source-cap-ext = /bits/ 8 <0xcf 0x29 0x75 0x63
|
|
0x00 0x00 0x00 0x00
|
|
0x00 0x00 0x00 0x00
|
|
0x00 0x00 0x00 0x00
|
|
0x00 0x00 0x00 0x00
|
|
0x00 0x00 0x01 0x07
|
|
0x00>;
|
|
pd,mfrs = "RichtekTCPC";
|
|
|
|
/*
|
|
* VSAFE5V = 0, MAX_POWER = 1, CUSTOM = 2,
|
|
* MAX_POWER_LV = 0x21, MAX_POWER_LVIC = 0x31
|
|
* MAX_POWER_HV = 0x41, MAX_POWER_HVIC = 0x51
|
|
*/
|
|
pd,charging_policy = <0x31>;
|
|
|
|
pd,source-pdo-size = <1>;
|
|
pd,source-pdo-data = <0x00019096>; /* 5V, 1500 mA */
|
|
pd,sink-pdo-size = <1>;
|
|
pd,sink-pdo-data = <0x000190c8>;
|
|
|
|
/*
|
|
* No DP, host + device
|
|
* pd,id-vdo-size = <6>;
|
|
* pd,id-vdo-data = <0xd14029cf 0x0 0x63750000
|
|
0x61000000 0x0 0x41000000>;
|
|
* With DP
|
|
* pd,id-vdo-size = <6>;
|
|
* pd,id-vdo-data = <0xd54029cf 0x0 0x63750000
|
|
0x61000000 0x0 0x41000000>;
|
|
*/
|
|
|
|
pd,id-vdo-size = <6>;
|
|
pd,id-vdo-data = <0xd54029cf 0x0 0x63750000
|
|
0x61000000 0x0 0x41000000>;
|
|
|
|
bat,nr = <1>;
|
|
bat-info0 {
|
|
bat,vid = <0x29cf>;
|
|
bat,pid = <0x6375>;
|
|
bat,mfrs = "bat1";
|
|
bat,design_cap = <3000>;
|
|
};
|
|
};
|
|
dpm_caps {
|
|
local_dr_power;
|
|
local_dr_data;
|
|
// local_ext_power;
|
|
local_usb_comm;
|
|
// local_usb_suspend;
|
|
// local_high_cap;
|
|
// local_give_back;
|
|
local_no_suspend;
|
|
local_vconn_supply;
|
|
|
|
// attempt_discover_cable_dfp;
|
|
attempt_enter_dp_mode;
|
|
attempt_discover_cable;
|
|
attempt_discover_id;
|
|
|
|
/* 0: disable, 1: prefer_snk, 2: prefer_src */
|
|
pr_check = <0>;
|
|
// pr_reject_as_source;
|
|
// pr_reject_as_sink;
|
|
// pr_check_gp_source;
|
|
// pr_check_gp_sink;
|
|
|
|
/* 0: disable, 1: prefer_ufp, 2: prefer_dfp */
|
|
dr_check = <0>;
|
|
// dr_reject_as_dfp;
|
|
// dr_reject_as_ufp;
|
|
};
|
|
displayport {
|
|
/* connection type = "both", "ufp_d", "dfp_d" */
|
|
1st_connection = "dfp_d";
|
|
2nd_connection = "dfp_d";
|
|
signal,dp_v13;
|
|
//signal,dp_gen2;
|
|
//usbr20_not_used;
|
|
typec,receptacle;
|
|
ufp_d {
|
|
//pin_assignment,mode_a;
|
|
//pin_assignment,mode_b;
|
|
//pin_assignment,mode_c;
|
|
//pin_assignment,mode_d;
|
|
//pin_assignment,mode_e;
|
|
};
|
|
dfp_d {
|
|
//pin_assignment,mode_a;
|
|
//pin_assignment,mode_b;
|
|
pin_assignment,mode_c;
|
|
pin_assignment,mode_d;
|
|
pin_assignment,mode_e;
|
|
//pin_assignment,mode_f;
|
|
};
|
|
};
|
|
};
|
|
mt6375_auxadc: auxadc {
|
|
compatible = "mediatek,pmic-auxadc",
|
|
"mediatek,mt6375-auxadc";
|
|
interrupts = <MT6375_GM30_EVT>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#io-channel-cells = <1>;
|
|
io-channels = <&mt6375_adc MT6375_ADC_VBAT>,
|
|
<&mt6375_auxadc MT6375_AUXADC_BATSNS_DBG>;
|
|
io-channel-names = "chg_vbat", "auxadc_vbat";
|
|
charger = <&mt6375_chg>;
|
|
isink_load-supply = <&mt6363_isink_load>;
|
|
imix_r {
|
|
val = <90>;
|
|
};
|
|
};
|
|
mtk_gauge: mtk_gauge {
|
|
compatible = "mediatek,mt6375-gauge";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
bootmode = <&chosen>;
|
|
charger = <&mt6375_chg>;
|
|
io-channels = <&mt6375_auxadc MT6375_AUXADC_BATSNS>,
|
|
<&mt6375_auxadc MT6375_AUXADC_BATON>,
|
|
<&mt6375_auxadc MT6375_AUXADC_IMP>,
|
|
<&mt6375_auxadc MT6375_AUXADC_IMIX_R>,
|
|
<&mt6375_auxadc MT6375_AUXADC_VREF>;
|
|
io-channel-names = "bat_volt", "bat_temp", "ptim_bat_volt",
|
|
"ptim_r", "vref";
|
|
interrupts-extended = <&mt6375 MT6375_GM30_EVT>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_BAT_H>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_BAT_L>,
|
|
<&mt6375_auxadc RG_INT_STATUS_BAT2_H>,
|
|
<&mt6375_auxadc RG_INT_STATUS_BAT2_L>,
|
|
<&mt6375_auxadc RG_INT_STATUS_NAG_C_DLTV>,
|
|
<&mtk_gauge RG_INT_STATUS_BATON_BAT_OUT>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_ZCV>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_N_CHARGE_L>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_IAVG_H>,
|
|
<&mtk_gauge RG_INT_STATUS_FG_IAVG_L>,
|
|
<&mt6375_auxadc RG_INT_STATUS_BAT_TEMP_H>,
|
|
<&mt6375_auxadc RG_INT_STATUS_BAT_TEMP_L>;
|
|
interrupt-names = "GM30_EVT", "COULOMB_H", "COULOMB_L",
|
|
"VBAT2_H", "VBAT2_L", "NAFG", "BAT_OUT", "ZCV",
|
|
"FG_N_CHARGE_L", "FG_IAVG_H", "FG_IAVG_L", "BAT_TMP_H",
|
|
"BAT_TMP_L";
|
|
nvmem-cells = <&fg_init>, <&fg_soc>;
|
|
nvmem-cell-names = "initialization", "state-of-charge";
|
|
};
|
|
lbat_service {
|
|
compatible = "mediatek,mt6375-lbat-service";
|
|
interrupts-extended = <&mt6375_auxadc RG_INT_STATUS_BAT_H>,
|
|
<&mt6375_auxadc RG_INT_STATUS_BAT_L>;
|
|
interrupt-names = "bat_h", "bat_l";
|
|
resistance-ratio = <4 1>;
|
|
};
|
|
dbg {
|
|
compatible = "mediatek,mt6375-dbg";
|
|
};
|
|
mt6375_batoc_throttle: mtk_battery_oc_throttling {
|
|
compatible = "mediatek,mt6375-battery_oc_throttling";
|
|
interrupts-extended = <&mtk_gauge MT6375_IRQ_FG_CUR_H>,
|
|
<&mtk_gauge MT6375_IRQ_FG_CUR_L>;
|
|
interrupt-names = "fg_cur_h", "fg_cur_l";
|
|
oc-thd-h = <6800>;
|
|
oc-thd-l = <8000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c6 {
|
|
gate_ic: gate_ic@11 {
|
|
compatible = "mediatek,gate-ic-i2c";
|
|
gate-power-gpios = <&pio 148 0>;
|
|
reg = <0x11>;
|
|
id = <6>;
|
|
status = "okay";
|
|
};
|
|
|
|
ps5169: ps5169@28 {
|
|
compatible = "parade,ps5169";
|
|
reg = <0x28>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
#include "mediatek/bat_setting/mt6886_battery_prop.dtsi"
|
|
#include "mediatek/mt6685.dtsi"
|
|
|
|
&mt6685_mfd {
|
|
mt6685_clock_buffer: mt6685_clock_buffer {
|
|
mediatek,xo-buf-support = <1 1 1 1 1> /* BBCK */,
|
|
<1 1 0> /* RFCK1 */,
|
|
<1 1 0> /* RFCK2 */,
|
|
<0 0> /* CONCK */;
|
|
mediatek,bblpm-support;
|
|
mediatek,xo-voter-support;
|
|
mediatek,dcxo-spmi-rw;
|
|
mediatek,pmrc-en-support;
|
|
clkbuf_ctl = <&clock_buffer_ctrl>;
|
|
|
|
mediatek,enable;
|
|
};
|
|
mt6685_consys: mt6685-consys {
|
|
compatible = "mediatek,mt6685-consys";
|
|
};
|
|
};
|
|
|
|
&mt6685_rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
#include "mediatek/trusty.dtsi"
|
|
#include "mediatek/cust_mt6886_msdc.dtsi"
|
|
#include "mediatek/rt5133.dtsi"
|
|
#include "mediatek/mt6363.dtsi"
|
|
#include "mediatek/mt6368.dtsi"
|
|
#include "mediatek/cust_mt6886_connfem.dtsi"
|
|
|
|
/* CONNSYS TCXO GPIO start */
|
|
&pio {
|
|
conninfra_pins_default: conninfra-pins-default {
|
|
};
|
|
conninfra_pins_tcxo_set: conninfra-tcxo-set {
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO4__FUNC_CONN_TCXOENA_REQ>;
|
|
};
|
|
};
|
|
conninfra_pins_tcxo_clr: conninfra-tcxo-clr {
|
|
pins-cmd-dat {
|
|
pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
|
|
};
|
|
};
|
|
};
|
|
/* CONNSYS TCXO GPIO end */
|
|
|
|
&rt5133 {
|
|
interrupts-extended = <&pio 157 0x0>;
|
|
enable-gpio = <&pio 156 0x0>;
|
|
};
|
|
|
|
&mt6363_vbuck1 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vbuck2 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vbuck4 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vbuck5 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vbuck6 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vsram_digrf {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vsram_modem {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vsram_cpub {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vsram_cpul {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vufs12 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vufs18 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vsram_apu {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vcn15 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vm18 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6363_vrf12 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6368_vbuck2 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6368_vbuck3 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6368_vbuck4 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6368_vbuck5 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
&mt6368_vbuck6 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
/delete-node/ &mt6363_vbuck4_sshub;
|
|
|
|
/delete-node/ &mt6363_vsram_mdfe;
|
|
|
|
/* AUDIO GPIO standardization start */
|
|
&pio {
|
|
aud_clk_mosi_off: aud-clk-mosi-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO33__FUNC_GPIO33>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO34__FUNC_GPIO34>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_clk_mosi_on: aud-clk-mosi-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO33__FUNC_AUD_CLK_MOSI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO34__FUNC_AUD_SYNC_MOSI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_mosi_off: aud-dat-mosi-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO35__FUNC_GPIO35>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_mosi_on: aud-dat-mosi-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO35__FUNC_AUD_DAT_MOSI0>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO36__FUNC_AUD_DAT_MOSI1>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_mosi_ch34_off: aud-dat-mosi-ch34-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_mosi_ch34_on: aud-dat-mosi-ch34-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO37__FUNC_AUD_DAT_MOSI2>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso0_off: aud-dat-miso0-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO40__FUNC_GPIO40>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_miso0_on: aud-dat-miso0-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO40__FUNC_AUD_DAT_MISO0>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso1_off: aud-dat-miso1-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO41__FUNC_GPIO41>;
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso1_on: aud-dat-miso1-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO41__FUNC_AUD_DAT_MISO1>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso2_off: aud-dat-miso2-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO42__FUNC_GPIO42>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_miso2_on: aud-dat-miso2-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO42__FUNC_AUD_DAT_MISO2>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
vow_dat_miso_off: vow-dat-miso-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO40__FUNC_GPIO40>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
vow_dat_miso_on: vow-dat-miso-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO40__FUNC_VOW_DAT_MISO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
vow_clk_miso_off: vow-clk-miso-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO41__FUNC_GPIO41>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
vow_clk_miso_on: vow-clk-miso-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO41__FUNC_VOW_CLK_MISO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_nle_mosi_off: aud-nle-mosi-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO38__FUNC_GPIO38>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO39__FUNC_GPIO39>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_nle_mosi_on: aud-nle-mosi-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO38__FUNC_AUD_NLE_MOSI0>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO39__FUNC_AUD_NLE_MOSI1>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_gpio_i2s0_off: aud-gpio-i2s0-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO104__FUNC_GPIO104>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_gpio_i2s0_on: aud-gpio-i2s0-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO104__FUNC_I2S0_DI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_gpio_i2s3_off: aud-gpio-i2s3-off {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO102__FUNC_GPIO102>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO103__FUNC_GPIO103>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins-cmd3-dat {
|
|
pinmux = <PINMUX_GPIO105__FUNC_GPIO105>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_gpio_i2s3_on: aud-gpio-i2s3-on {
|
|
pins-cmd1-dat {
|
|
pinmux = <PINMUX_GPIO102__FUNC_I2S3_BCK>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins-cmd2-dat {
|
|
pinmux = <PINMUX_GPIO103__FUNC_I2S3_LRCK>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins-cmd3-dat {
|
|
pinmux = <PINMUX_GPIO105__FUNC_I2S3_DO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
/* AUDIO GPIO standardization end */
|
|
|
|
#include "mediatek/mt6886-clkitg.dtsi"
|
|
#include "mediatek/mt6886-disable-unused.dtsi"
|
|
|
|
&mddriver {
|
|
/* for md pmic voltage setting*/
|
|
md-vmodem-supply = <&mt6363_vbuck6>;
|
|
md-vmodem = <800000 800000>;
|
|
md-vsram-supply = <&mt6363_vsram_modem>;
|
|
md-vsram = <800000 800000>;
|
|
md-vdigrf-supply = <&mt6363_vbuck1>;
|
|
md-vdigrf = <700000 700000>;
|
|
};
|
|
|
|
&md_auxadc {
|
|
io-channels = <&pmic_adc (ADC_PURES_OPEN_MASK | AUXADC_VIN1)>;
|
|
};
|
|
|
|
&trusty {
|
|
trusty-sapu {
|
|
compatible = "android,trusty-sapu";
|
|
iommus = <&apu_iommu0 M4U_PORT_L37_APU_CODE>;
|
|
status = "okay";
|
|
};
|
|
};
|