170 lines
4.7 KiB
C
170 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MML_MT6985_H
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#define _DT_BINDINGS_MML_MT6985_H
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/* MML engines in mt6985 */
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/* The id 0 leaves empty, do not use. */
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#define MML_MMLSYS 1
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#define MML_MUTEX 2
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#define MML_RDMA0 3
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#define MML_RDMA1 4
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#define MML_RDMA2 5
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#define MML_RDMA3 6
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#define MML_DLI0 7
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#define MML_DLI1 8
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#define MML_DLI0_SEL 9
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#define MML_DLI1_SEL 10
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#define MML_HDR0 11
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#define MML_HDR1 12
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#define MML_AAL0 13
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#define MML_AAL1 14
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#define MML_RSZ0 15
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#define MML_RSZ1 16
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#define MML_RSZ2 17
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#define MML_RSZ3 18
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#define MML_BIRSZ0 19
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#define MML_BIRSZ1 20
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#define MML_TDSHP0 21
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#define MML_TDSHP1 22
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#define MML_COLOR0 23
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#define MML_COLOR1 24
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#define MML_PQ0_SOUT 25
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#define MML_PQ1_SOUT 26
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#define MML_DLO0_SOUT 27
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#define MML_DLO1_SOUT 28
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#define MML_WROT0 29
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#define MML_WROT1 30
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#define MML_WROT2 31
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#define MML_WROT3 32
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#define MML_DLO0 33
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#define MML_DLO1 34
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#define MML_ENGINE_TOTAL 35
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/* MML component types. See mtk-mml-sys.c */
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#define MML_CT_SYS 1
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#define MML_CT_PATH 2
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#define MML_CT_DL_IN 3
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#define MML_CT_DL_OUT 4
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/* MML SYS registers */
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#define MMLSYS_MISC 0x0f0
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#define MML_CG_CON0 0x100
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#define MML_CG_SET0 0x104
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#define MML_CG_CLR0 0x108
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#define MML_CG_CON1 0x110
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#define MML_CG_SET1 0x114
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#define MML_CG_CLR1 0x118
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#define MML_CG_CON2 0x120
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#define MML_CG_SET2 0x124
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#define MML_CG_CLR2 0x128
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#define MML_CG_CON3 0x130
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#define MML_CG_SET3 0x134
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#define MML_CG_CLR3 0x138
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#define MML_CG_CON4 0x140
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#define MML_CG_SET4 0x144
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#define MML_CG_CLR4 0x148
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#define MML_SW0_RST_B 0x700
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#define MML_SW1_RST_B 0x704
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#define MML_SW2_RST_B 0x708
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#define MML_SW3_RST_B 0x70c
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#define MML_SW4_RST_B 0x710
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#define MML_EVENT_GCEM_EN 0x7f4
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#define MML_EVENT_GCED_EN 0x7f8
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#define MML_IN_LINE_READY_SEL 0x7fc
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#define MML_SMI_LARB_GREQ 0x8dc
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#define MML_BYPASS_MUX_SHADOW 0xf00
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#define MML_MOUT_RST 0xf04
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/* MML DL IN/OUT registers in mt6985 */
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#define MML_DL_IN_RELAY0_SIZE 0x220
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#define MML_DL_IN_RELAY1_SIZE 0x224
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#define MML_DL_OUT_RELAY0_SIZE 0x228
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#define MML_DL_OUT_RELAY1_SIZE 0x22c
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#define MML_DLO_ASYNC0_STATUS0 0x230
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#define MML_DLO_ASYNC0_STATUS1 0x234
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#define MML_DLO_ASYNC1_STATUS0 0x238
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#define MML_DLO_ASYNC1_STATUS1 0x23c
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#define MML_DLI_ASYNC0_STATUS0 0x240
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#define MML_DLI_ASYNC0_STATUS1 0x244
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#define MML_DLI_ASYNC1_STATUS0 0x248
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#define MML_DLI_ASYNC1_STATUS1 0x24c
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#define MML_DL_IN_RELAY2_SIZE 0x250
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#define MML_DL_IN_RELAY3_SIZE 0x254
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#define MML_DL_OUT_RELAY2_SIZE 0x258
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#define MML_DL_OUT_RELAY3_SIZE 0x25c
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#define MML_DLO_ASYNC2_STATUS0 0x260
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#define MML_DLO_ASYNC2_STATUS1 0x264
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#define MML_DLO_ASYNC3_STATUS0 0x268
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#define MML_DLO_ASYNC3_STATUS1 0x26c
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#define MML_DLI_ASYNC2_STATUS0 0x270
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#define MML_DLI_ASYNC2_STATUS1 0x274
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#define MML_DLI_ASYNC3_STATUS0 0x278
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#define MML_DLI_ASYNC3_STATUS1 0x27c
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/* MML MUX registers in mt6985 */
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#define MML_DLI0_SEL_IN 0xf14
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#define MML_DLI1_SEL_IN 0xf18
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#define MML_RDMA0_MOUT_EN 0xf20
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#define MML_RDMA1_MOUT_EN 0xf24
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#define MML_PQ0_SEL_IN 0xf30
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#define MML_PQ1_SEL_IN 0xf34
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#define MML_WROT0_SEL_IN 0xf70
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#define MML_WROT1_SEL_IN 0xf74
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#define MML_PQ0_SOUT_SEL 0xf80
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#define MML_PQ1_SOUT_SEL 0xf84
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#define MML_DLO0_SOUT_SEL 0xf88
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#define MML_DLO1_SOUT_SEL 0xf8c
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#define MML_BYP0_MOUT_EN 0xf90
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#define MML_BYP1_MOUT_EN 0xf94
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#define MML_BYP0_SEL_IN 0xf98
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#define MML_BYP1_SEL_IN 0xf9c
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#define MML_RSZ2_SEL_IN 0xfa0
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#define MML_RSZ3_SEL_IN 0xfa4
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#define MML_HDR0_SOUT_SEL 0xfa8
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#define MML_HDR1_SOUT_SEL 0xfac
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#define MML_AAL0_SEL_IN 0xf40
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#define MML_AAL1_SEL_IN 0xf44
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#define MML_TDSHP0_SOUT_SEL 0xf48
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#define MML_TDSHP1_SOUT_SEL 0xf4c
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#define MML_COLOR0_SEL_IN 0xf50
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#define MML_COLOR1_SEL_IN 0xf54
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#define MML_COLOR0_SOUT_SEL 0xf58
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#define MML_COLOR1_SOUT_SEL 0xf5c
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#define MML_TDSHP0_SEL_IN 0xf60
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#define MML_TDSHP1_SEL_IN 0xf64
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#define MML_AAL0_MOUT_EN 0xf68
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#define MML_AAL1_MOUT_EN 0xf6c
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#define MML_MOUT_MASK0 0xfd0
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#define MML_MOUT_MASK1 0xfd4
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#define MML_MOUT_MASK2 0xfd8
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/* MML AID for secure */
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#define MML_RDMA0_AIDSEL 0x500
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#define MML_RDMA1_AIDSEL 0x504
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#define MML_WROT0_AIDSEL 0x508
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#define MML_WROT1_AIDSEL 0x50C
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#define MML_WROT2_AIDSEL 0x510
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#define MML_WROT3_AIDSEL 0x514
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#define MML_FAKE0_AIDSEL 0x518
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#define MML_RDMA2_AIDSEL 0x51C
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#define MML_RDMA3_AIDSEL 0x520
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/* MMLSys debug valid/ready */
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#define MML_DL_VALID0 0xfe0
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#define MML_DL_VALID1 0xfe4
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#define MML_DL_VALID2 0xfe8
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#define MML_DL_VALID3 0xfec
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#define MML_DL_READY0 0xff0
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#define MML_DL_READY1 0xff4
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#define MML_DL_READY2 0xff8
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#define MML_DL_READY3 0xfdc
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/* MML SYS mux types. See mtk-mml-sys.c */
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#define MML_MUX_MOUT 1
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#define MML_MUX_SOUT 2
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#define MML_MUX_SLIN 3
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#endif /* _DT_BINDINGS_MML_MT6985_H */
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