636 lines
19 KiB
C
636 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6886_H
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#define _DT_BINDINGS_CLK_MT6886_H
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/* TOPCKGEN */
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#define CLK_TOP_AXI_SEL 0
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#define CLK_TOP_P_AXI_SEL 1
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#define CLK_TOP_U_HAXI_SEL 2
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#define CLK_TOP_BUS_AXIMEM_SEL 3
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#define CLK_TOP_DISP0_SEL 4
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#define CLK_TOP_MDP0_SEL 5
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#define CLK_TOP_MMINFRA_SEL 6
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#define CLK_TOP_MMUP_SEL 7
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#define CLK_TOP_DSP_SEL 8
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#define CLK_TOP_CAMTG_SEL 9
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#define CLK_TOP_CAMTG2_SEL 10
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#define CLK_TOP_CAMTG3_SEL 11
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#define CLK_TOP_CAMTG4_SEL 12
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#define CLK_TOP_CAMTG5_SEL 13
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#define CLK_TOP_CAMTG6_SEL 14
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#define CLK_TOP_UART_SEL 15
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#define CLK_TOP_SPI_SEL 16
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#define CLK_TOP_MSDC_MACRO_SEL 17
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#define CLK_TOP_MSDC30_1_SEL 18
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#define CLK_TOP_MSDC30_2_SEL 19
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#define CLK_TOP_AUDIO_SEL 20
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#define CLK_TOP_AUD_INTBUS_SEL 21
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#define CLK_TOP_ATB_SEL 22
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#define CLK_TOP_DISP_PWM_SEL 23
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#define CLK_TOP_USB_TOP_SEL 24
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#define CLK_TOP_USB_XHCI_SEL 25
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#define CLK_TOP_I2C_SEL 26
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#define CLK_TOP_SENINF_SEL 27
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#define CLK_TOP_SENINF1_SEL 28
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#define CLK_TOP_SENINF2_SEL 29
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#define CLK_TOP_SENINF3_SEL 30
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#define CLK_TOP_AUD_ENGEN1_SEL 31
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#define CLK_TOP_AUD_ENGEN2_SEL 32
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#define CLK_TOP_AES_UFSFDE_SEL 33
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#define CLK_TOP_U_SEL 34
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#define CLK_TOP_U_MBIST_SEL 35
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#define CLK_TOP_AUD_1_SEL 36
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#define CLK_TOP_AUD_2_SEL 37
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#define CLK_TOP_ADSP_SEL 38
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#define CLK_TOP_DPMAIF_MAIN_SEL 39
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#define CLK_TOP_VENC_SEL 40
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#define CLK_TOP_VDEC_SEL 41
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#define CLK_TOP_PWM_SEL 42
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#define CLK_TOP_AUDIO_H_SEL 43
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#define CLK_TOP_MCUPM_SEL 44
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#define CLK_TOP_MEM_SUB_SEL 45
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#define CLK_TOP_P_MEM_SEL 46
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#define CLK_TOP_U_MEM_SEL 47
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#define CLK_TOP_EMI_N_SEL 48
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#define CLK_TOP_DSI_OCC_SEL 49
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#define CLK_TOP_CCU_AHB_SEL 50
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#define CLK_TOP_AP2CONN_HOST_SEL 51
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#define CLK_TOP_IMG1_SEL 52
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#define CLK_TOP_IPE_SEL 53
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#define CLK_TOP_CAM_SEL 54
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#define CLK_TOP_CCUSYS_SEL 55
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#define CLK_TOP_CAMTM_SEL 56
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#define CLK_TOP_MCU_ACP_SEL 57
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#define CLK_TOP_CSI_OCC_SCAN_SEL 58
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#define CLK_TOP_IPSWEST_SEL 59
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#define CLK_TOP_IPSNORTH_SEL 60
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#define CLK_TOP_AXI_L3GIC_SEL 61
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#define CLK_TOP_APLL_I2S0_MCK_SEL 62
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#define CLK_TOP_APLL_I2S1_MCK_SEL 63
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#define CLK_TOP_APLL_I2S2_MCK_SEL 64
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#define CLK_TOP_APLL_I2S3_MCK_SEL 65
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#define CLK_TOP_APLL_I2S4_MCK_SEL 66
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#define CLK_TOP_APLL_I2S5_MCK_SEL 67
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#define CLK_TOP_APLL_I2S6_MCK_SEL 68
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#define CLK_TOP_APLL_I2S7_MCK_SEL 69
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#define CLK_TOP_APLL_I2S8_MCK_SEL 70
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#define CLK_TOP_APLL_I2S9_MCK_SEL 71
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#define CLK_TOP_APLL_ETDM_IN1_MCK_SEL 72
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#define CLK_TOP_APLL_ETDM_OUT1_MCK_SEL 73
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#define CLK_TOP_APLL12_CK_DIV0 74
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#define CLK_TOP_APLL12_CK_DIV1 75
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#define CLK_TOP_APLL12_CK_DIV2 76
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#define CLK_TOP_APLL12_CK_DIV3 77
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#define CLK_TOP_APLL12_CK_DIV4 78
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#define CLK_TOP_APLL12_CK_DIVB 79
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#define CLK_TOP_APLL12_CK_DIV5 80
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#define CLK_TOP_APLL12_CK_DIV6 81
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#define CLK_TOP_APLL12_CK_DIV7 82
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#define CLK_TOP_APLL12_CK_DIV8 83
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#define CLK_TOP_APLL12_CK_DIV9 84
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#define CLK_TOP_APLL12_CK_DIV_ETDM_IN1 85
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#define CLK_TOP_APLL12_CK_DIV_ETDM_OUT1 86
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#define CLK_TOP_CLKRTC 87
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#define CLK_TOP_TCK_26M_MX9 88
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#define CLK_TOP_F26M_CK_D2 89
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#define CLK_TOP_MMPLL_D4 90
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#define CLK_TOP_MMPLL_D4_D2 91
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#define CLK_TOP_MMPLL_D5_D2 92
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#define CLK_TOP_MMPLL_D6 93
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#define CLK_TOP_MMPLL_D6_D2 94
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#define CLK_TOP_MMPLL_D7 95
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#define CLK_TOP_MMPLL_D9 96
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#define CLK_TOP_MAINPLL_D3 97
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#define CLK_TOP_MAINPLL_D4 98
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#define CLK_TOP_MAINPLL_D4_D2 99
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#define CLK_TOP_MAINPLL_D4_D4 100
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#define CLK_TOP_MAINPLL_D4_D8 101
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#define CLK_TOP_MAINPLL_D4_D16 102
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#define CLK_TOP_MAINPLL_D5 103
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#define CLK_TOP_MAINPLL_D5_D2 104
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#define CLK_TOP_MAINPLL_D5_D4 105
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#define CLK_TOP_MAINPLL_D5_D8 106
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#define CLK_TOP_MAINPLL_D6 107
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#define CLK_TOP_MAINPLL_D6_D2 108
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#define CLK_TOP_MAINPLL_D6_D4 109
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#define CLK_TOP_MAINPLL_D7 110
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#define CLK_TOP_MAINPLL_D7_D2 111
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#define CLK_TOP_MAINPLL_D7_D4 112
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#define CLK_TOP_MAINPLL_D7_D8 113
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#define CLK_TOP_MAINPLL_D9 114
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#define CLK_TOP_UNIVPLL_D3 115
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#define CLK_TOP_UNIVPLL_D4 116
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#define CLK_TOP_UNIVPLL_D4_D2 117
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#define CLK_TOP_UNIVPLL_D4_D4 118
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#define CLK_TOP_UNIVPLL_D4_D8 119
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#define CLK_TOP_UNIVPLL_D5 120
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#define CLK_TOP_UNIVPLL_D5_D2 121
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#define CLK_TOP_UNIVPLL_D5_D4 122
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#define CLK_TOP_UNIVPLL_D6 123
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#define CLK_TOP_UNIVPLL_D6_D2 124
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#define CLK_TOP_UNIVPLL_D6_D4 125
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#define CLK_TOP_UNIVPLL_D6_D8 126
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#define CLK_TOP_UNIVPLL_D6_D16 127
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#define CLK_TOP_UNIVPLL_D7 128
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#define CLK_TOP_UNIVPLL_D7_D2 129
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#define CLK_TOP_UNIVPLL_192M 130
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#define CLK_TOP_UNIVPLL_192M_D2 131
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#define CLK_TOP_UNIVPLL_192M_D4 132
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#define CLK_TOP_UNIVPLL_192M_D8 133
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#define CLK_TOP_UNIVPLL_192M_D10 134
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#define CLK_TOP_UNIVPLL_192M_D16 135
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#define CLK_TOP_UNIVPLL_192M_D32 136
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#define CLK_TOP_MSDCPLL 137
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#define CLK_TOP_MSDCPLL_D2 138
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#define CLK_TOP_APLL1 139
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#define CLK_TOP_APLL1_D2 140
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#define CLK_TOP_APLL1_D4 141
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#define CLK_TOP_APLL1_D8 142
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#define CLK_TOP_APLL2 143
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#define CLK_TOP_APLL2_D2 144
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#define CLK_TOP_APLL2_D4 145
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#define CLK_TOP_APLL2_D8 146
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#define CLK_TOP_ADSPPLL 147
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#define CLK_TOP_EMIPLL 148
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#define CLK_TOP_IMGPLL_D2 149
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#define CLK_TOP_IMGPLL_D5 150
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#define CLK_TOP_UFSPLL_D2 151
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#define CLK_TOP_OSC 152
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#define CLK_TOP_ULPOSC 153
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#define CLK_TOP_OSC_D2 154
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#define CLK_TOP_OSC_D2P5 155
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#define CLK_TOP_OSC_D3 156
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#define CLK_TOP_OSC_D4 157
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#define CLK_TOP_OSC_D5 158
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#define CLK_TOP_OSC_D7 159
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#define CLK_TOP_OSC_D8 160
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#define CLK_TOP_OSC_D16 161
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#define CLK_TOP_OSC_D10 162
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#define CLK_TOP_OSC_D20 163
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#define CLK_TOP_OSC2_D4 164
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#define CLK_TOP_F26M 165
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#define CLK_TOP_AXI 166
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#define CLK_TOP_P_AXI 167
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#define CLK_TOP_DISP0 168
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#define CLK_TOP_MDP0 169
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#define CLK_TOP_MMINFRA 170
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#define CLK_TOP_DSP 171
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#define CLK_TOP_UART 172
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#define CLK_TOP_SPI 173
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#define CLK_TOP_MSDC30_1 174
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#define CLK_TOP_AUDIO 175
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#define CLK_TOP_AUD_INTBUS 176
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#define CLK_TOP_DISP_PWM 177
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#define CLK_TOP_USB_TOP 178
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#define CLK_TOP_USB_XHCI 179
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#define CLK_TOP_I2C 180
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#define CLK_TOP_AUD_ENGEN1 181
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#define CLK_TOP_AUD_ENGEN2 182
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#define CLK_TOP_AES_UFSFDE 183
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#define CLK_TOP_UFS 184
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#define CLK_TOP_AUD_1 185
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#define CLK_TOP_DPMAIF_MAIN 186
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#define CLK_TOP_VENC 187
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#define CLK_TOP_VDEC 188
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#define CLK_TOP_PWM 189
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#define CLK_TOP_AUDIO_H 190
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#define CLK_TOP_CCU_AHB 191
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#define CLK_TOP_IMG1 192
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#define CLK_TOP_IPE 193
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#define CLK_TOP_CAM 194
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#define CLK_TOP_CCUSYS 195
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#define CLK_TOP_CAMTM 196
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#define CLK_TOP_IMGAVS 197
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#define CLK_TOP_I2C_PSEUDO 198
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#define CLK_TOP_ARMPLL_DIVIDER_PLL1_CK_EN 199
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#define CLK_TOP_ARMPLL_DIVIDER_PLL2_CK_EN 200
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#define CLK_TOP_U_SAP_CFG_CK_EN 201
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#define CLK_TOP_MD_32K 202
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#define CLK_TOP_NR_CLK 203
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/* INFRACFG_AO */
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#define CLK_IFRAO_I2C_DUMMY 0
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#define CLK_IFRAO_THERM 1
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#define CLK_IFRAO_CQ_DMA_FPC 2
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#define CLK_IFRAO_CCIF1_AP 3
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#define CLK_IFRAO_CCIF1_MD 4
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#define CLK_IFRAO_CCIF_AP 5
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#define CLK_IFRAO_CCIF_MD 6
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#define CLK_IFRAO_CLDMA_BCLK 7
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#define CLK_IFRAO_CQ_DMA 8
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#define CLK_IFRAO_CCIF5_MD 9
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#define CLK_IFRAO_CCIF2_AP 10
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#define CLK_IFRAO_CCIF2_MD 11
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#define CLK_IFRAO_DPMAIF_MAIN 12
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#define CLK_IFRAO_CCIF4_MD 13
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#define CLK_IFRAO_RG_MMW_DPMAIF26M 14
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#define CLK_IFRAO_NR_CLK 15
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/* APMIXEDSYS */
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#define CLK_APMIXED_MAINPLL 0
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#define CLK_APMIXED_UNIVPLL 1
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#define CLK_APMIXED_MSDCPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_ADSPPLL 4
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#define CLK_APMIXED_UFSPLL 5
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#define CLK_APMIXED_APLL1 6
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#define CLK_APMIXED_APLL2 7
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#define CLK_APMIXED_MPLL 8
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#define CLK_APMIXED_EMIPLL 9
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#define CLK_APMIXED_IMGPLL 10
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#define CLK_APMIXED_NR_CLK 11
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/* PERICFG_AO */
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#define CLK_PERAO_UART0 0
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#define CLK_PERAO_UART1 1
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#define CLK_PERAO_PWM_H 2
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#define CLK_PERAO_PWM_B 3
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#define CLK_PERAO_PWM_FB1 4
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#define CLK_PERAO_PWM_FB2 5
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#define CLK_PERAO_PWM_FB3 6
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#define CLK_PERAO_PWM_FB4 7
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#define CLK_PERAO_BTIF_B 8
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#define CLK_PERAO_DISP_PWM0 9
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#define CLK_PERAO_SPI0_B 10
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#define CLK_PERAO_SPI1_B 11
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#define CLK_PERAO_SPI2_B 12
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#define CLK_PERAO_SPI3_B 13
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#define CLK_PERAO_SPI4_B 14
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#define CLK_PERAO_SPI5_B 15
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#define CLK_PERAO_SPI6_B 16
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#define CLK_PERAO_SPI7_B 17
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#define CLK_PERAO_APDMA 18
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#define CLK_PERAO_USB_SYS 19
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#define CLK_PERAO_USB_XHCI 20
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#define CLK_PERAO_USB_BUS 21
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#define CLK_PERAO_MSDC1 22
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#define CLK_PERAO_MSDC1_H 23
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#define CLK_PERAO_AUDIO_SLV_CKP 24
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#define CLK_PERAO_AUDIO_MST_CKP 25
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#define CLK_PERAO_INTBUS_CKP 26
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#define CLK_PERAO_AUDIO_MST_IDLE_EN 27
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#define CLK_PERAO_NR_CLK 28
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/* AFE */
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#define CLK_AFE_AFE 0
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#define CLK_AFE_22M 1
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#define CLK_AFE_24M 2
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#define CLK_AFE_APLL2_TUNER 3
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#define CLK_AFE_APLL_TUNER 4
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#define CLK_AFE_TDM 5
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#define CLK_AFE_ADC 6
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#define CLK_AFE_DAC 7
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#define CLK_AFE_DAC_PREDIS 8
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#define CLK_AFE_TML 9
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#define CLK_AFE_NLE 10
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#define CLK_AFE_GENERAL3_ASRC 11
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#define CLK_AFE_CONNSYS_I2S_ASRC 12
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#define CLK_AFE_GENERAL1_ASRC 13
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#define CLK_AFE_GENERAL2_ASRC 14
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#define CLK_AFE_DAC_HIRES 15
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#define CLK_AFE_ADC_HIRES 16
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#define CLK_AFE_ADC_HIRES_TML 17
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#define CLK_AFE_ADDA6_ADC 18
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#define CLK_AFE_ADDA6_ADC_HIRES 19
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#define CLK_AFE_3RD_DAC 20
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#define CLK_AFE_3RD_DAC_PREDIS 21
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#define CLK_AFE_3RD_DAC_TML 22
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#define CLK_AFE_3RD_DAC_HIRES 23
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#define CLK_AFE_I2S5_BCLK 24
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#define CLK_AFE_I2S6_BCLK 25
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#define CLK_AFE_I2S7_BCLK 26
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#define CLK_AFE_I2S8_BCLK 27
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#define CLK_AFE_I2S9_BCLK 28
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#define CLK_AFE_ETDM_IN0_BCLK 29
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#define CLK_AFE_ETDM_OUT0_BCLK 30
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#define CLK_AFE_I2S1_BCLK 31
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#define CLK_AFE_I2S2_BCLK 32
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#define CLK_AFE_I2S3_BCLK 33
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#define CLK_AFE_I2S4_BCLK 34
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#define CLK_AFE_ETDM_IN1_BCLK 35
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#define CLK_AFE_ETDM_OUT1_BCLK 36
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#define CLK_AFE_NR_CLK 37
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/* IMP_IIC_WRAP_C */
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#define CLK_IMPC_I2C5 0
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#define CLK_IMPC_I2C6 1
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#define CLK_IMPC_I2C10 2
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#define CLK_IMPC_I2C11 3
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#define CLK_IMPC_NR_CLK 4
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/* UFSCFG_AO */
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#define CLK_UFSAO_UNIPRO_TX_SYM 0
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#define CLK_UFSAO_UNIPRO_RX_SYM0 1
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#define CLK_UFSAO_UNIPRO_RX_SYM1 2
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#define CLK_UFSAO_UNIPRO_SYS 3
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#define CLK_UFSAO_UNIPRO_PHY_SAP 4
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#define CLK_UFSAO_NR_CLK 5
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/* UFSCFG_PDN */
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#define CLK_UFSPDN_UFSHCI_UFS 0
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#define CLK_UFSPDN_UFSHCI_AES 1
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#define CLK_UFSPDN_NR_CLK 2
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/* IMP_IIC_WRAP_ES */
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#define CLK_IMPES_I2C2 0
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#define CLK_IMPES_I2C4 1
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#define CLK_IMPES_I2C9 2
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#define CLK_IMPES_NR_CLK 3
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/* IMP_IIC_WRAP_W */
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#define CLK_IMPW_I2C0 0
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#define CLK_IMPW_I2C1 1
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#define CLK_IMPW_NR_CLK 2
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/* IMP_IIC_WRAP_E */
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#define CLK_IMPE_I2C3 0
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#define CLK_IMPE_I2C7 1
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#define CLK_IMPE_I2C8 2
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#define CLK_IMPE_NR_CLK 3
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/* MFGPLL_PLL_CTRL */
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#define CLK_MFG_AO_MFGPLL 0
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#define CLK_MFG_AO_NR_CLK 1
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/* MFGSCPLL_PLL_CTRL */
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#define CLK_MFGSC_AO_MFGSCPLL 0
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#define CLK_MFGSC_AO_NR_CLK 1
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/* DISPSYS_CONFIG */
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#define CLK_MM_DISP_MUTEX0 0
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#define CLK_MM_DISP_OVL0 1
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#define CLK_MM_DISP_MERGE0 2
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#define CLK_MM_DISP_FAKE_ENG0 3
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#define CLK_MM_INLINEROT0 4
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#define CLK_MM_DISP_WDMA0 5
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#define CLK_MM_DISP_FAKE_ENG1 6
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#define CLK_MM_DISP_OVL0_2L_NW 7
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#define CLK_MM_DISP_RDMA0 8
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#define CLK_MM_DISP_RDMA1 9
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#define CLK_MM_DISP_RSZ0 10
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#define CLK_MM_DISP_COLOR0 11
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#define CLK_MM_DISP_CCORR0 12
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#define CLK_MM_DISP_CCORR1 13
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#define CLK_MM_DISP_AAL0 14
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#define CLK_MM_DISP_GAMMA0 15
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#define CLK_MM_DISP_POSTMASK0 16
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#define CLK_MM_DISP_DITHER0 17
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#define CLK_MM_DISP_CM0 18
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#define CLK_MM_DISP_SPR0 19
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#define CLK_MM_DISP_DSC_WRAP0 20
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#define CLK_MM_FMM_DISP_DSI0 21
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#define CLK_MM_DISP_UFBC_WDMA0 22
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#define CLK_MM_DISP_WDMA1 23
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#define CLK_MM_APB_BUS 24
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#define CLK_MM_DISP_C3D0 25
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#define CLK_MM_DISP_Y2R0 26
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#define CLK_MM_DISP_CHIST0 27
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#define CLK_MM_DISP_CHIST1 28
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#define CLK_MM_DISP_OVL0_2L 29
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#define CLK_MM_DISP_DLI_ASYNC3 30
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#define CLK_MM_DISP_DLO_ASYNC3 31
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#define CLK_MM_DISP_OVL1_2L 32
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#define CLK_MM_DISP_OVL1_2L_NW 33
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#define CLK_MM_SMI_COMMON 34
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#define CLK_MM_DISP_DSI0 35
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#define CLK_MM_SIG_EMI 36
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#define CLK_MM_NR_CLK 37
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/* IMGSYS_MAIN */
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#define CLK_IMG_FDVT 0
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#define CLK_IMG_ME 1
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#define CLK_IMG_MMG 2
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#define CLK_IMG_LARB12 3
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#define CLK_IMG_LARB9 4
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#define CLK_IMG_TRAW0 5
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#define CLK_IMG_TRAW1 6
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#define CLK_IMG_VCORE_GALS 7
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#define CLK_IMG_DIP0 8
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#define CLK_IMG_WPE0 9
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#define CLK_IMG_IPE 10
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#define CLK_IMG_WPE1 11
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#define CLK_IMG_WPE2 12
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#define CLK_IMG_AVS 13
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#define CLK_IMG_GALS 14
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#define CLK_IMG_NR_CLK 15
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/* DIP_TOP_DIP1 */
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#define CLK_DIP_TOP_DIP1_LARB10 0
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#define CLK_DIP_TOP_DIP1_DIP_TOP 1
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#define CLK_DIP_TOP_DIP1_NR_CLK 2
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/* DIP_NR1_DIP1 */
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#define CLK_DIP_NR1_DIP1_LARB 0
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#define CLK_DIP_NR1_DIP1_DIP_NR1 1
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#define CLK_DIP_NR1_DIP1_NR_CLK 2
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/* DIP_NR2_DIP1 */
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#define CLK_DIP_NR2_DIP1_LARB15 0
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#define CLK_DIP_NR2_DIP1_DIP_NR 1
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#define CLK_DIP_NR2_DIP1_NR_CLK 2
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/* WPE1_DIP1 */
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#define CLK_WPE1_DIP1_LARB11 0
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#define CLK_WPE1_DIP1_WPE 1
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#define CLK_WPE1_DIP1_NR_CLK 2
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/* WPE2_DIP1 */
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#define CLK_WPE2_DIP1_LARB11 0
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#define CLK_WPE2_DIP1_WPE 1
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#define CLK_WPE2_DIP1_NR_CLK 2
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/* WPE3_DIP1 */
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#define CLK_WPE3_DIP1_LARB11 0
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#define CLK_WPE3_DIP1_WPE 1
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#define CLK_WPE3_DIP1_NR_CLK 2
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/* TRAW_DIP1 */
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#define CLK_TRAW_DIP1_LARB28 0
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#define CLK_TRAW_DIP1_TRAW 1
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#define CLK_TRAW_DIP1_NR_CLK 2
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/* VDEC_GCON_BASE */
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#define CLK_VDE2_LARB1_CKEN 0
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#define CLK_VDE2_LAT_CKEN 1
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#define CLK_VDE2_LAT_ACTIVE 2
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#define CLK_VDE2_MINI_MDP_EN 3
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#define CLK_VDE2_VDEC_CKEN 4
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#define CLK_VDE2_VDEC_ACTIVE 5
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#define CLK_VDE2_NR_CLK 6
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/* VENC_GCON */
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#define CLK_VEN_CKE0_LARB 0
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#define CLK_VEN_CKE1_VENC 1
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#define CLK_VEN_CKE2_JPGENC 2
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#define CLK_VEN_CKE5_GALS 3
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#define CLK_VEN_CKE6_GALS_SRAM 4
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#define CLK_VEN_NR_CLK 5
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/* VLP_CKSYS */
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#define CLK_VLP_CK_SCP_VLP_SEL 0
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#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1
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#define CLK_VLP_CK_26M_GPT_VLP_SEL 2
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#define CLK_VLP_CK_DXCC_VLP_SEL 3
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#define CLK_VLP_CK_SPMI_P_MST_SEL 4
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#define CLK_VLP_CK_SPMI_M_MST_SEL 5
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#define CLK_VLP_CK_DVFSRC_SEL 6
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#define CLK_VLP_CK_PWM_VLP_SEL 7
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#define CLK_VLP_CK_AXI_VLP_SEL 8
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#define CLK_VLP_CK_DBG_26M_VLP_SEL 9
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#define CLK_VLP_CK_STMR26M_VLP_SEL 10
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#define CLK_VLP_CK_SSPM_VLP_SEL 11
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#define CLK_VLP_CK_SSPM_F26M_SEL 12
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#define CLK_VLP_CK_SRCK_SEL 13
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#define CLK_VLP_CK_SCP_SPI_SEL 14
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#define CLK_VLP_CK_SCP_IIC_SEL 15
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#define CLK_VLP_CK_PSVLP_SEL 16
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#define CLK_VLP_CK_NR_CLK 17
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/* SCP */
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#define CLK_SCP_SPI0 0
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#define CLK_SCP_SPI1 1
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#define CLK_SCP_SPI2 2
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#define CLK_SCP_SPI3 3
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#define CLK_SCP_SET_SPI0 4
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#define CLK_SCP_SET_SPI1 5
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#define CLK_SCP_SET_SPI2 6
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#define CLK_SCP_SET_SPI3 7
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#define CLK_SCP_NR_CLK 8
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/* SCP_IIC */
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#define CLK_SCP_IIC_I2C0 0
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#define CLK_SCP_IIC_I2C1 1
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#define CLK_SCP_IIC_I2C2 2
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#define CLK_SCP_IIC_I2C3 3
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#define CLK_SCP_IIC_I2C4 4
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#define CLK_SCP_IIC_I2C5 5
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#define CLK_SCP_IIC_I2C6 6
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#define CLK_SCP_IIC_NR_CLK 7
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/* CAMSYS_MAIN */
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#define CLK_CAM_MAIN_LARB13_CON_0 0
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#define CLK_CAM_MAIN_LARB14_CON_0 1
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#define CLK_CAM_MAIN_LARB27_CON_0 2
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#define CLK_CAM_MAIN_LARB29_CON_0 3
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#define CLK_CAM_MAIN_CAM_CON_0 4
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#define CLK_CAM_MAIN_CAM_SUBA_CON_0 5
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#define CLK_CAM_MAIN_CAM_SUBB_CON_0 6
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#define CLK_CAM_MAIN_CAM_SUBC_CON_0 7
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#define CLK_CAM_MAIN_CAM_MRAW_CON_0 8
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#define CLK_CAM_MAIN_CAMTG_CON_0 9
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#define CLK_CAM_MAIN_SENINF_CON_0 10
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#define CLK_CAM_MAIN_CAMSV_TOP_CON_0 11
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#define CLK_CAM_MAIN_ADLRD_CON_0 12
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#define CLK_CAM_MAIN_ADLWR_CON_0 13
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#define CLK_CAM_MAIN_UISP_CON_0 14
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#define CLK_CAM_MAIN_FAKE_ENG_CON_0 15
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#define CLK_CAM_MAIN_CAM2MM0_GALS_CON_0 16
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#define CLK_CAM_MAIN_CAM2MM1_GALS_CON_0 17
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#define CLK_CAM_MAIN_CAM2SYS_GALS_CON_0 18
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#define CLK_CAM_MAIN_CAM2MM2_GALS_CON_0 19
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#define CLK_CAM_MAIN_CCUSYS_CON_0 20
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#define CLK_CAM_MAIN_IPS_CON_0 21
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#define CLK_CAM_MAIN_CAMSV_A_CON_1 22
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#define CLK_CAM_MAIN_CAMSV_B_CON_1 23
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#define CLK_CAM_MAIN_CAMSV_C_CON_1 24
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#define CLK_CAM_MAIN_CAMSV_D_CON_1 25
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#define CLK_CAM_MAIN_CAMSV_E_CON_1 26
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#define CLK_CAM_MAIN_CAMSV_CON_1 27
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#define CLK_CAM_M_NR_CLK 28
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/* CAMSYS_RAWA */
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#define CLK_CAM_RA_LARBX 0
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#define CLK_CAM_RA_CAM 1
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#define CLK_CAM_RA_CAMTG 2
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#define CLK_CAM_RA_NR_CLK 3
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/* CAMSYS_YUVA */
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#define CLK_CAM_YA_LARBX 0
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#define CLK_CAM_YA_CAM 1
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#define CLK_CAM_YA_CAMTG 2
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#define CLK_CAM_YA_NR_CLK 3
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/* CAMSYS_RAWB */
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#define CLK_CAM_RB_LARBX 0
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#define CLK_CAM_RB_CAM 1
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#define CLK_CAM_RB_CAMTG 2
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#define CLK_CAM_RB_NR_CLK 3
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/* CAMSYS_YUVB */
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#define CLK_CAM_YB_LARBX 0
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#define CLK_CAM_YB_CAM 1
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#define CLK_CAM_YB_CAMTG 2
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#define CLK_CAM_YB_NR_CLK 3
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/* CAMSYS_MRAW */
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#define CLK_CAM_MR_LARBX 0
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#define CLK_CAM_MR_CAMTG 1
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#define CLK_CAM_MR_MRAW0 2
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#define CLK_CAM_MR_MRAW1 3
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#define CLK_CAM_MR_MRAW2 4
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#define CLK_CAM_MR_MRAW3 5
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#define CLK_CAM_MR_PDA0 6
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#define CLK_CAM_MR_PDA1 7
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#define CLK_CAM_MR_NR_CLK 8
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/* CCU_MAIN */
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#define CLK_CCU_LARB19 0
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#define CLK_CCU_AHB 1
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#define CLK_CCUSYS_CCU0 2
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#define CLK_CCUSYS_DPE 3
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#define CLK_CCU_NR_CLK 4
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/* MMINFRA_CONFIG */
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#define CLK_MMINFRA_GCE_D 0
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#define CLK_MMINFRA_GCE_M 1
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#define CLK_MMINFRA_GCE_26M 2
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#define CLK_MMINFRA_CONFIG_NR_CLK 3
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/* MDPSYS_CONFIG */
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#define CLK_MDP_MUTEX0 0
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#define CLK_MDP_APB_BUS 1
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#define CLK_MDP_SMI0 2
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#define CLK_MDP_RDMA0 3
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#define CLK_MDP_HDR0 4
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#define CLK_MDP_AAL0 5
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#define CLK_MDP_RSZ0 6
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#define CLK_MDP_TDSHP0 7
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#define CLK_MDP_COLOR0 8
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#define CLK_MDP_WROT0 9
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#define CLK_MDP_FAKE_ENG0 10
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#define CLK_MDP_DL_RELAY0 11
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#define CLK_MDP_DL_RELAY1 12
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#define CLK_MDP_RDMA1 13
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#define CLK_MDP_HDR1 14
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#define CLK_MDP_AAL1 15
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#define CLK_MDP_RSZ1 16
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#define CLK_MDP_TDSHP1 17
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#define CLK_MDP_COLOR1 18
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#define CLK_MDP_WROT1 19
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#define CLK_MDP_DLO_ASYNC0 20
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#define CLK_MDP_DLO_ASYNC1 21
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#define CLK_MDP_HRE_TOP_MDPSYS 22
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#define CLK_MDP_NR_CLK 23
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/* CCIPLL_PLL_CTRL */
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#define CLK_CCIPLL 0
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#define CLK_CCI_NR_CLK 1
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/* ARMPLL_LL_PLL_CTRL */
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#define CLK_CPU_LL_ARMPLL_LL 0
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#define CLK_CPU_LL_NR_CLK 1
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/* ARMPLL_BL_PLL_CTRL */
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#define CLK_CPU_BL_ARMPLL_BL 0
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#define CLK_CPU_BL_NR_CLK 1
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/* PTPPLL_PLL_CTRL */
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#define CLK_PTPPLL 0
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#define CLK_PTP_NR_CLK 1
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#endif /* _DT_BINDINGS_CLK_MT6886_H */
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