52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Anthony Huang <anthony.huang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MMDVFS_CLK_H
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#define _DT_BINDINGS_MMDVFS_CLK_H
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/* clock consumer */
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#define CLK_MMDVFS_DISP (0)
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#define CLK_MMDVFS_MDP (1)
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#define CLK_MMDVFS_MML (2)
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#define CLK_MMDVFS_SMI_COMMON0 (3)
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#define CLK_MMDVFS_SMI_COMMON1 (4)
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#define CLK_MMDVFS_VENC (5)
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#define CLK_MMDVFS_JPEGENC (6)
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#define CLK_MMDVFS_VDEC (7)
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#define CLK_MMDVFS_VFMT (8)
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#define CLK_MMDVFS_JPEGDEC (9)
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#define CLK_MMDVFS_IMG (10)
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#define CLK_MMDVFS_IPE (11)
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#define CLK_MMDVFS_CAM (12)
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#define CLK_MMDVFS_CCU (13)
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#define CLK_MMDVFS_AOV (14)
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#define CLK_MMDVFS_VCORE (15)
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#define CLK_MMDVFS_VMM (16)
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#define CLK_MMDVFS_VDISP (17)
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/* new clk append here */
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#define CLK_MMDVFS_NUM (18)
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/* power supplier */
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#define PWR_MMDVFS_VCORE (0)
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#define PWR_MMDVFS_VMM (1)
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#define PWR_MMDVFS_VDISP (2)
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#define PWR_MMDVFS_NUM (3)
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/* ipi type */
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#define IPI_MMDVFS_VCP (0)
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#define IPI_MMDVFS_CCU (1)
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/* spec type */
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#define SPEC_MMDVFS_NORMAL (0)
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#define SPEC_MMDVFS_ALONE (1)
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#define SPEC_MMDVFS_DVFSRC (2)
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#endif /* _DT_BINDINGS_MMDVFS_CLK_H */
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