81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __RPOC_MTK_CCU_IPS7_H
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#define __RPOC_MTK_CCU_IPS7_H
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#include <linux/kernel.h>
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#include <linux/remoteproc.h>
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#include <linux/wait.h>
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#include <linux/types.h>
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#include "mtk_ccu_common.h"
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#define MTK_CCU_CORE_PMEM_BASE (0x00000000)
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#define MTK_CCU_CORE_DMEM_BASE (0x00020000)
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#define MTK_CCU_PMEM_BASE (0x1B000000)
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#define MTK_CCU_DMEM_BASE (0x1B020000)
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#define MTK_CCU_PMEM_SIZE (0x20000)
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#define MTK_CCU_DMEM_SIZE (0x20000)
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#define MTK_CCU_ISR_LOG_SIZE (0x400)
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#define MTK_CCU_LOG_SIZE (0x800)
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#define MTK_CCU_CACHE_SIZE (0)
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#define MTK_CCU_CACHE_BASE (0x40000000)
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#define MTK_CCU_SHARED_BUF_OFFSET 0 //at DCCM start
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#define MTK_CCU_BASE_MASK (0xFFF00000)
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#define MTK_CCU_REG_RESET (0x0)
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#define MTK_CCU_HW_RESET_BIT (0x000d0100)
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#define MTK_CCU_REG_CTRL (0x0c)
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#define MTK_CCU_REG_AXI_REMAP (0x24)
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#define MTK_CCU_REG_CORE_CTRL (0x28)
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#define MTK_CCU_RUN_BIT (0x00000010)
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#define MTK_CCU_REG_CORE_STATUS (0x28)
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#define MTK_CCU_INT_TRG (0x8010) // (0x2C)
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#define MTK_CCU_INT_CLR (0x5C)
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#define MTK_CCU_INT_CLR_EXCH (0x80A4)
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#define MTK_CCU_INT_ST (0x60)
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#define MTK_CCU_MON_ST (0x78)
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#define MTK_CCU_SPARE_REG00 (0x8020)
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#define MTK_CCU_SPARE_REG01 (0x8024)
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#define MTK_CCU_SPARE_REG02 (0x8028)
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#define MTK_CCU_SPARE_REG03 (0x802C)
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#define MTK_CCU_SPARE_REG04 (0x8030)
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#define MTK_CCU_SPARE_REG05 (0x8034)
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#define MTK_CCU_SPARE_REG06 (0x8038)
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#define MTK_CCU_SPARE_REG07 (0x803C)
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#define MTK_CCU_SPARE_REG08 (0x8040)
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#define MTK_CCU_SPARE_REG09 (0x8044)
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#define MTK_CCU_SPARE_REG10 (0x8048)
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#define MTK_CCU_SPARE_REG11 (0x804C)
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#define MTK_CCU_SPARE_REG12 (0x8050)
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#define MTK_CCU_SPARE_REG13 (0x8054)
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#define MTK_CCU_SPARE_REG14 (0x8058)
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#define MTK_CCU_SPARE_REG15 (0x805C)
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#define MTK_CCU_SPARE_REG16 (0x8060)
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#define MTK_CCU_SPARE_REG17 (0x8064)
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#define MTK_CCU_SPARE_REG18 (0x8068)
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#define MTK_CCU_SPARE_REG19 (0x806C)
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#define MTK_CCU_SPARE_REG20 (0x8070)
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#define MTK_CCU_SPARE_REG21 (0x8074)
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#define MTK_CCU_SPARE_REG22 (0x8078)
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#define MTK_CCU_SPARE_REG23 (0x807C)
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#define MTK_CCU_SPARE_REG24 (0x8080)
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#define MTK_CCU_SPARE_REG25 (0x8084)
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#define MTK_CCU_SPARE_REG26 (0x8088)
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#define MTK_CCU_SPARE_REG27 (0x808C)
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#define MTK_CCU_SPARE_REG28 (0x8090)
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#define MTK_CCU_SPARE_REG29 (0x8094)
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#define MTK_CCU_SPARE_REG30 (0x8098)
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#define MTK_CCU_SPARE_REG31 (0x809C)
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#define CCU_STATUS_INIT_DONE 0xffff0000
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#define CCU_STATUS_INIT_DONE_2 0xffff00a5
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#define CCU_GO_TO_LOAD 0x10AD10AD
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#define CCU_GO_TO_RUN 0x17172ACE
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#define CCU_GO_TO_STOP 0x8181DEAD
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#endif //__RPOC_MTK_CCU_IPS7_H
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