301 lines
12 KiB
C
301 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_SLBC_SRAM_H__
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#define __MTK_SLBC_SRAM_H__
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/*
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* BIT Operation
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*/
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#define SLBC_BIT(_bit_) \
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((unsigned int)(1U << (_bit_)))
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#define SLBC_BITMASK(_bits_) \
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(((unsigned int) -1 >> (31 - ((1) ? _bits_))) & \
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~((1U << ((0) ? _bits_)) - 1))
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#define SLBC_BITS(_bits_, _val_) \
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(SLBC_BITMASK(_bits_) & \
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((_val_) << ((0) ? _bits_)))
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#define SLBC_GET_BITS_VAL_0(_bits_, _val_) \
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(((_val_) & (SLBC_BITMASK(_bits_))) >> ((0) ? _bits_))
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#define SLBC_NAME_VAL(_name_, _val_) \
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(_val_ << _name_##_SHIFT)
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#define SLBC_GET_NAME_VAL(_reg_val_, _name_) \
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((_reg_val_) & (_name_##_MASK))
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#define SLBC_GET_NAME_VAL_0(_reg_val_, _name_) \
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(((_reg_val_) & (_name_##_MASK)) >> _name_##_SHIFT)
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#define SLBC_SET_NAME_VAL(_reg_val_, _name_, _val_) \
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(((_reg_val_) & ~(_name_##_MASK)) | \
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((_val_ << _name_##_SHIFT) & (_name_##_MASK)))
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#define SLBC_UID_USED 0x0
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#define SLBC_SID_MASK 0x4
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#define SLBC_SID_REQ_Q 0x8
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#define SLBC_SID_REL_Q 0xC
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#define SLBC_SLOT_USED 0x10
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#define SLBC_FORCE 0x14
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#define SLBC_BUFFER_REF 0x18
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#define SLBC_REF 0x1C
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#define SLBC_DEBUG_0 0x20
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#define SLBC_DEBUG_1 0x24
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#define SLBC_DEBUG_2 0x28
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#define SLBC_DEBUG_3 0x2C
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#define SLBC_DEBUG_4 0x30
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#define SLBC_DEBUG_5 0x34
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#define SLBC_DEBUG_6 0x38
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#define SLBC_DEBUG_7 0x3C
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#define SLBC_APU_BW 0x40
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#define SLBC_MM_BW 0x44
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#define SLBC_MM_EST_BW 0x48
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#define SLBC_CACHE_USED 0x4C
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#define SLBC_PMU_0 0x50
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#define SLBC_PMU_1 0x54
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#define SLBC_PMU_2 0x58
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#define SLBC_PMU_3 0x5C
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#define SLBC_PMU_4 0x60
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#define SLBC_PMU_5 0x64
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#define SLBC_PMU_6 0x68
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#define SLBC_SCMI_AP 0x6C
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#define SLBC_SCMI_SSPM 0x70
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#define SLBC_SCMI_RET1 0x74
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#define SLBC_SCMI_RET2 0x78
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#define SLBC_SCMI_RET3 0x7C
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#define SLBC_SRAM_CON 0x80
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#define SLBC_L3CTL 0x84
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#define SLBC_CPU_DEBUG0 0x88
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#define SLBC_CPU_DEBUG1 0x8C
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#define SLBC_STA 0x90
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#define SLBC_ACK_C 0x94
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#define SLBC_ACK_G 0x98
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#define CPUQOS_MODE 0x9C
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#define SLBC_DEBUG_8 0xA0
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#define SLBC_DEBUG_9 0xA4
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#define SLBC_DEBUG_10 0xA8
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#define SLBC_DEBUG_11 0xAC
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#define SLBC_DEBUG_12 0xB0
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#define SLBC_DEBUG_13 0xB4
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#define SLBC_DEBUG_14 0xB8
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#define SLBC_DEBUG_15 0xBC
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/* SLBC_UID_USED */
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#define SLBC_UID_USED_STA_LSB SLBC_BIT(0)
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#define SLBC_UID_USED_STA_SHIFT 0
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#define SLBC_UID_USED_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_SID_MASK */
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#define SLBC_SID_MASK_STA_LSB SLBC_BIT(0)
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#define SLBC_SID_MASK_STA_SHIFT 0
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#define SLBC_SID_MASK_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_SID_REQ_Q */
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#define SLBC_SID_REQ_Q_STA_LSB SLBC_BIT(0)
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#define SLBC_SID_REQ_Q_STA_SHIFT 0
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#define SLBC_SID_REQ_Q_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_SID_REL_Q */
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#define SLBC_SID_REL_Q_STA_LSB SLBC_BIT(0)
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#define SLBC_SID_REL_Q_STA_SHIFT 0
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#define SLBC_SID_REL_Q_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_SLOT_USED */
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#define SLBC_SLOT_USED_STA_LSB SLBC_BIT(0)
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#define SLBC_SLOT_USED_STA_SHIFT 0
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#define SLBC_SLOT_USED_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_FORCE */
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#define SLBC_FORCE_STA_LSB SLBC_BIT(0)
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#define SLBC_FORCE_STA_SHIFT 0
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#define SLBC_FORCE_STA_MASK SLBC_BITMASK(15:0)
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#define SLBC_FORCE_ENABLE_LSB SLBC_BIT(16)
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#define SLBC_FORCE_ENABLE_SHIFT 16
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#define SLBC_FORCE_ENABLE_MASK SLBC_BITMASK(16:16)
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/* SLBC_BUFFER_REF */
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#define SLBC_BUFFER_REF_STA_LSB SLBC_BIT(0)
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#define SLBC_BUFFER_REF_STA_SHIFT 0
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#define SLBC_BUFFER_REF_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_REF */
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#define SLBC_REF_STA_LSB SLBC_BIT(0)
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#define SLBC_REF_STA_SHIFT 0
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#define SLBC_REF_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_0 */
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#define SLBC_DEBUG_0_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_0_STA_SHIFT 0
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#define SLBC_DEBUG_0_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_1 */
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#define SLBC_DEBUG_1_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_1_STA_SHIFT 0
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#define SLBC_DEBUG_1_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_2 */
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#define SLBC_DEBUG_2_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_2_STA_SHIFT 0
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#define SLBC_DEBUG_2_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_3 */
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#define SLBC_DEBUG_3_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_3_STA_SHIFT 0
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#define SLBC_DEBUG_3_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_4 */
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#define SLBC_DEBUG_4_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_4_STA_SHIFT 0
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#define SLBC_DEBUG_4_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_5 */
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#define SLBC_DEBUG_5_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_5_STA_SHIFT 0
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#define SLBC_DEBUG_5_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_6 */
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#define SLBC_DEBUG_6_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_6_STA_SHIFT 0
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#define SLBC_DEBUG_6_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_7 */
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#define SLBC_DEBUG_7_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_7_STA_SHIFT 0
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#define SLBC_DEBUG_7_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_APU_BW */
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#define SLBC_APU_BW_R_LSB SLBC_BIT(0)
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#define SLBC_APU_BW_R_SHIFT 0
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#define SLBC_APU_BW_R_MASK SLBC_BITMASK(31:0)
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/* SLBC_MM_BW */
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#define SLBC_MM_BW_R_LSB SLBC_BIT(0)
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#define SLBC_MM_BW_R_SHIFT 0
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#define SLBC_MM_BW_R_MASK SLBC_BITMASK(31:0)
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/* SLBC_MM_EST_BW */
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#define SLBC_MM_BW_EST_R_LSB SLBC_BIT(0)
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#define SLBC_MM_BW_EST_R_SHIFT 0
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#define SLBC_MM_BW_EST_R_MASK SLBC_BITMASK(31:0)
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/* SLBC_CACHE_USED */
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#define SLBC_CACHE_USED_R_LSB SLBC_BIT(0)
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#define SLBC_CACHE_USED_R_SHIFT 0
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#define SLBC_CACHE_USED_R_MASK SLBC_BITMASK(15:0)
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#define SLBC_CACHE_CPU_STA_LSB SLBC_BIT(16)
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#define SLBC_CACHE_CPU_STA_SHIFT 16
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#define SLBC_CACHE_CPU_STA_MASK SLBC_BITMASK(23:16)
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#define SLBC_CACHE_GPU_STA_LSB SLBC_BIT(24)
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#define SLBC_CACHE_GPU_STA_SHIFT 24
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#define SLBC_CACHE_GPU_STA_MASK SLBC_BITMASK(31:24)
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/* SLBC_PMU_0 */
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#define SLBC_PMU_0_LSB SLBC_BIT(0)
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#define SLBC_PMU_0_SHIFT 0
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#define SLBC_PMU_0_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_1 */
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#define SLBC_PMU_1_LSB SLBC_BIT(0)
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#define SLBC_PMU_1_SHIFT 0
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#define SLBC_PMU_1_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_2 */
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#define SLBC_PMU_2_LSB SLBC_BIT(0)
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#define SLBC_PMU_2_SHIFT 0
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#define SLBC_PMU_2_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_3 */
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#define SLBC_PMU_3_LSB SLBC_BIT(0)
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#define SLBC_PMU_3_SHIFT 0
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#define SLBC_PMU_3_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_4 */
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#define SLBC_PMU_4_LSB SLBC_BIT(0)
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#define SLBC_PMU_4_SHIFT 0
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#define SLBC_PMU_4_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_5 */
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#define SLBC_PMU_5_LSB SLBC_BIT(0)
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#define SLBC_PMU_5_SHIFT 0
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#define SLBC_PMU_5_MASK SLBC_BITMASK(31:0)
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/* SLBC_PMU_6 */
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#define SLBC_PMU_6_LSB SLBC_BIT(0)
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#define SLBC_PMU_6_SHIFT 0
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#define SLBC_PMU_6_MASK SLBC_BITMASK(31:0)
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/* SLBC_SCMI_AP */
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#define SLBC_SCMI_AP_LSB SLBC_BIT(0)
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#define SLBC_SCMI_AP_SHIFT 0
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#define SLBC_SCMI_AP_MASK SLBC_BITMASK(31:0)
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/* SLBC_SCMI_SSPM */
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#define SLBC_SCMI_SSPM_LSB SLBC_BIT(0)
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#define SLBC_SCMI_SSPM_SHIFT 0
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#define SLBC_SCMI_SSPM_MASK SLBC_BITMASK(31:0)
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/* SLBC_SCMI_RET1 */
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#define SLBC_SCMI_RET1_LSB SLBC_BIT(0)
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#define SLBC_SCMI_RET1_SHIFT 0
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#define SLBC_SCMI_RET1_MASK SLBC_BITMASK(31:0)
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/* SLBC_SCMI_RET2 */
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#define SLBC_SCMI_RET2_LSB SLBC_BIT(0)
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#define SLBC_SCMI_RET2_SHIFT 0
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#define SLBC_SCMI_RET2_MASK SLBC_BITMASK(31:0)
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/* SLBC_SCMI_RET3 */
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#define SLBC_SCMI_RET3_LSB SLBC_BIT(0)
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#define SLBC_SCMI_RET3_SHIFT 0
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#define SLBC_SCMI_RET3_MASK SLBC_BITMASK(31:0)
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/* SLBC_SRAM_CON */
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#define SLBC_SRAM_CON_LSB SLBC_BIT(0)
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#define SLBC_SRAM_CON_SHIFT 0
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#define SLBC_SRAM_CON_MASK SLBC_BITMASK(31:0)
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/* SLBC_L3CTL */
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#define SLBC_L3CTL_LSB SLBC_BIT(0)
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#define SLBC_L3CTL_SHIFT 0
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#define SLBC_L3CTL_MASK SLBC_BITMASK(31:0)
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/* SLBC_CPU_DEBUG0 */
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#define SLBC_CPU_DEBUG0_R_LSB SLBC_BIT(0)
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#define SLBC_CPU_DEBUG0_R_SHIFT 0
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#define SLBC_CPU_DEBUG0_R_MASK SLBC_BITMASK(31:0)
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/* SLBC_CPU_DEBUG1 */
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#define SLBC_CPU_DEBUG1_R_LSB SLBC_BIT(0)
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#define SLBC_CPU_DEBUG1_R_SHIFT 0
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#define SLBC_CPU_DEBUG1_R_MASK SLBC_BITMASK(31:0)
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/* SLBC_STA */
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#define SLBC_STA_C_MODE_LSB SLBC_BIT(0)
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#define SLBC_STA_C_MODE_SHIFT 0
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#define SLBC_STA_C_MODE_MASK SLBC_BITMASK(1:0)
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#define SLBC_STA_C_L3C_PD_DIS_LSB SLBC_BIT(2)
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#define SLBC_STA_C_L3C_PD_DIS_SHIFT 2
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#define SLBC_STA_C_L3C_PD_DIS_MASK SLBC_BITMASK(2:2)
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#define SLBC_STA_C_WAY_LSB SLBC_BIT(3)
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#define SLBC_STA_C_WAY_SHIFT 3
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#define SLBC_STA_C_WAY_MASK SLBC_BITMASK(6:3)
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#define SLBC_STA_C_DRAM_OPP_LSB SLBC_BIT(7)
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#define SLBC_STA_C_DRAM_OPP_SHIFT 7
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#define SLBC_STA_C_DRAM_OPP_MASK SLBC_BITMASK(10:7)
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#define SLBC_STA_G_MODE_LSB SLBC_BIT(16)
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#define SLBC_STA_G_MODE_SHIFT 16
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#define SLBC_STA_G_MODE_MASK SLBC_BITMASK(17:16)
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#define SLBC_STA_G_WAY_LSB SLBC_BIT(18)
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#define SLBC_STA_G_WAY_SHIFT 18
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#define SLBC_STA_G_WAY_MASK SLBC_BITMASK(21:18)
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/* SLBC_ACK_C */
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#define SLBC_ACK_C_MODE_LSB SLBC_BIT(0)
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#define SLBC_ACK_C_MODE_SHIFT 0
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#define SLBC_ACK_C_MODE_MASK SLBC_BITMASK(1:0)
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#define SLBC_ACK_C_L3C_LSB SLBC_BIT(2)
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#define SLBC_ACK_C_L3C_SHIFT 2
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#define SLBC_ACK_C_L3C_MASK SLBC_BITMASK(5:2)
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/* SLBC_ACK_G */
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#define SLBC_ACK_G_MODE_LSB SLBC_BIT(0)
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#define SLBC_ACK_G_MODE_SHIFT 0
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#define SLBC_ACK_G_MODE_MASK SLBC_BITMASK(1:0)
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/* CPUQOS_MODE */
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#define POWER_CPUQOS_MODE_LSB SLBC_BIT(0)
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#define POWER_CPUQOS_MODE_SHIFT 0
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#define POWER_CPUQOS_MODE_MASK SLBC_BITMASK(3:0)
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/* SLBC_DEBUG_8 */
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#define SLBC_DEBUG_8_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_8_STA_SHIFT 0
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#define SLBC_DEBUG_8_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_9 */
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#define SLBC_DEBUG_9_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_9_STA_SHIFT 0
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#define SLBC_DEBUG_9_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_10 */
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#define SLBC_DEBUG_10_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_10_STA_SHIFT 0
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#define SLBC_DEBUG_10_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_11 */
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#define SLBC_DEBUG_11_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_11_STA_SHIFT 0
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#define SLBC_DEBUG_11_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_12 */
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#define SLBC_DEBUG_12_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_12_STA_SHIFT 0
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#define SLBC_DEBUG_12_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_13 */
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#define SLBC_DEBUG_13_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_13_STA_SHIFT 0
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#define SLBC_DEBUG_13_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_14 */
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#define SLBC_DEBUG_14_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_14_STA_SHIFT 0
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#define SLBC_DEBUG_14_STA_MASK SLBC_BITMASK(31:0)
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/* SLBC_DEBUG_15 */
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#define SLBC_DEBUG_15_STA_LSB SLBC_BIT(0)
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#define SLBC_DEBUG_15_STA_SHIFT 0
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#define SLBC_DEBUG_15_STA_MASK SLBC_BITMASK(31:0)
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#endif
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