137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __BUS_TRACER_V1_H__
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#define __BUS_TRACER_V1_H__
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#define get_bit_at(reg, pos) (((reg) >> (pos)) & 1)
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#define NUM_ID_FILTER 2
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#define SW_RST_B (1 << 0)
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#define ID_FILTER0_EN (1 << 1)
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#define ID_FILTER1_EN (1 << 2)
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#define ID_FILTER2_EN (1 << 3)
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#define ID_FILTER3_EN (1 << 4)
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#define ID_WATCH_OR_BYPASS (1 << 5)
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#define ID_FILTER_EN (1 << 6)
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#define ADDR_FILTER0_EN (1 << 7)
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#define ADDR_FILTER1_EN (1 << 8)
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#define ADDR_FILTER2_EN (1 << 9)
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#define ADDR_FILTER3_EN (1 << 10)
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#define ADDR_WATCH_OR_BYPASS (1 << 11)
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#define ADDR_FILTER_EN (1 << 12)
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#define ADDR_RANGE0_EN (1 << 13)
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#define ADDR_RANGE1_EN (1 << 14)
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#define ADDR_RANGE_MODE (1 << 15)
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#define BUS_TRACE_EN (1 << 16)
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#define WDT_RST_EN (1 << 18)
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#define AW_DISABLE (1 << 20)
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#define AR_DISABLE (1 << 21)
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#define W_DISABLE (1 << 22)
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#define B_DISABLE (1 << 23)
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#define R_DISABLE (1 << 24)
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#define BYPASS_FILTER_SHIFT 12
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#define BUS_TRACE_CON 0x0
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#define BUS_TRACE_CON_SYNC_SET 0x4
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#define BUS_TRACE_CON_SYNC_STATUS 0x8
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#define BUS_TRACE_ADDR_RANGE0_L 0x10
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#define BUS_TRACE_ADDR_RANGE0_H 0x14
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#define BUS_TRACE_ADDR_RANGE1_L 0x18
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#define BUS_TRACE_ADDR_RANGE1_H 0x1c
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#define BUS_TRACE_ID_FILTER0 0x20
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#define BUS_TRACE_ID_FILTER1 0x24
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#define BUS_TRACE_ID_FILTER2 0x28
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#define BUS_TRACE_ID_FILTER3 0x2c
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#define BUS_TRACE_ID_MASK0 0x30
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#define BUS_TRACE_ID_MASK1 0x34
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#define BUS_TRACE_ID_MASK2 0x38
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#define BUS_TRACE_ID_MASK3 0x3c
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#define BUS_TRACE_ADDR_FILTER0_L 0x40
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#define BUS_TRACE_ADDR_FILTER0_H 0x44
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#define BUS_TRACE_ADDR_FILTER1_L 0x48
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#define BUS_TRACE_ADDR_FILTER1_H 0x4c
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#define BUS_TRACE_ADDR_FILTER2_L 0x50
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#define BUS_TRACE_ADDR_FILTER2_H 0x54
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#define BUS_TRACE_ADDR_FILTER3_L 0x58
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#define BUS_TRACE_ADDR_FILTER3_H 0x5c
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#define BUS_TRACE_ADDR_MASK0_L 0x60
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#define BUS_TRACE_ADDR_MASK0_H 0x64
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#define BUS_TRACE_ADDR_MASK1_L 0x68
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#define BUS_TRACE_ADDR_MASK1_H 0x6c
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#define BUS_TRACE_ADDR_MASK2_L 0x70
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#define BUS_TRACE_ADDR_MASK2_H 0x74
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#define BUS_TRACE_ADDR_MASK3_L 0x78
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#define BUS_TRACE_ADDR_MASK3_H 0x7c
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#define BUS_TRACE_ATID 0x80
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#define BUS_TRACE_BUS_DBG_CON_AO 0xfc
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/* ETB registers, "CoreSight Components TRM", 9.3 */
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#define ETB_DEPTH 0x04
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#define ETB_STATUS 0x0c
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#define ETB_READMEM 0x10
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#define ETB_READADDR 0x14
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#define ETB_WRITEADDR 0x18
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#define ETB_TRIGGERCOUNT 0x1c
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#define ETB_CTRL 0x20
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#define ETB_RWD 0x24
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#define ETB_REG28 0x28
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#define ETB_REG110 0x110
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#define ETB_REG304 0x304
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#define ETB_LAR 0xfb0
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#define DEM_DBGRST_ALL 0x28
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#define DEM_ATB_CG 0x68
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#define DEM_ATB_CLK 0x70
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#define INSERT_TS0 0x80
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#define ETR_AWID 0x84
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#define ETR_AWUSER 0x88
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#define DEM_LAR 0xfb0
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#define DBG_ERR_FLAG_CON 0x80
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#define DBG_ERR_FLAG_WDT_MASK_EN 0x84
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#define DBG_ERR_FLAG_STATUS0 0x88
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#define DBG_ERR_FLAG_STATUS1 0x8c
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#define DBG_ERR_FLAG_SYSTIMER_L 0x90
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#define DBG_ERR_FLAG_SYSTIMER_H 0x94
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#define DBG_ERR_FLAG_ERR_STAGE 0x98
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#define DBG_ERR_FLAG_IRQ_POLARITY 0x9c
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#define REPLICATOR1_BASE 0x1000
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#define REPLICATOR_LAR 0xfb0
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#define REPLICATOR_IDFILTER0 0x0
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#define REPLICATOR_IDFILTER1 0x4
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#define FUNNEL_CTRL_REG 0x0
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#define FUNNEL_LOCKACCESS 0xfb0
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#define CORESIGHT_LAR 0xfb0
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#define CORESIGHT_UNLOCK 0xc5acce55
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static inline void CS_LOCK(void __iomem *addr)
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{
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do {
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/* Wait for things to settle */
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mb();
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writel_relaxed(0x0, addr + CORESIGHT_LAR);
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} while (0);
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}
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static inline void CS_UNLOCK(void __iomem *addr)
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{
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do {
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writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
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/* Make sure everyone has seen this */
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mb();
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} while (0);
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}
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void disable_etb_capture(void);
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void enable_etb_for_gpu_mcu(void);
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#endif /* end of __BUS_TRACER_V1_H__ */
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