72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Anthony Huang <anthony.huang@mediatek.com>
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*/
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#ifndef _MTK_MMDVFS_V3_MEMORY_H_
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#define _MTK_MMDVFS_V3_MEMORY_H_
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#if IS_ENABLED(CONFIG_MTK_MMDVFS)
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void *mmdvfs_get_vcp_base(phys_addr_t *pa);
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bool mmdvfs_is_init_done(void);
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#else
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static inline void *mmdvfs_get_vcp_base(phys_addr_t *pa)
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{
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if (pa)
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*pa = 0;
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return NULL;
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}
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static inline bool mmdvfs_is_init_done(void) { return false; }
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#endif
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#define MEM_BASE mmdvfs_get_vcp_base(NULL)
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#define MEM_LOG_FLAG (MEM_BASE + 0x0)
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#define MEM_FREERUN (MEM_BASE + 0x4)
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#define MEM_VSRAM_VOL (MEM_BASE + 0x8)
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#define MEM_IPI_SYNC_FUNC (MEM_BASE + 0xC)
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#define MEM_IPI_SYNC_DATA (MEM_BASE + 0x10)
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/* skip : 0x14 */
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#define MEM_GENPD_ENABLE_USR(x) (MEM_BASE + 0x18 + 0x4 * (x)) // CAM, VDE
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#define MEM_AGING_CNT_USR(x) (MEM_BASE + 0x20 + 0x4 * (x)) // CAM, IMG
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#define MEM_FRESH_CNT_USR(x) (MEM_BASE + 0x28 + 0x4 * (x)) // CAM, IMG
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#define MEM_FORCE_OPP_PWR(x) (MEM_BASE + 0x30 + 0x4 * (x)) // POWER_NUM
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#define MEM_VOTE_OPP_PWR(x) (MEM_BASE + 0x40 + 0x4 * (x)) // POWER_NUM
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#define MEM_VOTE_OPP_USR(x) (MEM_BASE + 0x50 + 0x4 * (x)) // USER_NUM
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/* skip : 0x8C */
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#define MEM_CLKMUX_ENABLE (MEM_BASE + 0x90)
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#define MEM_CLKMUX_ENABLE_DONE (MEM_BASE + 0x94)
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#define MEM_VMM_CEIL_ENABLE (MEM_BASE + 0x98)
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#define MEM_VMM_EFUSE (MEM_BASE + 0x9C)
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#define MEM_VMM_OPP_VOLT(x) (MEM_BASE + 0xA0 + 0x4 * (x)) // VMM_OPP_NUM(8)
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/* next start: 0xC0 */
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#define MEM_REC_PWR_OBJ 4
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#define MEM_REC_USR_OBJ 5
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#define MEM_REC_VMM_DBG_OBJ 5
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#define MEM_REC_CNT_MAX 16
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#define MEM_REC_VMM_DBG_CNT (MEM_BASE + 0xC74)
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#define MEM_REC_VMM_SEC(x) (MEM_BASE + 0xC78 + MEM_REC_VMM_DBG_OBJ * 0x4 * (x))
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#define MEM_REC_VMM_NSEC(x) (MEM_BASE + 0xC7C + MEM_REC_VMM_DBG_OBJ * 0x4 * (x))
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#define MEM_REC_VMM_VOLT(x) (MEM_BASE + 0xC80 + MEM_REC_VMM_DBG_OBJ * 0x4 * (x))
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#define MEM_REC_VMM_TEMP(x) (MEM_BASE + 0xC84 + MEM_REC_VMM_DBG_OBJ * 0x4 * (x))
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#define MEM_REC_VMM_AVS(x) (MEM_BASE + 0xC88 + MEM_REC_VMM_DBG_OBJ * 0x4 * (x))
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#define MEM_REC_PWR_CNT (MEM_BASE + 0xDB8)
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#define MEM_REC_PWR_SEC(x) (MEM_BASE + 0xDBC + MEM_REC_PWR_OBJ * 0x4 * (x))
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#define MEM_REC_PWR_NSEC(x) (MEM_BASE + 0xDC0 + MEM_REC_PWR_OBJ * 0x4 * (x))
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#define MEM_REC_PWR_ID(x) (MEM_BASE + 0xDC4 + MEM_REC_PWR_OBJ * 0x4 * (x))
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#define MEM_REC_PWR_OPP(x) (MEM_BASE + 0xDC8 + MEM_REC_PWR_OBJ * 0x4 * (x))
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#define MEM_REC_USR_CNT (MEM_BASE + 0xEBC)
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#define MEM_REC_USR_SEC(x) (MEM_BASE + 0xEC0 + MEM_REC_USR_OBJ * 0x4 * (x))
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#define MEM_REC_USR_NSEC(x) (MEM_BASE + 0xEC4 + MEM_REC_USR_OBJ * 0x4 * (x))
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#define MEM_REC_USR_PWR(x) (MEM_BASE + 0xEC8 + MEM_REC_USR_OBJ * 0x4 * (x))
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#define MEM_REC_USR_ID(x) (MEM_BASE + 0xECC + MEM_REC_USR_OBJ * 0x4 * (x))
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#define MEM_REC_USR_OPP(x) (MEM_BASE + 0xED0 + MEM_REC_USR_OBJ * 0x4 * (x))
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#endif
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