238 lines
8.8 KiB
C
238 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __MCUPM_IPI_TABLE_H__
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#define __MCUPM_IPI_TABLE_H__
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#include <mtk_tinysys_ipi.h>
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#include "mcupm_ipi_id.h"
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#define MCUPM_MBOX_TOTAL 8
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/*share memory start address defination*/
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#define SMEM_SIZE_80B 0x00000014 //80 Bytes
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#define PIN_S_SIZE SMEM_SIZE_80B
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#define PIN_R_SIZE SMEM_SIZE_80B
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#define MBOX_TABLE_SIZE (PIN_S_SIZE + PIN_R_SIZE)
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#define SMEM0_SET_IRQ_REG SW_INT_SET
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#define SMEM0_CLR_IRQ_REG SW_INT_CLR
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/* definition of slot offset for send PINs */
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#define PIN_S_OFFSET_PLATFORM 0
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#define PIN_S_OFFSET_CPU_DVFS 0
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#define PIN_S_OFFSET_FHCTL 0
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#define PIN_S_OFFSET_MCDI 0
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#define PIN_S_OFFSET_SUSPEND 0
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#define PIN_S_OFFSET_SMET 0
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#define PIN_S_OFFSET_RMET 0
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#define PIN_S_OFFSET_EEMSN 0
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#define PIN_S_MSG_SIZE_PLATFORM 4 //uint 4 byts
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#define PIN_S_MSG_SIZE_CPU_DVFS 4 //uint 4 byts
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#define PIN_S_MSG_SIZE_FHCTL 9 //uint 4 byts
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#define PIN_S_MSG_SIZE_MCDI 3 //uint 4 byts
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#define PIN_S_MSG_SIZE_SUSPEND 3 //uint 4 byts
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#define PIN_S_MSG_SIZE_SMET 4 //unit 4 bytes
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#define PIN_S_MSG_SIZE_RMET 1 //unit 4 bytes
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#define PIN_S_MSG_SIZE_EEMSN 4 //unit 4 bytes
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/* definition of slot size for send PINs */
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#define PIN_S_SIZE_PLATFORM PIN_S_SIZE
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#define PIN_S_SIZE_CPU_DVFS PIN_S_SIZE
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#define PIN_S_SIZE_FHCTL PIN_S_SIZE
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#define PIN_S_SIZE_MCDI PIN_S_SIZE
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#define PIN_S_SIZE_SUSPEND PIN_S_SIZE
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#define PIN_S_SIZE_SMET PIN_S_SIZE
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#define PIN_S_SIZE_RMET PIN_S_SIZE
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#define PIN_S_SIZE_EEMSN PIN_S_SIZE
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#define PIN_R_MSG_SIZE_PLATFORM 1 //uint 4 byts
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#define PIN_R_MSG_SIZE_CPU_DVFS 4 //uint 4 byts
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#define PIN_R_MSG_SIZE_FHCTL 1 //uint 4 byts
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#define PIN_R_MSG_SIZE_MCDI 1 //uint 4 byts
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#define PIN_R_MSG_SIZE_SUSPEND 1 //uint 4 byts
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#define PIN_R_MSG_SIZE_SMET 1 //uint 4 byts
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#define PIN_R_MSG_SIZE_RMET 4 //uint 4 byts
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#define PIN_R_MSG_SIZE_EEMSN 1 //unit 4 bytes
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/* definition of slot size for received PINs */
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#define PIN_R_SIZE_PLATFORM PIN_R_SIZE
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#define PIN_R_SIZE_CPU_DVFS PIN_R_SIZE
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#define PIN_R_SIZE_FHCTL PIN_R_SIZE
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#define PIN_R_SIZE_MCDI PIN_R_SIZE
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#define PIN_R_SIZE_SUSPEND PIN_R_SIZE
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#define PIN_R_SIZE_SMET PIN_R_SIZE
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#define PIN_R_SIZE_RMET PIN_R_SIZE
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#define PIN_R_SIZE_EEMSN PIN_R_SIZE
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/* definition of slot offset for received PINs */
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#define PIN_R_OFFSET_PLATFORM (PIN_S_OFFSET_PLATFORM + PIN_S_SIZE_PLATFORM)
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#define PIN_R_OFFSET_CPU_DVFS (PIN_S_OFFSET_CPU_DVFS + PIN_S_SIZE_CPU_DVFS)
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#define PIN_R_OFFSET_FHCTL (PIN_S_OFFSET_FHCTL + PIN_S_SIZE_FHCTL)
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#define PIN_R_OFFSET_MCDI (PIN_S_OFFSET_MCDI + PIN_S_SIZE_MCDI)
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#define PIN_R_OFFSET_SUSPEND (PIN_S_OFFSET_SUSPEND + PIN_S_SIZE_SUSPEND)
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#define PIN_R_OFFSET_SMET (PIN_S_OFFSET_SMET + PIN_S_SIZE_SMET)
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#define PIN_R_OFFSET_RMET (PIN_S_OFFSET_RMET + PIN_S_SIZE_RMET)
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#define PIN_R_OFFSET_EEMSN (PIN_S_OFFSET_EEMSN + PIN_S_SIZE_EEMSN)
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extern struct mtk_ipi_device mcupm_ipidev;
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/*
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* mbox information
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*
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* mbdev :mbox device
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* irq_num:identity of mbox irq
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* id :mbox id
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* slot :how many slots that mbox used, up to 1GB
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* opt :option for mbox or share memory, 0:mbox, 1:share memory
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* enable :mbox status, 0:disable, 1: enable
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* is64d :mbox is64d status, 0:32d, 1: 64d
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* base :mbox base address
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* set_irq_reg : mbox set irq register
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* clr_irq_reg : mbox clear irq register
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* init_base_reg: mbox initialize register
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* mbox lock : lock of mbox
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*/
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struct mtk_mbox_info mcupm_mbox_table[MCUPM_MBOX_TOTAL] = {
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{0, 0, 0, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 1, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 2, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 3, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 4, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 5, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 6, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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{0, 0, 7, MBOX_TABLE_SIZE, MBOX_OPT_SMEM, 1, 0, 0, 0, 0, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } }, {0, 0, 0} },
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};
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/*
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* mbox pin structure, this is for send defination,
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* ipi=endpoint=pin
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* mbox : (mbox number)mbox number of the pin, up to 16(plt)
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* offset : (slot)msg offset in share memory, up to 1024*4 KB(plt)
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* send_opt : (opt)send opt, 0:send ,1: send for response(plt)
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* lock : (lock)polling lock 0:unuse,1:used
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* msg_size : (slot)message size in words, 4 bytes alignment(plt)
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* pin_index : (bit offset)pin index in the mbox(plt)
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* chan_id : (u32) ipc channel id(plt)
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* mutex : (mutex)mutex for remote response
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* completion : (completion)completion for remote response
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* pin_lock : (spinlock_t)lock of the pin
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*/
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struct mtk_mbox_pin_send mcupm_mbox_pin_send[] = {
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{0, PIN_S_OFFSET_PLATFORM, 1, 0, PIN_S_MSG_SIZE_PLATFORM,
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0, CH_S_PLATFORM,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{1, PIN_S_OFFSET_CPU_DVFS, 1, 0, PIN_S_MSG_SIZE_CPU_DVFS,
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1, CH_S_CPU_DVFS,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{2, PIN_S_OFFSET_FHCTL, 1, 0, PIN_S_MSG_SIZE_FHCTL,
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2, CH_S_FHCTL,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{3, PIN_S_OFFSET_MCDI, 1, 0, PIN_S_MSG_SIZE_MCDI,
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3, CH_S_MCDI,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{4, PIN_S_OFFSET_SUSPEND, 1, 0, PIN_S_MSG_SIZE_SUSPEND,
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4, CH_S_SUSPEND,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{5, PIN_S_OFFSET_RMET, 1, 0, PIN_S_MSG_SIZE_RMET,
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5, CH_IPIR_C_MET,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{6, PIN_S_OFFSET_SMET, 1, 0, PIN_S_MSG_SIZE_SMET,
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6, CH_IPIS_C_MET,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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{7, PIN_S_OFFSET_EEMSN, 1, 0, PIN_S_MSG_SIZE_EEMSN,
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7, CH_S_EEMSN,
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{ { 0 } }, { 0 }, { { { __ARCH_SPIN_LOCK_UNLOCKED } } } },
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};
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/*
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* mbox pin structure, this is for receive defination,
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* ipi=endpoint=pin
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* mbox : (mbox number)mbox number of the pin, up to 16(plt)
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* offset : (slot)msg offset in share memory, up to 1024*4 KB(plt)
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* recv_opt : (opt)recv option, 0:receive ,1: response(plt)
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* lock : (lock)polling lock 0:unuse,1:used
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* buf_full_opt : (opt)buffer option 0:drop, 1:assert, 2:overwrite(plt)
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* cb_ctx_opt : (opt)callback option 0:isr context, 1:process context(plt)
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* msg_size : (slot)msg used slots in the mbox, 4 bytes alignment(plt)
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* pin_index : (bit offset)pin index in the mbox(plt)
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* chan_id : (u32) ipc channel id(plt)
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* notify : (completion)notify process
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* mbox_pin_cb: (cb)cb function
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* pin_buf : (void*)buffer point
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* prdata : (void*)private data
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* pin_lock: (spinlock_t)lock of the pin
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*/
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struct mtk_mbox_pin_recv mcupm_mbox_pin_recv[] = {
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{0, PIN_R_OFFSET_PLATFORM, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_PLATFORM, 0,
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CH_S_PLATFORM, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{1, PIN_R_OFFSET_CPU_DVFS, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_CPU_DVFS, 1,
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CH_S_CPU_DVFS, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{2, PIN_R_OFFSET_FHCTL, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_FHCTL, 2,
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CH_S_FHCTL, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{3, PIN_R_OFFSET_MCDI, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_MCDI, 3,
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CH_S_MCDI, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{4, PIN_R_OFFSET_SUSPEND, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_SUSPEND, 4,
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CH_S_SUSPEND, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{5, PIN_R_OFFSET_RMET, 0, 0, 1, 1,
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PIN_R_MSG_SIZE_RMET, 5,
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CH_IPIR_C_MET, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{6, PIN_R_OFFSET_SMET, 1, 0, 1, 1,
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PIN_R_MSG_SIZE_SMET, 6,
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CH_IPIS_C_MET, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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{7, PIN_R_OFFSET_EEMSN, 0, 0, 1, 0,
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PIN_R_MSG_SIZE_EEMSN, 7,
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CH_S_EEMSN, { 0 }, 0, 0, 0,
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{ { { __ARCH_SPIN_LOCK_UNLOCKED } } },
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{0, 0, 0, 0, 0, 0} },
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};
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#define MCUPM_TOTAL_SEND_PIN (sizeof(mcupm_mbox_pin_send) \
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/ sizeof(struct mtk_mbox_pin_send))
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#define MCUPM_TOTAL_RECV_PIN (sizeof(mcupm_mbox_pin_recv) \
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/ sizeof(struct mtk_mbox_pin_recv))
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struct mtk_mbox_device mcupm_mboxdev = {
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.name = "mcupm_mboxdev",
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.pin_recv_table = &mcupm_mbox_pin_recv[0],
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.pin_send_table = &mcupm_mbox_pin_send[0],
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.info_table = &mcupm_mbox_table[0],
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.count = MCUPM_MBOX_TOTAL,
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.recv_count = MCUPM_TOTAL_RECV_PIN,
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.send_count = MCUPM_TOTAL_SEND_PIN,
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};
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struct mtk_ipi_device mcupm_ipidev = {
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.name = "mcupm_ipidev",
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.id = IPI_DEV_MCUPM,
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.mbdev = &mcupm_mboxdev,
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};
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#endif
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