315 lines
7.8 KiB
C
315 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_EEMG_CONFIG_H_
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#define _MTK_EEMG_CONFIG_H_
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/* CONFIG (SW related) */
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//#define EEMG_NOT_READY (1)
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#define CONFIG_EEMG_SHOWLOG (0)
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#define EN_ISR_LOG (0)
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#define EEMG_BANK_SOC (0) /* use voltage bin, so disable it */
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#define EARLY_PORTING (0)
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#define DUMP_DATA_TO_DE (1)
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#define EEMG_ENABLE (1) /* enable; after pass HPT mini-SQC */
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#define EEMG_FAKE_EFUSE (0)
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/* FIX ME */
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#define EEMG_LOCKTIME_LIMIT (3000)
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#define EEMG_OFFSET
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#define SET_PMIC_VOLT (1)
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#define SET_PMIC_VOLT_TO_DVFS (1)
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#define LOG_INTERVAL (2LL * NSEC_PER_SEC)
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#define SUPPORT_DCONFIG (1)
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#define ENABLE_HT_FT (1)
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#define ENABLE_REMOVE_AGING (0)
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#define DUMP_LEN 105
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#define DEVINFO_IDX_0 0xC8
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#define DEVINFO_IDX_1 0xCC
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#define DEVINFO_IDX_2 0xD0
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#define DEVINFO_IDX_3 0xD4
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#define DEVINFO_IDX_4 0xD8
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#define DEVINFO_IDX_5 0xDC
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#define DEVINFO_IDX_6 0xE0
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#define DEVINFO_IDX_7 0xE4
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#define DEVINFO_IDX_8 0xE8
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#define DEVINFO_IDX_9 0xEC
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#define DEVINFO_IDX_10 0xF0
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#define DEVINFO_IDX_11 0xF4
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#define DEVINFO_IDX_12 0xF8
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#define DEVINFO_IDX_13 0xFC
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#define DEVINFO_IDX_14 0x100
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#define DEVINFO_IDX_15 0x104
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#define DEVINFO_IDX_16 0x108
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#define DEVINFO_IDX_17 0x10C
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#define DEVINFO_IDX_18 0x110
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#define DEVINFO_IDX_19 0x114
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#define DEVINFO_IDX_20 0x1D0
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#if EEMG_FAKE_EFUSE /* select secure mode based on efuse config */
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#define SEC_MOD_SEL 0x00 /* non secure mode */
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#else
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#define SEC_MOD_SEL 0x00 /* Secure Mode 0 */
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#endif
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#if SEC_MOD_SEL == 0xF0
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#define DEVINFO_0 0xFF00
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#define DEVINFO_1 0x10bd3c1b
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#define DEVINFO_2 0x550055
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#define DEVINFO_3 0x10bd3c1b
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#define DEVINFO_4 0x10bd3c1b
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#define DEVINFO_5 0x550055
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#define DEVINFO_6 0x10bd3c1b
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#define DEVINFO_7 0x10bd3c1b
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#define DEVINFO_8 0x550055
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#define DEVINFO_9 0x10bd3c1b
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#define DEVINFO_10 0x10bd3c1b
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#define DEVINFO_11 0x550055
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#define DEVINFO_12 0x10bd3c1b
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#define DEVINFO_16 0x10bd3c1b
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#define DEVINFO_17 0x550055
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#else
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#if defined(CMD_LOAD)
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#define DEVINFO_0 0x00060006
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#define DEVINFO_1 0x0
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#define DEVINFO_2 0x000000AF
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#define DEVINFO_3 0x9B0B0363
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#define DEVINFO_4 0x9B0B0769
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#define DEVINFO_5 0x00A100A6
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#define DEVINFO_6 0x9B0BBF96
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#define DEVINFO_7 0x10bd3c1b
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#define DEVINFO_8 0x550055
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#define DEVINFO_9 0x10bd3c1b
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#define DEVINFO_10 0x9B0B2263
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#define DEVINFO_11 0x00B900AC
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#define DEVINFO_12 0x570B166E
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#define DEVINFO_16 0x9B0B0866
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#define DEVINFO_17 0x00A100BB
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#elif defined(MC50_LOAD)
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#define DEVINFO_0 0x00000001
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#define DEVINFO_1 0x0
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#define DEVINFO_2 0x5A1E242A
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#define DEVINFO_3 0x57142476
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#define DEVINFO_4 0x49172454
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#define DEVINFO_5 0x0
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#define DEVINFO_6 0x0
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#define DEVINFO_7 0x4D152457
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#define DEVINFO_8 0x00000000
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#define DEVINFO_9 0x56EC00DC
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#define DEVINFO_10 0x081800A6
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#define DEVINFO_11 0x6F572444
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#define DEVINFO_12 0x725C244D
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#define DEVINFO_13 0x1B031B03
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#define DEVINFO_14 0x1B031B03
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#define DEVINFO_15 0x00000000
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#define DEVINFO_16 0x1B031B03
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#define DEVINFO_17 0x1B031B03
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//#define DEVINFO_18 0x5D025D02
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#else
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/* MC99 Safe EFUSE */
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#define DEVINFO_0 0x0
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#define DEVINFO_1 0x94132424
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#define DEVINFO_2 0xB1E92424
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#define DEVINFO_3 0x42122446
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#define DEVINFO_4 0x63122424
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#define DEVINFO_5 0x0
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#define DEVINFO_6 0x0
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#define DEVINFO_7 0x62122424
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#define DEVINFO_8 0x51152498
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#define DEVINFO_9 0x46EA0098
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#define DEVINFO_10 0x37170054
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#define DEVINFO_11 0xC3990089
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#define DEVINFO_12 0xDC910089
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#define DEVINFO_13 0x1B031B03
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#define DEVINFO_14 0x1B031B03
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#define DEVINFO_15 0x0
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#define DEVINFO_16 0x1B031B03
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#define DEVINFO_17 0x1B031B03
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#endif
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#endif
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/*****************************************
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* eem sw setting
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******************************************
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*/
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//#define NR_HW_RES_FOR_BANK (18) /* real eem banks for efuse */
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#define EEMG_INIT01_FLAG (0x01) /* 0x01=> [0]:GPU */
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#define NR_FREQ 16
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#define NR_FREQ_GPU 16
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#define BANK_GPU_TURN_PT 6
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/*
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* 100 us, This is the EEM Detector sampling time as represented in
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* cycles of bclk_ck during INIT. 52 MHz
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*/
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#define DETWINDOW_VAL 0xA28
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/*
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* mili Volt to config value. voltage = 600mV + val * 6.25mV
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* val = (voltage - 600) / 6.25
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* @mV: mili volt
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*/
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/* 1mV=>10uV */
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/* EEM */
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#define EEMG_V_BASE (40000)
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#define EEMG_STEP (625)
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/* CPU */
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#define CPU_PMIC_BASE_6359 (0)
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#define CPU_PMIC_STEP (625)
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/* GPU */
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#define GPU_PMIC_BASE (0)
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#define GPU_PMIC_STEP (625)
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/* common part: for cci, LL, L, GPU */
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/* common part: for LL, L */
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#define VBOOT_PMIC_VAL (75000)
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#define VBOOT_PMIC_CLR (0)
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#define VBOOT_VAL (0x38) /* volt domain: 0.75v */
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#define VMAX_VAL (0x60) /* volt domain: 1v*/
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#define VMIN_VAL (0x20) /* volt domain: 0.55v*/
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#define VCO_VAL (0x18)
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#define DVTFIXED_VAL (0x6)
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#define DVTFIXED_M_VAL (0x6)
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#define VMAX_VAL_B (0x60) /* volt domain: 1v*/
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#define VMIN_VAL_B (0x20) /* volt domain: 0.6v*/
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#define VCO_VAL_B (0x18) /* volt domain: 0.55v*/
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#define DVTFIXED_VAL_B (0x6)
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#define DTHI_VAL (0x01) /* positive */
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#define DTLO_VAL (0xfe) /* negative (2's compliment) */
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/* This timeout value is in cycles of bclk_ck. */
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#define DETMAX_VAL (0xffff)
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#define AGECONFIG_VAL (0x555555)
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#define AGEM_VAL (0x0)
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#define DCCONFIG_VAL (0x1)
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/* different for GPU */
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#define VMAX_VAL_GPU (0x60) /* eem domain: 1v*/
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#define VMIN_VAL_GPU (0x1A) /* 0.5625v */
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#define VMIN_VAL_GPU_01 (0x1E) /* 0.5875v */
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#define VCO_VAL_GPU (0x18) /* eem domain: 0.55v*/
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/* different for GPU_L */
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#define VMAX_VAL_GL (0x60)
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#define VMIN_VAL_GL (0x18)
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#define VCO_VAL_GL (0x18)
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#define DVTFIXED_VAL_GL (0x01)
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#define DVTFIXED_VAL_GPU (0x06)
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/* different for GPU_H */
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#define VMAX_VAL_GH (0x60) /* volt domain: 1.11875v*/
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#define VMIN_VAL_GH (0x1A) /* 0.5625v */
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#define VMIN_VAL_GH_01 (0x1E) /* 0.5875v */
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#define VCO_VAL_GH (0x18)
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/* different for L_L */
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#define VMAX_VAL_LL (0x37)
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#define VMIN_VAL_LL (0x15)
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#define VCO_VAL_LL (0x15)
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/* different for B_L */
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#define VMAX_VAL_BL (0x60) /* volt domain: 1.11875v*/
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#define VMIN_VAL_BL (0x20)
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#define VCO_VAL_BL (0x18)
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#define DVTFIXED_VAL_BL (0x6)
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/* different for L_H */
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#define VMAX_VAL_H (0x50)
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#define VMIN_VAL_H (0x30)
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#define VCO_VAL_H (0x30)
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#define DVTFIXED_VAL_H (0x03)
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/* different for B_H */
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#define VMAX_VAL_BH (0x73) /* volt domain: 1.11875v*/
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#define VMIN_VAL_BH (0x20)
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#define VCO_VAL_BH (0x18)
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#define DVTFIXED_VAL_BH (0x6)
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/* use in base_ops_mon_mode */
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#define MTS_VAL (0x1fb)
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#define BTS_VAL (0x6d1)
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#define CORESEL_VAL (0x8fff0000)
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#define CORESEL_INIT2_VAL (0x0fff0000)
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#define LOW_TEMP_VAL (25000)
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#define EXTRA_LOW_TEMP_VAL (10000)
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#define HIGH_TEMP_VAL (85000)
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#define LOW_TEMP_OFF_DEFAULT (0)
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#define LOW_TEMP_OFF_L (8)
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#define HIGH_TEMP_OFF_L (3)
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#define LOW_TEMP_OFF_B (8)
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#define HIGH_TEMP_OFF_B (3)
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#define LOW_TEMP_OFF_GPU (4)
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#define HIGH_TEMP_OFF_GPU (0)
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#define EXTRA_LOW_TEMP_OFF_GPU (7)
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#define MARGIN_ADD_OFF (5)
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#define MARGIN_CLAMP_OFF (8)
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/* for EEMCTL0's setting */
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#define EEMG_CTL0_GPU (0x00540003)
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#define AGING_VAL_GPU (0x0) /* GPU aging margin : 43.75mv*/
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#if SEC_MOD_SEL == 0x00
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#define SEC_DCBDET 0xCC
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#define SEC_DCMDET 0xE6
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#define SEC_BDES 0xF5
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#define SEC_MDES 0x97
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#define SEC_MTDES 0xAC
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#elif SEC_MOD_SEL == 0x10
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#define SEC_DCBDET 0xE5
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#define SEC_DCMDET 0xB
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#define SEC_BDES 0x31
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#define SEC_MDES 0x53
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#define SEC_MTDES 0x68
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#elif SEC_MOD_SEL == 0x20
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#define SEC_DCBDET 0x39
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#define SEC_DCMDET 0xFE
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#define SEC_BDES 0x18
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#define SEC_MDES 0x8F
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#define SEC_MTDES 0xB4
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#elif SEC_MOD_SEL == 0x30
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#define SEC_DCBDET 0xDF
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#define SEC_DCMDET 0x18
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#define SEC_BDES 0x0B
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#define SEC_MDES 0x7A
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#define SEC_MTDES 0x52
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#elif SEC_MOD_SEL == 0x40
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#define SEC_DCBDET 0x36
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#define SEC_DCMDET 0xF1
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#define SEC_BDES 0xE2
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#define SEC_MDES 0x80
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#define SEC_MTDES 0x41
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#endif
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#endif
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