122 lines
4.9 KiB
C
122 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_DEFEEMG_
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#define _MTK_DEFEEMG_
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#include <linux/kernel.h>
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extern void __iomem *eemg_base;
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#define EEMG_BASEADDR eemg_base
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#define EEMG_TEMPMONCTL0 (EEMG_BASEADDR + 0x000)
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#define EEMG_TEMPMONCTL1 (EEMG_BASEADDR + 0x004)
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#define EEMG_TEMPMONCTL2 (EEMG_BASEADDR + 0x008)
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#define EEMG_TEMPMONINT (EEMG_BASEADDR + 0x00C)
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#define EEMG_TEMPMONINTSTS (EEMG_BASEADDR + 0x010)
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#define EEMG_TEMPMONIDET0 (EEMG_BASEADDR + 0x014)
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#define EEMG_TEMPMONIDET1 (EEMG_BASEADDR + 0x018)
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#define EEMG_TEMPMONIDET2 (EEMG_BASEADDR + 0x01C)
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#define EEMG_TEMPH2NTHRE (EEMG_BASEADDR + 0x024)
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#define EEMG_TEMPHTHRE (EEMG_BASEADDR + 0x028)
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#define EEMG_TEMPCTHRE (EEMG_BASEADDR + 0x02C)
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#define EEMG_TEMPOFFSETH (EEMG_BASEADDR + 0x030)
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#define EEMG_TEMPOFFSETL (EEMG_BASEADDR + 0x034)
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#define EEMG_TEMPMSRCTL0 (EEMG_BASEADDR + 0x038)
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#define EEMG_TEMPMSRCTL1 (EEMG_BASEADDR + 0x03C)
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#define EEMG_TEMPAHBPOLL (EEMG_BASEADDR + 0x040)
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#define EEMG_TEMPAHBTO (EEMG_BASEADDR + 0x044)
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#define EEMG_TEMPADCPNP0 (EEMG_BASEADDR + 0x048)
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#define EEMG_TEMPADCPNP1 (EEMG_BASEADDR + 0x04C)
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#define EEMG_TEMPADCPNP2 (EEMG_BASEADDR + 0x050)
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#define EEMG_TEMPADCMUX (EEMG_BASEADDR + 0x054)
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#define EEMG_TEMPADCEXT (EEMG_BASEADDR + 0x058)
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#define EEMG_TEMPADCEXT1 (EEMG_BASEADDR + 0x05C)
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#define EEMG_TEMPADCEN (EEMG_BASEADDR + 0x060)
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#define EEMG_TEMPPNPMUXADDR (EEMG_BASEADDR + 0x064)
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#define EEMG_TEMPADCMUXADDR (EEMG_BASEADDR + 0x068)
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#define EEMG_TEMPADCEXTADDR (EEMG_BASEADDR + 0x06C)
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#define EEMG_TEMPADCEXT1ADDR (EEMG_BASEADDR + 0x070)
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#define EEMG_TEMPADCENADDR (EEMG_BASEADDR + 0x074)
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#define EEMG_TEMPADCVALIDADDR (EEMG_BASEADDR + 0x078)
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#define EEMG_TEMPADCVOLTADDR (EEMG_BASEADDR + 0x07C)
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#define EEMG_TEMPRDCTRL (EEMG_BASEADDR + 0x080)
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#define EEMG_TEMPADCVALIDMASK (EEMG_BASEADDR + 0x084)
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#define EEMG_TEMPADCVOLTAGESHIFT (EEMG_BASEADDR + 0x088)
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#define EEMG_TEMPADCWRITECTRL (EEMG_BASEADDR + 0x08C)
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#define EEMG_TEMPMSR0 (EEMG_BASEADDR + 0x090)
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#define EEMG_TEMPMSR1 (EEMG_BASEADDR + 0x094)
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#define EEMG_TEMPMSR2 (EEMG_BASEADDR + 0x098)
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#define EEMG_TEMPIMMD0 (EEMG_BASEADDR + 0x0A0)
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#define EEMG_TEMPIMMD1 (EEMG_BASEADDR + 0x0A4)
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#define EEMG_TEMPIMMD2 (EEMG_BASEADDR + 0x0A8)
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#define EEMG_TEMPMONIDET3 (EEMG_BASEADDR + 0x0B0)
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#define EEMG_TEMPADCPNP3 (EEMG_BASEADDR + 0x0B4)
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#define EEMG_TEMPMSR3 (EEMG_BASEADDR + 0x0B8)
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#define EEMG_TEMPIMMD3 (EEMG_BASEADDR + 0x0BC)
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#define EEMG_TEMPPROTCTL (EEMG_BASEADDR + 0x0C0)
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#define EEMG_TEMPPROTTA (EEMG_BASEADDR + 0x0C4)
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#define EEMG_TEMPPROTTB (EEMG_BASEADDR + 0x0C8)
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#define EEMG_TEMPPROTTC (EEMG_BASEADDR + 0x0CC)
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#define EEMG_TEMPSPARE0 (EEMG_BASEADDR + 0x8F0)
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#define EEMG_TEMPSPARE1 (EEMG_BASEADDR + 0x8F4)
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#define EEMG_TEMPSPARE2 (EEMG_BASEADDR + 0x8F8)
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#define EEMG_TEMPSPARE3 (EEMG_BASEADDR + 0x8FC)
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#define EEMG_DESCHAR (EEMG_BASEADDR + 0xC00)
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#define EEMG_TEMPCHAR (EEMG_BASEADDR + 0xC04)
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#define EEMG_DETCHAR (EEMG_BASEADDR + 0xC08)
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#define EEMG_AGECHAR (EEMG_BASEADDR + 0xC0C)
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#define EEMG_DCCONFIG (EEMG_BASEADDR + 0xC10)
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#define EEMG_AGECONFIG (EEMG_BASEADDR + 0xC14)
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#define EEMG_FREQPCT30 (EEMG_BASEADDR + 0xC18)
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#define EEMG_FREQPCT74 (EEMG_BASEADDR + 0xC1C)
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#define EEMG_LIMITVALS (EEMG_BASEADDR + 0xC20)
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#define EEMG_VBOOT (EEMG_BASEADDR + 0xC24)
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#define EEMG_DETWINDOW (EEMG_BASEADDR + 0xC28)
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#define EEMGCONFIG (EEMG_BASEADDR + 0xC2C)
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#define EEMG_TSCALCS (EEMG_BASEADDR + 0xC30)
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#define EEMG_RUNCONFIG (EEMG_BASEADDR + 0xC34)
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#define EEMGEN (EEMG_BASEADDR + 0xC38)
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#define EEMG_INIT2VALS (EEMG_BASEADDR + 0xC3C)
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#define EEMG_DCVALUES (EEMG_BASEADDR + 0xC40)
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#define EEMG_AGEVALUES (EEMG_BASEADDR + 0xC44)
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#define EEMG_VOP30 (EEMG_BASEADDR + 0xC48)
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#define EEMG_VOP74 (EEMG_BASEADDR + 0xC4C)
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#define TEMPG (EEMG_BASEADDR + 0xC50)
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#define EEMGINTSTS (EEMG_BASEADDR + 0xC54)
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#define EEMGINTSTSRAW (EEMG_BASEADDR + 0xC58)
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#define EEMGINTEN (EEMG_BASEADDR + 0xC5C)
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#define EEMG_CHKSHIFT (EEMG_BASEADDR + 0xC64)
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#define EEMG_VDESIGN30 (EEMG_BASEADDR + 0xC6C)
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#define EEMG_VDESIGN74 (EEMG_BASEADDR + 0xC70)
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#define EEMG_AGECOUNT (EEMG_BASEADDR + 0xC7C)
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#define EEMG_SMSTATE0 (EEMG_BASEADDR + 0xC80)
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#define EEMG_SMSTATE1 (EEMG_BASEADDR + 0xC84)
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#define EEMG_CTL0 (EEMG_BASEADDR + 0xC88)
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#define EEMGCORESEL (EEMG_BASEADDR + 0xF00)
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#define EEMG_THERMINTST (EEMG_BASEADDR + 0xF04)
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#define EEMGODINTST (EEMG_BASEADDR + 0xF08)
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#define EEMG_THSTAGE0ST (EEMG_BASEADDR + 0xF0C)
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#define EEMG_THSTAGE1ST (EEMG_BASEADDR + 0xF10)
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#define EEMG_THSTAGE2ST (EEMG_BASEADDR + 0xF14)
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#define EEMG_THAHBST0 (EEMG_BASEADDR + 0xF18)
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#define EEMG_THAHBST1 (EEMG_BASEADDR + 0xF1C)
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#define EEMGSPARE0 (EEMG_BASEADDR + 0xF20)
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#define EEMGSPARE1 (EEMG_BASEADDR + 0xF24)
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#define EEMGSPARE2 (EEMG_BASEADDR + 0xF28)
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#define EEMGSPARE3 (EEMG_BASEADDR + 0xF2C)
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#define EEMG_THSLPEVEB (EEMG_BASEADDR + 0xF30)
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#define EEMG_THERMAL (EEMG_BASEADDR + 0x848)
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#endif
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