228 lines
5.8 KiB
C
228 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef _MT_RSC_H
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#define _MT_RSC_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/*
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* enforce kernel log enable
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*/
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_RSC_FRAME_REQUEST_ 6
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#define _SUPPORT_MAX_RSC_REQUEST_RING_SIZE_ 4
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/*
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*
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*/
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#define RSC_DEV_MAJOR_NUMBER 251
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#define RSC_MAGIC 'r'
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#define RSC_REG_RANGE (0x1000)
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#define RSC_BASE_HW 0x1b003000
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/*This macro is for setting irq status represnted
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* by a local variable,RSCInfo.IrqInfo.Status[RSC_IRQ_TYPE_INT_RSC_ST]
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*/
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#define RSC_INT_ST (1<<0)
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struct RSC_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct RSC_REG_IO_STRUCT {
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struct RSC_REG_STRUCT *pData; /* pointer to RSC_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/*
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* interrupt clear type
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*/
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enum RSC_IRQ_CLEAR_ENUM {
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RSC_IRQ_CLEAR_NONE, /* non-clear wait, clear after wait */
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RSC_IRQ_CLEAR_WAIT, /* clear wait, clear before and after wait */
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RSC_IRQ_WAIT_CLEAR,
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/* wait the signal and clear it, avoid hw executime is too s hort. */
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RSC_IRQ_CLEAR_STATUS, /* clear specific status only */
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RSC_IRQ_CLEAR_ALL /* clear all status */
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};
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/*
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum RSC_IRQ_TYPE_ENUM {
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RSC_IRQ_TYPE_INT_RSC_ST, /* RSC */
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RSC_IRQ_TYPE_AMOUNT
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};
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struct RSC_WAIT_IRQ_STRUCT {
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enum RSC_IRQ_CLEAR_ENUM Clear;
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enum RSC_IRQ_TYPE_ENUM Type;
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unsigned int Status; /*IRQ Status */
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unsigned int Timeout;
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int UserKey; /* user key for doing interrupt operation */
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int ProcessID; /* user ProcessID (will filled in kernel) */
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unsigned int bDumpReg; /* check dump register or not */
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};
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struct RSC_CLEAR_IRQ_STRUCT {
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enum RSC_IRQ_TYPE_ENUM Type;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status; /* Input */
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};
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struct RSC_Config {
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unsigned int RSC_CTRL;
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unsigned int RSC_SIZE;
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unsigned int RSC_IMGI_C_BASE_ADDR;
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unsigned int RSC_IMGI_C_FD;
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unsigned int RSC_IMGI_C_OFFSET;
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unsigned int RSC_IMGI_C_STRIDE;
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unsigned int RSC_IMGI_P_BASE_ADDR;
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unsigned int RSC_IMGI_P_FD;
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unsigned int RSC_IMGI_P_OFFSET;
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unsigned int RSC_IMGI_P_STRIDE;
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unsigned int RSC_MVI_BASE_ADDR;
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unsigned int RSC_MVI_FD;
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unsigned int RSC_MVI_OFFSET;
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unsigned int RSC_MVI_STRIDE;
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unsigned int RSC_APLI_C_BASE_ADDR;
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unsigned int RSC_APLI_C_FD;
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unsigned int RSC_APLI_C_OFFSET;
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unsigned int RSC_APLI_P_BASE_ADDR;
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unsigned int RSC_APLI_P_FD;
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unsigned int RSC_APLI_P_OFFSET;
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unsigned int RSC_MVO_BASE_ADDR;
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unsigned int RSC_MVO_FD;
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unsigned int RSC_MVO_OFFSET;
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unsigned int RSC_MVO_STRIDE;
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unsigned int RSC_BVO_BASE_ADDR;
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unsigned int RSC_BVO_FD;
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unsigned int RSC_BVO_OFFSET;
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unsigned int RSC_BVO_STRIDE;
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unsigned int IS_LEGACY;
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#define RSC_TUNABLE
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#ifdef RSC_TUNABLE
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unsigned int RSC_MV_OFFSET;
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unsigned int RSC_GMV_OFFSET;
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unsigned int RSC_CAND_NUM;
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unsigned int RSC_RAND_HORZ_LUT;
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unsigned int RSC_RAND_VERT_LUT;
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unsigned int RSC_SAD_CTRL;
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unsigned int RSC_SAD_EDGE_GAIN_CTRL;
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unsigned int RSC_SAD_CRNR_GAIN_CTRL;
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unsigned int RSC_STILL_STRIP_CTRL0;
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unsigned int RSC_STILL_STRIP_CTRL1;
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unsigned int RSC_RAND_PNLTY_CTRL;
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unsigned int RSC_RAND_PNLTY_GAIN_CTRL0;
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unsigned int RSC_RAND_PNLTY_GAIN_CTRL1;
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#endif
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unsigned int RSC_STA_0;
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};
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/*
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*
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*/
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enum RSC_CMD_ENUM {
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RSC_CMD_RESET, /* Reset */
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RSC_CMD_DUMP_REG, /* Dump RSC Register */
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RSC_CMD_DUMP_ISR_LOG, /* Dump RSC ISR log */
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RSC_CMD_READ_REG, /* Read register from driver */
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RSC_CMD_WRITE_REG, /* Write register to driver */
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RSC_CMD_WAIT_IRQ, /* Wait IRQ */
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RSC_CMD_CLEAR_IRQ, /* Clear IRQ */
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RSC_CMD_ENQUE_NUM, /* RSC Enque Number */
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RSC_CMD_ENQUE, /* RSC Enque */
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RSC_CMD_ENQUE_REQ, /* RSC Enque Request */
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RSC_CMD_DEQUE_NUM, /* RSC Deque Number */
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RSC_CMD_DEQUE, /* RSC Deque */
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RSC_CMD_DEQUE_REQ, /* RSC Deque Request */
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RSC_CMD_TOTAL,
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};
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struct RSC_Request {
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unsigned int m_ReqNum;
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struct RSC_Config *m_pRscConfig;
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};
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#ifdef CONFIG_COMPAT
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struct compat_RSC_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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struct compat_RSC_Request {
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unsigned int m_ReqNum;
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compat_uptr_t m_pRscConfig;
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};
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#endif
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#define RSC_RESET _IO(RSC_MAGIC, RSC_CMD_RESET)
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#define RSC_DUMP_REG _IO(RSC_MAGIC, RSC_CMD_DUMP_REG)
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#define RSC_DUMP_ISR_LOG _IO(RSC_MAGIC, RSC_CMD_DUMP_ISR_LOG)
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#define RSC_READ_REGISTER \
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_IOWR(RSC_MAGIC, RSC_CMD_READ_REG, struct RSC_REG_IO_STRUCT)
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#define RSC_WRITE_REGISTER \
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_IOWR(RSC_MAGIC, RSC_CMD_WRITE_REG, struct RSC_REG_IO_STRUCT)
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#define RSC_WAIT_IRQ \
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_IOW(RSC_MAGIC, RSC_CMD_WAIT_IRQ, struct RSC_WAIT_IRQ_STRUCT)
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#define RSC_CLEAR_IRQ \
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_IOW(RSC_MAGIC, RSC_CMD_CLEAR_IRQ, struct RSC_CLEAR_IRQ_STRUCT)
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#define RSC_ENQNUE_NUM _IOW(RSC_MAGIC, RSC_CMD_ENQUE_NUM, int)
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#define RSC_ENQUE _IOWR(RSC_MAGIC, RSC_CMD_ENQUE, struct RSC_Config)
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#define RSC_ENQUE_REQ _IOWR(RSC_MAGIC, RSC_CMD_ENQUE_REQ, struct RSC_Request)
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#define RSC_DEQUE_NUM _IOR(RSC_MAGIC, RSC_CMD_DEQUE_NUM, int)
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#define RSC_DEQUE _IOWR(RSC_MAGIC, RSC_CMD_DEQUE, struct RSC_Config)
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#define RSC_DEQUE_REQ _IOWR(RSC_MAGIC, RSC_CMD_DEQUE_REQ, struct RSC_Request)
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#ifdef CONFIG_COMPAT
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#define COMPAT_RSC_WRITE_REGISTER \
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_IOWR(RSC_MAGIC, RSC_CMD_WRITE_REG, struct compat_RSC_REG_IO_STRUCT)
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#define COMPAT_RSC_READ_REGISTER \
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_IOWR(RSC_MAGIC, RSC_CMD_READ_REG, struct compat_RSC_REG_IO_STRUCT)
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#define COMPAT_RSC_ENQUE_REQ \
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_IOWR(RSC_MAGIC, RSC_CMD_ENQUE_REQ, struct compat_RSC_Request)
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#define COMPAT_RSC_DEQUE_REQ \
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_IOWR(RSC_MAGIC, RSC_CMD_DEQUE_REQ, struct compat_RSC_Request)
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#endif
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#endif
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