569 lines
17 KiB
C
569 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef _MT_DPE_H
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#define _MT_DPE_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/*
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* enforce kernel log enable
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*/
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_DPE_FRAME_REQUEST_ 12 // 6
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#define _SUPPORT_MAX_DPE_REQUEST_RING_SIZE_ 4
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/*
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*
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*/
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#define DPE_DEV_MAJOR_NUMBER 302
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#define DPE_MAGIC 'd'
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#define DPE_REG_RANGE (0x1000)
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#define DPE_BASE_HW 0x1B100000
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/*This macro is for setting irq status represnted
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* by a local variable,DPEInfo.IrqInfo.Status[DPE_IRQ_TYPE_INT_DPE_ST]
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*/
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#define DPE_INT_ST (1UL<<31)
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// MEDV buffer width size should be 64B align
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// All other buffer width size should be 128B align
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// Assume max width = 640 should meet above requirements
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#define DPE_MAX_FRAME_SIZE 307200 //640x480
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#define WB_INT_MEDV_SIZE DPE_MAX_FRAME_SIZE
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#define WB_DCV_L_SIZE DPE_MAX_FRAME_SIZE
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#define WB_ASFRM_SIZE DPE_MAX_FRAME_SIZE
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#define WB_ASFRMExt_SIZE DPE_MAX_FRAME_SIZE
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#define WB_WMFHF_SIZE DPE_MAX_FRAME_SIZE
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#define WB_TOTAL_SIZE \
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(WB_INT_MEDV_SIZE+WB_DCV_L_SIZE+ \
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WB_ASFRM_SIZE+WB_ASFRMExt_SIZE+WB_WMFHF_SIZE)
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// ----------------- DPE_DVS_ME Grouping Definitions -------------------
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struct DVS_ME_CFG {
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unsigned int DVS_ME_00; //1B100300
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unsigned int DVS_ME_01; //1B100304
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unsigned int DVS_ME_02; //1B100308
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unsigned int DVS_ME_03; //1B10030C
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unsigned int DVS_ME_04; //1B100310
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unsigned int DVS_ME_05; //1B100314
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unsigned int DVS_ME_06; //1B100318
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unsigned int DVS_ME_07; //1B10031C
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unsigned int DVS_ME_08; //1B100320
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unsigned int DVS_ME_09; //1B100324
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unsigned int DVS_ME_10; //1B100328
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unsigned int DVS_ME_11; //1B10032C
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unsigned int DVS_ME_12; //1B100330
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unsigned int DVS_ME_13; //1B100334
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unsigned int DVS_ME_14; //1B100338
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unsigned int DVS_ME_15; //1B10033C
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unsigned int DVS_ME_16; //1B100340
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unsigned int DVS_ME_17; //1B100344
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unsigned int DVS_ME_18; //1B100348
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unsigned int DVS_ME_19; //1B10034C
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unsigned int DVS_ME_20; //1B100350
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unsigned int DVS_ME_21; //1B100354
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unsigned int DVS_ME_22; //1B100358
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unsigned int DVS_ME_23; //1B10035C
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unsigned int DVS_ME_24; //1B100360
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};
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// ----------------- DPE_DVS_OCC Grouping Definitions -------------------
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struct DVS_OCC_CFG {
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unsigned int DVS_OCC_PQ_0; //1B1003A0
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unsigned int DVS_OCC_PQ_1; //1B1003A4
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unsigned int DVS_OCC_PQ_2; //1B1003A8
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unsigned int DVS_OCC_PQ_3; //1B1003AC
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unsigned int DVS_OCC_PQ_4; //1B1003B0
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unsigned int DVS_OCC_PQ_5; //1B1003B4
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};
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// ----------------- DPE_DVP_CTRL Grouping Definitions -------------------
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struct DVP_CORE_CFG {
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unsigned int DVP_CORE_00; //1B100900
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unsigned int DVP_CORE_01; //1B100904
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unsigned int DVP_CORE_02; //1B100908
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unsigned int DVP_CORE_03; //1B10090C
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unsigned int DVP_CORE_04; //1B100910
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unsigned int DVP_CORE_05; //1B100914
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unsigned int DVP_CORE_06; //1B100918
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unsigned int DVP_CORE_07; //1B10091C
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unsigned int DVP_CORE_08; //1B100920
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unsigned int DVP_CORE_09; //1B100924
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unsigned int DVP_CORE_10; //1B100928
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unsigned int DVP_CORE_11; //1B10092C
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unsigned int DVP_CORE_12; //1B100930
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unsigned int DVP_CORE_13; //1B100934
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unsigned int DVP_CORE_14; //1B100938
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unsigned int DVP_CORE_15; //1B10093C
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};
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// -----------------------------------------------------
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struct DPE_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct DPE_REG_IO_STRUCT {
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struct DPE_REG_STRUCT *pData; /* pointer to DPE_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/*
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* interrupt clear type
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*/
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enum DPE_IRQ_CLEAR_ENUM {
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DPE_IRQ_CLEAR_NONE, /* non-clear wait, clear after wait */
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DPE_IRQ_CLEAR_WAIT, /* clear wait, clear before and after wait */
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DPE_IRQ_WAIT_CLEAR,
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/* wait the signal and clear it, avoid hw executime is too s hort. */
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DPE_IRQ_CLEAR_STATUS, /* clear specific status only */
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DPE_IRQ_CLEAR_ALL /* clear all status */
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};
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/*
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum DPE_IRQ_TYPE_ENUM {
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DPE_IRQ_TYPE_INT_DVP_ST, /* DVP */
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DPE_IRQ_TYPE_INT_DVS_ST, /* DVS */
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DPE_IRQ_TYPE_AMOUNT
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};
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struct DPE_WAIT_IRQ_STRUCT {
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enum DPE_IRQ_CLEAR_ENUM Clear;
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enum DPE_IRQ_TYPE_ENUM Type;
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unsigned int Status; /*IRQ Status */
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unsigned int Timeout;
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int UserKey; /* user key for doing interrupt operation */
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int ProcessID; /* user ProcessID (will filled in kernel) */
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unsigned int bDumpReg; /* check dump register or not */
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};
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struct DPE_CLEAR_IRQ_STRUCT {
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enum DPE_IRQ_TYPE_ENUM Type;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status; /* Input */
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};
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struct DPE_Kernel_Config {
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unsigned int DVS_CTRL00;
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unsigned int DVS_CTRL01;
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unsigned int DVS_CTRL02;
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unsigned int DVS_CTRL03;
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// unsigned int DVS_CTRL04;
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// unsigned int DVS_CTRL05;
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unsigned int DVS_CTRL06;
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unsigned int DVS_CTRL07;
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unsigned int DVS_IRQ_00;
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unsigned int DVS_CTRL_STATUS0;
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// unsigned int DVS_CTRL_STATUS1;
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unsigned int DVS_CTRL_STATUS2;
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unsigned int DVS_IRQ_STATUS;
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unsigned int DVS_FRM_STATUS0;
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unsigned int DVS_FRM_STATUS1;
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// unsigned int DVS_FRM_STATUS2;
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// unsigned int DVS_FRM_STATUS3;
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unsigned int DVS_CUR_STATUS;
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unsigned int DVS_SRC_CTRL;
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unsigned int DVS_CRC_CTRL;
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unsigned int DVS_CRC_IN;
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unsigned int DVS_DRAM_STA0;
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unsigned int DVS_DRAM_STA1;
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unsigned int DVS_DRAM_ULT;
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unsigned int DVS_DRAM_PITCH;
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unsigned int DVS_SRC_00;
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unsigned int DVS_SRC_01;
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unsigned int DVS_SRC_02;
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unsigned int DVS_SRC_03;
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unsigned int DVS_SRC_04;
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unsigned int DVS_SRC_05_L_FRM0;
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unsigned int DVS_SRC_06_L_FRM1;
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unsigned int DVS_SRC_07_L_FRM2;
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unsigned int DVS_SRC_08_L_FRM3;
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unsigned int DVS_SRC_09_R_FRM0;
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unsigned int DVS_SRC_10_R_FRM1;
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unsigned int DVS_SRC_11_R_FRM2;
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unsigned int DVS_SRC_12_R_FRM3;
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unsigned int DVS_SRC_13_L_VMAP0;
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unsigned int DVS_SRC_14_L_VMAP1;
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unsigned int DVS_SRC_15_L_VMAP2;
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unsigned int DVS_SRC_16_L_VMAP3;
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unsigned int DVS_SRC_17_R_VMAP0;
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unsigned int DVS_SRC_18_R_VMAP1;
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unsigned int DVS_SRC_19_R_VMAP2;
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unsigned int DVS_SRC_20_R_VMAP3;
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unsigned int DVS_SRC_21_INTER_MEDV;
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unsigned int DVS_SRC_26_OCCDV0;
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unsigned int DVS_SRC_27_OCCDV1;
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unsigned int DVS_SRC_28_OCCDV2;
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unsigned int DVS_SRC_29_OCCDV3;
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unsigned int DVS_SRC_30_DCV_CONF0;
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unsigned int DVS_SRC_31_DCV_CONF1;
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unsigned int DVS_SRC_32_DCV_CONF2;
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unsigned int DVS_SRC_33_DCV_CONF3;
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unsigned int DVS_SRC_34_DCV_L_FRM0;
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unsigned int DVS_SRC_42_OCCDV_EXT0;
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unsigned int DVS_SRC_43_OCCDV_EXT1;
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unsigned int DVS_SRC_44_OCCDV_EXT2;
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unsigned int DVS_SRC_45_OCCDV_EXT3;
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unsigned int DVS_CRC_OUT_0;
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unsigned int DVS_CRC_OUT_1;
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unsigned int DVS_CRC_OUT_2;
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unsigned int DVS_CRC_OUT_3;
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unsigned int DVS_PD_SRC_00_L_FRM0;
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unsigned int DVS_PD_SRC_01_L_FRM1;
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unsigned int DVS_PD_SRC_02_L_FRM2;
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unsigned int DVS_PD_SRC_03_L_FRM3;
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unsigned int DVS_PD_SRC_04_R_FRM0;
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unsigned int DVS_PD_SRC_05_R_FRM1;
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unsigned int DVS_PD_SRC_06_R_FRM2;
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unsigned int DVS_PD_SRC_07_R_FRM3;
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unsigned int DVS_PD_SRC_08_OCCDV0;
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unsigned int DVS_PD_SRC_09_OCCDV1;
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unsigned int DVS_PD_SRC_10_OCCDV2;
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unsigned int DVS_PD_SRC_11_OCCDV3;
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unsigned int DVS_PD_SRC_12_OCCDV_EXT0;
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unsigned int DVS_PD_SRC_13_OCCDV_EXT1;
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unsigned int DVS_PD_SRC_14_OCCDV_EXT2;
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unsigned int DVS_PD_SRC_15_OCCDV_EXT3;
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unsigned int DVS_PD_SRC_16_DCV_CONF0;
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unsigned int DVS_PD_SRC_17_DCV_CONF1;
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unsigned int DVS_PD_SRC_18_DCV_CONF2;
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unsigned int DVS_PD_SRC_19_DCV_CONF3;
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unsigned int DVS_CTRL_RESERVED;
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unsigned int DVS_CTRL_ATPG;
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unsigned int DVS_ME_00;
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unsigned int DVS_ME_01;
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unsigned int DVS_ME_02;
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unsigned int DVS_ME_03;
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unsigned int DVS_ME_04;
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unsigned int DVS_ME_05;
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unsigned int DVS_ME_06;
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unsigned int DVS_ME_07;
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unsigned int DVS_ME_08;
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unsigned int DVS_ME_09;
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unsigned int DVS_ME_10;
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unsigned int DVS_ME_11;
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unsigned int DVS_ME_12;
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unsigned int DVS_ME_13;
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unsigned int DVS_ME_14;
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unsigned int DVS_ME_15;
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unsigned int DVS_ME_16;
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unsigned int DVS_ME_17;
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unsigned int DVS_ME_18;
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unsigned int DVS_ME_19;
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unsigned int DVS_ME_20;
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unsigned int DVS_ME_21;
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unsigned int DVS_ME_22;
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unsigned int DVS_ME_23;
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unsigned int DVS_ME_24;
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unsigned int DVS_DEBUG;
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unsigned int DVS_ME_RESERVED;
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unsigned int DVS_ME_ATPG;
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unsigned int DVS_OCC_PQ_0;
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unsigned int DVS_OCC_PQ_1;
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unsigned int DVS_OCC_PQ_2;
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unsigned int DVS_OCC_PQ_3;
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unsigned int DVS_OCC_PQ_4;
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unsigned int DVS_OCC_PQ_5;
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unsigned int DVS_OCC_ATPG;
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unsigned int DVP_CTRL00;
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unsigned int DVP_CTRL01;
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unsigned int DVP_CTRL02;
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unsigned int DVP_CTRL03;
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unsigned int DVP_CTRL04;
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// unsigned int DVP_CTRL05;
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// unsigned int DVP_CTRL06;
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unsigned int DVP_CTRL07;
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unsigned int DVP_IRQ_00;
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unsigned int DVP_CTRL_STATUS0;
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unsigned int DVP_CTRL_STATUS1;
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unsigned int DVP_CTRL_STATUS2;
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unsigned int DVP_IRQ_STATUS;
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unsigned int DVP_FRM_STATUS0;
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// unsigned int DVP_FRM_STATUS1;
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unsigned int DVP_FRM_STATUS2;
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// unsigned int DVP_FRM_STATUS3;
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unsigned int DVP_CUR_STATUS;
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unsigned int DVP_SRC_00;
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unsigned int DVP_SRC_01;
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unsigned int DVP_SRC_02;
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unsigned int DVP_SRC_03;
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unsigned int DVP_SRC_04;
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unsigned int DVP_SRC_05_Y_FRM0;
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unsigned int DVP_SRC_06_Y_FRM1;
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unsigned int DVP_SRC_07_Y_FRM2;
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unsigned int DVP_SRC_08_Y_FRM3;
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unsigned int DVP_SRC_09_C_FRM0;
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unsigned int DVP_SRC_10_C_FRM1;
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unsigned int DVP_SRC_11_C_FRM2;
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unsigned int DVP_SRC_12_C_FRM3;
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unsigned int DVP_SRC_13_OCCDV0;
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unsigned int DVP_SRC_14_OCCDV1;
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unsigned int DVP_SRC_15_OCCDV2;
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unsigned int DVP_SRC_16_OCCDV3;
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unsigned int DVP_SRC_17_CRM;
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unsigned int DVP_SRC_18_ASF_RMDV;
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unsigned int DVP_SRC_19_ASF_RDDV;
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unsigned int DVP_SRC_20_ASF_DV0;
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unsigned int DVP_SRC_21_ASF_DV1;
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unsigned int DVP_SRC_22_ASF_DV2;
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unsigned int DVP_SRC_23_ASF_DV3;
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unsigned int DVP_SRC_24_WMF_HFDV;
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unsigned int DVP_SRC_25_WMF_DV0;
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unsigned int DVP_SRC_26_WMF_DV1;
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unsigned int DVP_SRC_27_WMF_DV2;
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unsigned int DVP_SRC_28_WMF_DV3;
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unsigned int DVP_CORE_00;
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unsigned int DVP_CORE_01;
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unsigned int DVP_CORE_02;
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unsigned int DVP_CORE_03;
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unsigned int DVP_CORE_04;
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unsigned int DVP_CORE_05;
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unsigned int DVP_CORE_06;
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unsigned int DVP_CORE_07;
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unsigned int DVP_CORE_08;
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unsigned int DVP_CORE_09;
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unsigned int DVP_CORE_10;
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unsigned int DVP_CORE_11;
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unsigned int DVP_CORE_12;
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unsigned int DVP_CORE_13;
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unsigned int DVP_CORE_14;
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unsigned int DVP_CORE_15;
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unsigned int DVP_SRC_CTRL;
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unsigned int DVP_CTRL_RESERVED;
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unsigned int DVP_CTRL_ATPG;
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unsigned int DVP_CRC_OUT_0;
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unsigned int DVP_CRC_OUT_1;
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unsigned int DVP_CRC_OUT_2;
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unsigned int DVP_CRC_CTRL;
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unsigned int DVP_CRC_OUT;
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unsigned int DVP_CRC_IN;
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unsigned int DVP_DRAM_STA;
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unsigned int DVP_DRAM_ULT;
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unsigned int DVP_DRAM_PITCH;
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unsigned int DVP_CORE_CRC_IN;
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unsigned int DVP_EXT_SRC_13_OCCDV0;
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unsigned int DVP_EXT_SRC_14_OCCDV1;
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unsigned int DVP_EXT_SRC_15_OCCDV2;
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unsigned int DVP_EXT_SRC_16_OCCDV3;
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unsigned int DVP_EXT_SRC_18_ASF_RMDV;
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unsigned int DVP_EXT_SRC_19_ASF_RDDV;
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unsigned int DVP_EXT_SRC_20_ASF_DV0;
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unsigned int DVP_EXT_SRC_21_ASF_DV1;
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unsigned int DVP_EXT_SRC_22_ASF_DV2;
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unsigned int DVP_EXT_SRC_23_ASF_DV3;
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//unsigned int USERDUMP_EN;
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unsigned int DPE_MODE;
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};
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enum DPEMODE {
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MODE_DVS_DVP_BOTH = 0,
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MODE_DVS_ONLY,
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MODE_DVP_ONLY
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};
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enum DPE_MAINEYE_SEL {
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LEFT = 0,
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RIGHT = 1
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};
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struct DVS_SubModule_EN {
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bool sbf_en;
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bool conf_en;
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bool occ_en;
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};
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struct DVP_SubModule_EN {
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bool asf_crm_en;
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bool asf_rm_en;
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bool asf_rd_en;
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bool asf_hf_en;
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bool wmf_hf_en;
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bool wmf_filt_en;
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unsigned int asf_hf_rounds;
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unsigned int asf_nb_rounds;
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unsigned int wmf_filt_rounds;
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bool asf_recursive_en;
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};
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struct DVS_Iteration {
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unsigned int y_IterTimes;
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unsigned int y_IterStartDirect_0;
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unsigned int y_IterStartDirect_1;
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unsigned int x_IterStartDirect_0;
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unsigned int x_IterStartDirect_1;
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};
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struct DPE_feedback {
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unsigned int reg1;
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unsigned int reg2;
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};
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struct DVS_Settings {
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enum DPE_MAINEYE_SEL mainEyeSel;
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struct DVS_ME_CFG TuningBuf_ME;
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struct DVS_OCC_CFG TuningBuf_OCC;
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struct DVS_SubModule_EN SubModule_EN;
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struct DVS_Iteration Iteration;
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bool is_pd_mode;
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unsigned int pd_frame_num; // set by driver
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unsigned int pd_st_x; // set by driver
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unsigned int frmWidth;
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unsigned int frmHeight;
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unsigned int L_engStart_x;
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unsigned int R_engStart_x;
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unsigned int engStart_y;
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unsigned int engWidth;
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unsigned int engHeight;
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unsigned int occWidth;
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unsigned int occStart_x;
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unsigned int pitch;
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};
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struct DVP_Settings {
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enum DPE_MAINEYE_SEL mainEyeSel;
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bool Y_only;
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struct DVP_CORE_CFG TuningBuf_CORE;
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struct DVP_SubModule_EN SubModule_EN;
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bool disp_guide_en;
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unsigned int frmWidth;
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unsigned int frmHeight;
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unsigned int engStart_x;
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unsigned int engStart_y;
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unsigned int engWidth;
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unsigned int engHeight;
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};
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|
|
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struct DPE_Config {
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enum DPEMODE Dpe_engineSelect;
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unsigned int Dpe_is16BitMode;
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struct DVS_Settings Dpe_DVSSettings;
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|
struct DVP_Settings Dpe_DVPSettings;
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|
unsigned int Dpe_InBuf_SrcImg_Y_L;
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|
unsigned int Dpe_InBuf_SrcImg_Y_R;
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|
unsigned int Dpe_InBuf_SrcImg_Y;
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unsigned int Dpe_InBuf_SrcImg_C;
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unsigned int Dpe_InBuf_ValidMap_L;
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unsigned int Dpe_InBuf_ValidMap_R;
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|
unsigned int Dpe_OutBuf_CONF;
|
|
unsigned int Dpe_OutBuf_OCC;
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|
unsigned int Dpe_OutBuf_OCC_Ext;
|
|
|
|
unsigned int Dpe_InBuf_OCC;
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|
unsigned int Dpe_InBuf_OCC_Ext;
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|
unsigned int Dpe_OutBuf_CRM;
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|
//unsigned int Dpe_OutBuf_ASF_RM;
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|
//unsigned int Dpe_OutBuf_ASF_RM_Ext;
|
|
unsigned int Dpe_OutBuf_ASF_RD;
|
|
unsigned int Dpe_OutBuf_ASF_RD_Ext;
|
|
unsigned int Dpe_OutBuf_ASF_HF;
|
|
unsigned int Dpe_OutBuf_ASF_HF_Ext;
|
|
//MUINT32 Dpe_OutBuf_WMF_HF;
|
|
unsigned int Dpe_OutBuf_WMF_FILT;
|
|
|
|
unsigned int DVS_SRC_21_INTER_MEDV;
|
|
unsigned int DVS_SRC_34_DCV_L_FRM0;
|
|
unsigned int DVP_SRC_18_ASF_RMDV;
|
|
unsigned int DVP_SRC_24_WMF_HFDV;
|
|
unsigned int DVP_EXT_SRC_18_ASF_RMDV;
|
|
struct DPE_feedback Dpe_feedback;
|
|
};
|
|
|
|
/*
|
|
*
|
|
*/
|
|
enum DPE_CMD_ENUM {
|
|
DPE_CMD_RESET, /* Reset */
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|
DPE_CMD_DUMP_REG, /* Dump DPE Register */
|
|
DPE_CMD_DUMP_ISR_LOG, /* Dump DPE ISR log */
|
|
DPE_CMD_READ_REG, /* Read register from driver */
|
|
DPE_CMD_WRITE_REG, /* Write register to driver */
|
|
DPE_CMD_WAIT_IRQ, /* Wait IRQ */
|
|
DPE_CMD_CLEAR_IRQ, /* Clear IRQ */
|
|
DPE_CMD_ENQUE_NUM, /* DPE Enque Number */
|
|
DPE_CMD_ENQUE, /* DPE Enque */
|
|
DPE_CMD_ENQUE_REQ, /* DPE Enque Request */
|
|
DPE_CMD_DEQUE_NUM, /* DPE Deque Number */
|
|
DPE_CMD_DEQUE, /* DPE Deque */
|
|
DPE_CMD_DEQUE_REQ, /* DPE Deque Request */
|
|
DPE_CMD_TOTAL,
|
|
};
|
|
/* */
|
|
|
|
struct DPE_Request {
|
|
unsigned int m_ReqNum;
|
|
struct DPE_Config *m_pDpeConfig;
|
|
};
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
struct compat_DPE_REG_IO_STRUCT {
|
|
compat_uptr_t pData;
|
|
unsigned int Count; /* count */
|
|
};
|
|
|
|
struct compat_DPE_Request {
|
|
unsigned int m_ReqNum;
|
|
compat_uptr_t m_pDpeConfig;
|
|
};
|
|
|
|
#endif
|
|
|
|
#define DPE_RESET _IO(DPE_MAGIC, DPE_CMD_RESET)
|
|
#define DPE_DUMP_REG _IO(DPE_MAGIC, DPE_CMD_DUMP_REG)
|
|
#define DPE_DUMP_ISR_LOG _IO(DPE_MAGIC, DPE_CMD_DUMP_ISR_LOG)
|
|
|
|
#define DPE_READ_REGISTER \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_READ_REG, struct DPE_REG_IO_STRUCT)
|
|
#define DPE_WRITE_REGISTER \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_WRITE_REG, struct DPE_REG_IO_STRUCT)
|
|
#define DPE_WAIT_IRQ \
|
|
_IOW(DPE_MAGIC, DPE_CMD_WAIT_IRQ, struct DPE_WAIT_IRQ_STRUCT)
|
|
#define DPE_CLEAR_IRQ \
|
|
_IOW(DPE_MAGIC, DPE_CMD_CLEAR_IRQ, struct DPE_CLEAR_IRQ_STRUCT)
|
|
|
|
#define DPE_ENQNUE_NUM _IOW(DPE_MAGIC, DPE_CMD_ENQUE_NUM, int)
|
|
#define DPE_ENQUE _IOWR(DPE_MAGIC, DPE_CMD_ENQUE, struct DPE_Config)
|
|
#define DPE_ENQUE_REQ _IOWR(DPE_MAGIC, DPE_CMD_ENQUE_REQ, struct DPE_Request)
|
|
|
|
#define DPE_DEQUE_NUM _IOR(DPE_MAGIC, DPE_CMD_DEQUE_NUM, int)
|
|
#define DPE_DEQUE _IOWR(DPE_MAGIC, DPE_CMD_DEQUE, struct DPE_Config)
|
|
#define DPE_DEQUE_REQ _IOWR(DPE_MAGIC, DPE_CMD_DEQUE_REQ, struct DPE_Request)
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
#define COMPAT_DPE_WRITE_REGISTER \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_WRITE_REG, struct compat_DPE_REG_IO_STRUCT)
|
|
#define COMPAT_DPE_READ_REGISTER \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_READ_REG, struct compat_DPE_REG_IO_STRUCT)
|
|
|
|
#define COMPAT_DPE_ENQUE_REQ \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_ENQUE_REQ, struct compat_DPE_Request)
|
|
#define COMPAT_DPE_DEQUE_REQ \
|
|
_IOWR(DPE_MAGIC, DPE_CMD_DEQUE_REQ, struct compat_DPE_Request)
|
|
#endif
|
|
|
|
/* */
|
|
#endif
|