317 lines
7.6 KiB
C
317 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __HAL_PUB_H_
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#define __HAL_PUB_H_
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/kfifo.h>
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#include <linux/vmalloc.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/sched/rt.h>
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#ifdef CONFIG_OF
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#else
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#include <mach/mt_reg_base.h>
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#include <mach/mt_irq.h>
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#endif
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#if defined(CONFIG_MTK_CLKMGR)
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#include <mach/mt_clkmgr.h>
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#else
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#endif /* defined(CONFIG_MTK_CLKMGR) */
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extern int mtk_btif_hal_get_log_lvl(void);
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#define MTK_BTIF_MARK_UNUSED_API
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#define MTK_BTIF_ENABLE_CLK_CTL 1
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#define MTK_BTIF_ENABLE_CLK_REF_COUNTER 1
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#define DBG_LOG_STR_SIZE 256
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/*Log defination*/
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static int hal_log_print(const char *str, ...)
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{
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va_list args;
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int ret;
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char temp_sring[DBG_LOG_STR_SIZE];
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va_start(args, str);
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ret = vsnprintf(temp_sring, DBG_LOG_STR_SIZE, str, args);
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va_end(args);
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if (ret > 0)
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pr_info("%s", temp_sring);
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return ret;
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}
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#define BTIF_LOG_LOUD 4
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#define BTIF_LOG_DBG 3
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#define BTIF_LOG_INFO 2
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#define BTIF_LOG_WARN 1
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#define BTIF_LOG_ERR 0
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#ifndef DFT_TAG
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#define DFT_TAG "[BTIF-DFT]"
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#endif
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#define BTIF_LOUD_FUNC(fmt, arg ...) \
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do { \
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_LOUD) \
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hal_log_print(DFT_TAG "[L]%s:" fmt, \
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__func__, ## arg); \
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} while (0)
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#define BTIF_INFO_FUNC(fmt, arg ...) \
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do { \
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_INFO)\
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hal_log_print(DFT_TAG "[I]%s:" fmt, \
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__func__, ## arg); \
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} while (0)
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#define BTIF_WARN_FUNC(fmt, arg ...) \
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do { \
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_WARN)\
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hal_log_print(DFT_TAG "[W]%s:" fmt, \
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__func__, ## arg); \
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} while (0)
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#define BTIF_ERR_FUNC(fmt, arg ...)\
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do {\
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_ERR)\
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hal_log_print(DFT_TAG "[E]%s(%d):" fmt,\
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__func__, __LINE__, ## arg);\
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} while (0)
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#define BTIF_DBG_FUNC(fmt, arg ...) \
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do { \
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_DBG) \
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hal_log_print(DFT_TAG "[D]%s:" fmt, \
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__func__, ## arg); \
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} while (0)
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#define BTIF_TRC_FUNC(f) \
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do { \
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if (mtk_btif_hal_get_log_lvl() >= BTIF_LOG_DBG) \
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hal_log_print(DFT_TAG "<%s> <%d>\n", \
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__func__, __LINE__); \
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} while (0)
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/*-------------------------------Enum Defination----------------------------*/
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/*IRQ sensetive type */
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enum _ENUM_IRQ_SENS_TYPE_ {
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IRQ_SENS_EDGE = 0,
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IRQ_SENS_LVL = IRQ_SENS_EDGE + 1,
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IRQ_SENS_TYPE_MAX
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};
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/*IRQ level trigger type */
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enum _ENUM_IRQ_LVL_TYPE_ {
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IRQ_LVL_LOW = 0,
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IRQ_LVL_HIGH = IRQ_LVL_LOW + 1,
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IRQ_LVL_MAX
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};
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/*IRQ edge trigger type */
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enum _ENUM_IRQ_EDGE_TYPE_ {
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IRQ_EDGE_FALL = 0,
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IRQ_EDGE_RAISE = IRQ_EDGE_FALL + 1,
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IRQ_EDGE_BOTH = IRQ_EDGE_RAISE + 1,
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IRQ_EDGE_MAX
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};
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enum _ENUM_CLOCK_CTRL_ {
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CLK_OUT_DISABLE = 0,
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CLK_OUT_ENABLE = CLK_OUT_DISABLE + 1,
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CLK_OUT_MAX
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};
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/*Error No. table */
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enum _ENUM_ERROR_CODE_ {
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ERR_NO_ERROR = 0,
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ERR_INVALID_PAR = ERR_NO_ERROR - 1,
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ERR_MAX = ERR_INVALID_PAR - 1,
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};
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enum _ENUM_BTIF_DIR_ {
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BTIF_TX = 0,
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BTIF_RX = BTIF_TX + 1,
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BTIF_DIR_MAX,
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};
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enum _ENUM_DMA_DIR_ {
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DMA_DIR_RX = 0,
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DMA_DIR_TX = DMA_DIR_RX + 1,
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DMA_DIR_BOTH,
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};
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enum _ENUM_BTIF_REG_ID_ {
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REG_IIR = 0, /*Interrupt Identification Register */
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REG_LSR = 1, /*Line Status Register */
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REG_FAKE_LCR = 2, /*Fake Lcr Regiseter */
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REG_FIFO_CTRL = 3, /*FIFO Control Register */
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REG_IER = 4, /*Interrupt Enable Register */
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REG_SLEEP_EN = 5, /*Sleep Enable Register */
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REG_RTO_COUNTER = 6, /*Rx Timeout Counter Register */
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REG_DMA_EN = 7, /*DMA Enalbe Register */
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REG_TRIG_LVL = 8, /*Tx/Rx Trigger Level Register */
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REG_WAT_TIME = 9, /*Async Wait Time Register */
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REG_HANDSHAKE = 10, /*New HandShake Mode Register */
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REG_SLP_WAK = 11, /*Sleep Wakeup Reigster */
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REG_ALL = 12, /*all registers */
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REG_IRQ = 13, /*IRQ registers */
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REG_MAX
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};
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enum _MTK_BTIF_PM_OPID_ {
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BTIF_PM_DPIDLE_EN,
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BTIF_PM_DPIDLE_DIS,
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BTIF_PM_SUSPEND,
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BTIF_PM_RESUME,
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BTIF_PM_RESTORE_NOIRQ,
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};
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#define BTIF_HAL_TX_FIFO_SIZE (1024 * 4)
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/*----------------------------Enum Defination End---------------------------*/
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/*****************************structure definition***************************/
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/*IRQ related information*/
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struct _MTK_BTIF_IRQ_STR_ {
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const char *name;
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bool is_irq_sup;
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unsigned int irq_id;
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#ifdef CONFIG_OF
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unsigned int irq_flags;
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#else
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enum _ENUM_IRQ_SENS_TYPE_ sens_type;
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union {
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enum _ENUM_IRQ_LVL_TYPE_ lvl_type;
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enum _ENUM_IRQ_EDGE_TYPE_ edge_type;
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};
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#endif
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bool reg_flag;
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irq_handler_t p_irq_handler;
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};
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struct _DMA_VFIFO_ {
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/*[Driver Access] vFIFO memory'svirtual address */
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unsigned char *p_vir_addr;
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/*[HW Access] dma handle, physical address, set to DMA's HW Register */
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dma_addr_t phy_addr;
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/*DMA's vFIFO size */
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unsigned int vfifo_size;
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/*DMA's threshold value */
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unsigned int thre;
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};
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struct _MTK_DMA_INFO_STR_;
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struct _MTK_BTIF_INFO_STR_;
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typedef unsigned int (*dma_rx_buf_write) (
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struct _MTK_DMA_INFO_STR_ *p_dma_info,
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unsigned char *p_buf,
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unsigned int buf_len);
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typedef unsigned int (*btif_rx_buf_write) (
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struct _MTK_BTIF_INFO_STR_ *p_btif_info,
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unsigned char *p_buf,
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unsigned int buf_len);
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/*DMA related information*/
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struct _MTK_DMA_INFO_STR_ {
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unsigned long base;
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enum _ENUM_DMA_DIR_ dir;
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struct _MTK_BTIF_IRQ_STR_ *p_irq;
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dma_rx_buf_write rx_cb;
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struct _DMA_VFIFO_ *p_vfifo;
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};
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/*DMA related information*/
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struct _MTK_BTIF_INFO_STR_ {
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unsigned long base; /*base address */
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struct _MTK_BTIF_IRQ_STR_ *p_irq; /*irq related information */
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unsigned int tx_fifo_size; /*BTIF tx FIFO size */
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unsigned int rx_fifo_size; /*BTIF rx FIFO size */
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unsigned int tx_tri_lvl; /*BTIFtx trigger level in FIFO mode */
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unsigned int rx_tri_lvl; /*BTIFrx trigger level in FIFO mode */
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unsigned int clk_gat_addr; /*clock gating address */
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unsigned int set_bit; /*enable clock gating bit */
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unsigned int clr_bit; /*clear clock gating bit */
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unsigned int rx_data_len; /*rx data length */
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btif_rx_buf_write rx_cb;
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struct kfifo *p_tx_fifo; /*tx fifo */
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spinlock_t tx_fifo_spinlock; /*tx fifo spinlock */
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};
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/**********End of Structure Definition***********/
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/***********register operation***********/
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#ifdef __KERNEL__
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/*byte write <1 byte> */
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#define btif_reg_sync_writeb(v, a) \
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do { \
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writeb(v, (void __iomem *)a); \
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/* call mb () */ \
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mb(); \
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} while (0)
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/*word write <2 byte> */
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#define btif_reg_sync_writew(v, a) \
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do { \
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writew(v, (void __iomem *)a); \
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/* call mb () */ \
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mb(); \
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} while (0)
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/*long write <4 byte> */
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#define btif_reg_sync_writel(v, a) \
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do { \
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writel(v, (void __iomem *)a); \
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/* call mb () */ \
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mb(); \
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} while (0)
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#else
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/*byte write <1 byte> */
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#define btif_reg_sync_writeb(v, a) mt65xx_reg_sync_writeb(v, a)
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/*word write <2 byte> */
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#define btif_reg_sync_writew(v, a) mt65xx_reg_sync_writew(v, a)
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/*long write <4 byte> */
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#define btif_reg_sync_writel(v, a) mt65xx_reg_sync_writel(v, a)
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#endif
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#define BTIF_READ8(REG) __raw_readb((unsigned char *)(REG))
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#define BTIF_READ16(REG) __raw_readw((unsigned short *)(REG))
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#define BTIF_READ32(REG) __raw_readl((unsigned int *)(REG))
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#define BTIF_SET_BIT(REG, BITVAL) do { \
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writel(readl((unsigned int *)(REG)) | ((unsigned int)(BITVAL)), \
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(unsigned int *)(REG)); \
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mb(); /**/ \
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} \
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while (0)
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#define BTIF_CLR_BIT(REG, BITVAL) do { \
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writel(readl((unsigned int *)(REG)) & ~((unsigned int)(BITVAL)), \
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(unsigned int *)(REG)); \
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mb(); /**/\
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} \
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while (0)
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/***********end of register operation *********/
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#endif /*__HAL_PUB_H_*/
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