35 lines
857 B
C
35 lines
857 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef APU_HW_H_
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#define APU_HW_H_
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/* reviser register definition */
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#define UP_NORMAL_DOMAIN_NS (0x0)
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#define UP_PRI_DOMAIN_NS (0x4)
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#define UP_IOMMU_CTRL (0X8)
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#define UP_CORE0_VABASE0 (0xc)
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#define UP_CORE0_MVABASE0 (0x10)
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#define UP_CORE0_VABASE1 (0x14)
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#define UP_CORE0_MVABASE1 (0x18)
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#define USERFW_CTXT (0x1000)
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#define SECUREFW_CTXT (0x1004)
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/* md32_sysctrl register definition */
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#define MD32_SYS_CTRL (0x0)
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#define DBG_BUS_SEL (0x98)
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#define APU_UP_SYS_DBG_EN (1UL << 16)
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#define MD32_CLK_EN (0xb8)
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#define UP_WAKE_HOST_MASK0 (0xbc)
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/* apu_rcx_ao_ctrl register definition */
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#define MD32_PRE_DEFINE (0x0)
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#define MD32_BOOT_CTRL (0x4)
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#define MD32_RUNSTALL (0x8)
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/* apu_mbox register definition */
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#define MBOX_HOST_CONFIG_ADDR (0x48)
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#endif /* APU_HW_H_ */
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