120 lines
4.7 KiB
C
120 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*/
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#ifndef __ADSP_REG_H
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#define __ADSP_REG_H
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/*#define ADSP_BASE in use file */
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#define ADSP_A_INTR_STATUS (ADSP_BASE + 0x0010)
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#define ADSP_B_INTR_STATUS (ADSP_BASE + 0x0014)
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#define INFRABUS_TIMEOUT_IRQ (1 << 24)
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#define ADSP_SW_INT_SET (ADSP_BASE + 0x0018)
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#define ADSP_SW_INT_CLR (ADSP_BASE + 0x001C)
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#define ADSP_A_SW_INT (1 << 0)
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#define ADSP_B_SW_INT (1 << 1)
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#define ADSP_AB_SW_INT (1 << 2)
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#define ADSP_GENERAL_IRQ_SET (ADSP_BASE + 0x0034)
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#define ADSP_GENERAL_IRQ_CLR (ADSP_BASE + 0x0038)
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#define ADSP_A_2HOST_IRQ_BIT (1 << 0)
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#define ADSP_B_2HOST_IRQ_BIT (1 << 1)
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#define ADSP_A_AFE2HOST_IRQ_BIT (1 << 2)
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#define ADSP_B_AFE2HOST_IRQ_BIT (1 << 3)
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#define ADSP_GENERAL_IRQ_INUSED \
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(ADSP_A_2HOST_IRQ_BIT | ADSP_B_2HOST_IRQ_BIT \
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| ADSP_A_AFE2HOST_IRQ_BIT | ADSP_B_AFE2HOST_IRQ_BIT)
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#define ADSP_A_DDREN_REQ (ADSP_BASE + 0x0044)
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#define ADSP_B_DDREN_REQ (ADSP_BASE + 0x0048)
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#define ADSP_SPM_ACK (ADSP_BASE + 0x004C)
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#define ADSP_DDR_REQ_SEL (0x3 << 6)
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#define ADSP_DDR_EN (0x1 << 4)
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#define ADSP_SRCLKENA (0x1 << 3)
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#define ADSP_APSRC_EN (0x1 << 2)
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#define ADSP_VREF18_REQ (0x1 << 1)
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#define ADSP_INFRA_REQ (0x1 << 0)
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#define ADSP_SPM_SRC_BITS (ADSP_DDR_EN | ADSP_SRCLKENA \
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| ADSP_APSRC_EN | ADSP_VREF18_REQ \
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| ADSP_INFRA_REQ)
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#define ADSP_A_SPM_SRC_BITS (0xF << 0)
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#define ADSP_A_IRQ_EN (ADSP_BASE + 0x0050)
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#define ADSP_B_IRQ_EN (ADSP_BASE + 0x0058)
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#define ADSP_A_SPM_WAKEUPSRC (ADSP_BASE + 0x005C)
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#define ADSP_B_SPM_WAKEUPSRC (ADSP_BASE + 0x0060)
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#define ADSP_WAKEUP_SPM (0x1 << 0)
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#define ADSP_SEMAPHORE (ADSP_BASE + 0x0064)
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#define ADSP_B_WDT_REG (ADSP_BASE + 0x0068)
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#define ADSP_B_WDT_INIT_VALUE (ADSP_BASE + 0x006C)
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#define ADSP_B_WDT_CNT (ADSP_BASE + 0x0070)
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#define ADSP_A_WDT_REG (ADSP_BASE + 0x007C)
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#define ADSP_A_WDT_INIT_VALUE (ADSP_BASE + 0x0080)
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#define ADSP_A_WDT_CNT (ADSP_BASE + 0x0084)
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#define ADSP_WDT_TRIGGER (ADSP_A_WDT_INIT_VALUE)
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#define WDT_EN_BIT (1 << 31)
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#define WDT_DIS_BIT (0 << 31)
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#define WDT_KICK_BIT 0
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#define ADSP_CFGREG_RSV_RW_REG0 (ADSP_BASE + 0x008C)
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#define ADSP_CFGREG_RSV_RW_REG1 (ADSP_BASE + 0x0090)
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/* Latch Debug info after WDT */
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#define ADSP_A_WDT_DEBUG_PC_REG (ADSP_BASE + 0x0170)
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#define ADSP_A_WDT_DEBUG_SP_REG (ADSP_BASE + 0x0174)
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/* TODO : add in aee dump */
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#define ADSP_A_WDT_EXCVADDR_REG (ADSP_BASE + 0x0178)
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/* TODO : add in aee dump */
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#define ADSP_A_WDT_EXCCAUSE_REG (ADSP_BASE + 0x017C)
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/*latency monitor*/
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#define ADSP_LATMON_DVFS_MODE (ADSP_BASE + 0x0100)
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#define ADSP_LATMON_CON1 (ADSP_BASE + 0x0104)
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#define ADSP_LATMON_CON2 (ADSP_BASE + 0x0108)
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#define ADSP_LATMON_MARGIN (ADSP_BASE + 0x010C)
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#define ADSP_LATMON_THRESHOLD (ADSP_BASE + 0x0110)
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#define ADSP_LATMON_STATE (ADSP_BASE + 0x0114)
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#define ADSP_LATMON_ACCCNT (ADSP_BASE + 0x0118)
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/* latency threshold & budget for 0.8V. 0.7V. 0.625V */
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#define ADSP_LATMON_CONT0 (ADSP_BASE + 0x012C)
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#define ADSP_LATMON_CONT1 (ADSP_BASE + 0x0130)
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#define ADSP_LATMON_CONT2 (ADSP_BASE + 0x0134)
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#define ADSP_A_DEBUG_PC_REG (ADSP_BASE + 0x013C)
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#define ADSP_DBG_PEND_CNT (ADSP_BASE + 0x015C)
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#define ADSP_SLEEP_STATUS_REG (ADSP_BASE + 0x0158)
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#define ADSP_BUS_MON_BASE (ADSP_BASE + 0x5000)
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/* adsp power state*/
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#define ADSP_A_IS_RESET (0x00)
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#define ADSP_A_IS_ACTIVE (0x10)
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/* adsp current state */
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#define ADSP_A_CUR_RESET (0x0)
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#define ADSP_A_CUR_STALL (0x1)
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#define ADSP_A_CUR_ACTIVE (0x3)
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#define ADSP_A_CUR_WFI (0x4)
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#define ADSP_A_CUR_WAKEUP (0x5) //Wakeup state (Receive irq)
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#define ADSP_A_IS_WFI (1 << 0)
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#define ADSP_B_IS_WFI (1 << 1)
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#define ADSP_AXI_BUS_IS_IDLE (1 << 2)
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/* clk reg */
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#define ADSP_CLK_CTRL_BASE (ADSP_BASE + 0x1000)
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#define ADSP_CLK_UART_EN (1 << 5)
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#define ADSP_CLK_DMA_EN (1 << 4)
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#define ADSP_CLK_TIMER_EN (1 << 3)
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#define ADSP_CLK_CORE_1_EN (1 << 1)
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#define ADSP_CLK_CORE_0_EN (1 << 0)
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#define ADSP_UART_CTRL (ADSP_BASE + 0x1010)
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#define ADSP_UART_RST_N (1 << 3)
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#define ADSP_UART_CLK_SEL (1 << 1)
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#define ADSP_UART_BCLK_CG (1 << 0)
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#endif
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