122 lines
2.6 KiB
C
122 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <emi_mpu.h>
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#include <linux/bits.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ratelimit.h>
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static bool axi_id_is_gpu(unsigned int axi_id)
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{
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unsigned int port;
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unsigned int id;
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unsigned int i;
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port = axi_id & (BIT_MASK(3) - 1);
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id = axi_id >> 3;
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for (i = 0; i < global_emi_mpu->bypass_axi_num; i++) {
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/* master is MFG_MPU(GPU MPU) */
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if (port == global_emi_mpu->bypass_axi[i].port
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&& ((id & global_emi_mpu->bypass_axi[i].axi_mask)
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== global_emi_mpu->bypass_axi[i].axi_value))
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return true;
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}
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return false;
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}
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int bypass_info(unsigned int offset)
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{
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unsigned int i;
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for (i = 0; i < global_emi_mpu->bypass_miu_reg_num; i++) {
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if (offset == global_emi_mpu->bypass_miu_reg[i])
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return i;
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}
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return -1;
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}
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static irqreturn_t emi_mpu_isr_hook(unsigned int emi_id,
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struct reg_info_t *dump,
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unsigned int leng)
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{
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int i;
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unsigned int srinfo_r = 0, axi_id_r = 0;
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unsigned int srinfo_w = 0, axi_id_w = 0;
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bool bypass;
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static DEFINE_RATELIMIT_STATE(ratelimit, 1 * HZ, 3);
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for (i = 0; i < leng; i++) {
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switch (bypass_info(dump[i].offset)) {
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case WRITE_SRINFO:
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srinfo_w = dump[i].value;
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break;
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case READ_SRINFO:
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srinfo_r = dump[i].value;
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break;
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case WRITE_AXI:
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if (srinfo_w == 3)
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axi_id_w |= (dump[i].value & (BIT_MASK(20) - 1));
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break;
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case READ_AXI:
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if (srinfo_r == 3)
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axi_id_r |= (dump[i].value & (BIT_MASK(20) - 1));
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break;
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case WRITE_AXI_MSB:
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if (srinfo_w == 3) {
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axi_id_w &= (BIT_MASK(16) - 1);
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axi_id_w |=
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((dump[i].value & (BIT_MASK(4) - 1)) << 16);
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}
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break;
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case READ_AXI_MSB:
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if (srinfo_r == 3) {
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axi_id_r &= (BIT_MASK(16) - 1);
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axi_id_r |=
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((dump[i].value & (BIT_MASK(4) - 1)) << 16);
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}
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break;
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default:
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break;
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}
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}
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if (srinfo_r == 3 && !axi_id_is_gpu(axi_id_r))
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bypass = true;
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else if (srinfo_w == 3 && !axi_id_is_gpu(axi_id_w))
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bypass = true;
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else
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bypass = false;
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if (bypass == true) {
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if (__ratelimit(&ratelimit)) {
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pr_info("srinfo_r %d, axi_id_r 0x%x\n",
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srinfo_r, axi_id_r);
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pr_info("srinfo_w %d, axi_id_w 0x%x\n",
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srinfo_w, axi_id_w);
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}
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}
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return (bypass) ? IRQ_HANDLED : IRQ_NONE;
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}
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static __init int emi_mpu_mt6983_init(void)
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{
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int ret;
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pr_info("emi_mpu_mt6983 was loaded\n");
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ret = mtk_emimpu_isr_hook_register(emi_mpu_isr_hook);
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if (ret)
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pr_err("Failed to register the EMI MPU ISR hook function\n");
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return 0;
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}
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module_init(emi_mpu_mt6983_init);
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MODULE_DESCRIPTION("MediaTek EMI MPU MT6983 Driver");
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MODULE_LICENSE("GPL v2");
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