352 lines
8.2 KiB
C
352 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: PC Chen <pc.chen@mediatek.com>
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*/
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#ifndef _VCODEC_IPI_MSG_H_
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#define _VCODEC_IPI_MSG_H_
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#include <linux/videodev2.h>
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#include <linux/v4l2-controls.h>
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#ifdef VIDEO_MAX_FRAME
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#undef VIDEO_MAX_FRAME
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#define VIDEO_MAX_FRAME 64
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#endif
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#define AP_IPIMSG_VDEC_SEND_BASE 0xA000
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#define VCU_IPIMSG_VDEC_ACK_BASE 0xB000
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#define VCU_IPIMSG_VDEC_SEND_BASE 0xC000
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#define AP_IPIMSG_VDEC_ACK_BASE 0xD000
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#define AP_IPIMSG_VENC_SEND_BASE 0x1000
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#define VCU_IPIMSG_VENC_ACK_BASE 0x2000
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#define VCU_IPIMSG_VENC_SEND_BASE 0x3000
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#define AP_IPIMSG_VENC_ACK_BASE 0x4000
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#define VDEC_TF_INFO_OFFSET 0x70000
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#define VENC_TF_INFO_OFFSET 0x7F00
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enum mtk_venc_hw_id {
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MTK_VENC_CORE_0 = 0,
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MTK_VENC_CORE_1 = 1,
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MTK_VENC_CORE_2 = 2,
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MTK_VENC_HW_NUM = 3,
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};
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enum mtk_vdec_hw_id {
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MTK_VDEC_CORE = 0,
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MTK_VDEC_LAT = 1,
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MTK_VDEC_CORE1 = 2,
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MTK_VDEC_LAT1 = 3,
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MTK_VDEC_HW_NUM = 4,
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MTK_VDEC_LINE_COUNT = 4,
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MTK_VDEC_IRQ_NUM = 5,
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};
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enum mtk_fmt_type {
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MTK_FMT_DEC = 0,
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MTK_FMT_ENC = 1,
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MTK_FMT_FRAME = 2,
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};
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enum mtk_frame_type {
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MTK_FRAME_NONE = 0,
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MTK_FRAME_I = 1,
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MTK_FRAME_P = 2,
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MTK_FRAME_B = 3,
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};
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enum v4l2_vdec_trick_mode {
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/* decode all frame */
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V4L2_VDEC_TRICK_MODE_ALL = 0,
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/* decode all except of non-reference frame */
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V4L2_VDEC_TRICK_MODE_IP,
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/* only decode I frame */
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V4L2_VDEC_TRICK_MODE_I
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};
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enum mtk_dec_dtsi_m4u_port_idx {
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VDEC_M4U_PORT_MC,
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VDEC_M4U_PORT_UFO,
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VDEC_M4U_PORT_PP,
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VDEC_M4U_PORT_PRED_RD,
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VDEC_M4U_PORT_PRED_WR,
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VDEC_M4U_PORT_PPWRAP,
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VDEC_M4U_PORT_TILE,
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VDEC_M4U_PORT_VLD,
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VDEC_M4U_PORT_VLD2,
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VDEC_M4U_PORT_AVC_MV,
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VDEC_M4U_PORT_RG_CTRL_DMA,
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VDEC_M4U_PORT_UFO_ENC,
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VDEC_M4U_PORT_LAT0_VLD,
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VDEC_M4U_PORT_LAT0_VLD2,
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VDEC_M4U_PORT_LAT0_AVC_MV,
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VDEC_M4U_PORT_LAT0_PRED_RD,
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VDEC_M4U_PORT_LAT0_TILE,
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VDEC_M4U_PORT_LAT0_WDMA,
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VDEC_M4U_PORT_LAT0_RG_CTRL_DMA,
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VDEC_M4U_PORT_LAT0_MC,
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VDEC_M4U_PORT_LAT0_UFO,
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VDEC_M4U_PORT_LAT0_UFO_C,
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VDEC_M4U_PORT_VIDEO_UP_SEC,
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VDEC_M4U_PORT_VIDEO_UP_NOR,
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VDEC_M4U_PORT_UP_1,
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VDEC_M4U_PORT_UP_2,
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VDEC_M4U_PORT_UP_3,
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VDEC_M4U_PORT_UP_4,
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NUM_MAX_VDEC_M4U_PORT
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};
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/**
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* struct mtk_video_fmt - Structure used to store information about pixelformats
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*/
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struct mtk_video_fmt {
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__u32 fourcc;
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__u32 type; /* enum mtk_fmt_type */
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__u32 num_planes;
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__u32 reserved;
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};
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/**
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* struct mtk_codec_framesizes - Structure used to store information about
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* framesizes
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*/
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struct mtk_codec_framesizes {
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__u32 fourcc;
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__u32 profile;
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__u32 level;
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__u32 reserved;
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struct v4l2_frmsize_stepwise stepwise;
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};
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struct mtk_tf_info {
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__u32 hw_id;
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__u32 port;
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__u64 tf_mva;
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__u32 has_tf;
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};
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/**
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* struct mtk_video_frame_frameintervals - Structure used to store information about
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* frameintervals
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* fourcc/width/height are input parameters
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* stepwise is output parameter
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*/
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struct mtk_video_frame_frameintervals {
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__u32 fourcc;
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__u32 width;
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__u32 height;
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struct v4l2_frmival_stepwise stepwise;
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};
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struct mtk_color_desc {
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__u32 color_primaries;
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__u32 transform_character;
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__u32 matrix_coeffs;
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__u32 display_primaries_x[3];
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__u32 display_primaries_y[3];
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__u32 white_point_x;
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__u32 white_point_y;
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__u32 max_display_mastering_luminance;
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__u32 min_display_mastering_luminance;
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__u32 max_content_light_level;
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__u32 max_pic_light_level;
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__u32 is_hdr;
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__u32 full_range;
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__u32 reserved;
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};
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struct v4l2_vdec_hdr10_info {
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__u8 matrix_coefficients;
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__u8 bits_per_channel;
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__u8 chroma_subsampling_horz;
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__u8 chroma_subsampling_vert;
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__u8 cb_subsampling_horz;
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__u8 cb_subsampling_vert;
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__u8 chroma_siting_horz;
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__u8 chroma_siting_vert;
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__u8 color_range;
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__u8 transfer_characteristics;
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__u8 colour_primaries;
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__u16 max_CLL; // CLL: Content Light Level
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__u16 max_FALL; // FALL: Frame Average Light Level
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__u16 primaries[3][2];
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__u16 white_point[2];
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__u32 max_luminance;
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__u32 min_luminance;
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};
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struct v4l2_vdec_hdr10plus_data {
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__u64 addr; // user pointer
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__u32 size;
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};
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struct mtk_venc_multi_ref {
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__u32 multi_ref_en;
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__u32 intra_period;
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__u32 superp_period;
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__u32 superp_ref_type;
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__u32 ref0_distance;
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__u32 ref1_dsitance;
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__u32 max_distance;
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__u32 reserved;
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};
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struct mtk_venc_vui_info {
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__u32 aspect_ratio_idc;
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__u32 sar_width;
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__u32 sar_height;
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__u32 reserved;
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};
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struct mtk_hdr_dynamic_info {
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__u32 max_sc_lR;
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// u(17); Max R Nits *10; in the range of 0x00000-0x186A0
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__u32 max_sc_lG;
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// u(17); Max G Nits *10; in the range of 0x00000-0x186A0
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__u32 max_sc_lB;
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// u(17); Max B Nits *10; in the range of 0x00000-0x186A0
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__u32 avg_max_rgb;
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// u(17); Average maxRGB Nits *10; in 0x00000-0x186A0
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__u32 distribution_values[9];
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/* u(17)
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* 0=1% percentile maxRGB Nits *10
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* 1=Maximum Nits of 99YF *10
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* 2=Average Nits of DPY100F
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* 3=25% percentile maxRGB Nits *10
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* 4=50% percentile maxRGB Nits *10
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* 5=75% percentile maxRGB Nits *10
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* 6=90% percentile maxRGB Nits *10
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* 7=95% percentile maxRGB Nits *10
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* 8=99.95% percentile maxRGB Nits *10
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*/
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__u32 reserved;
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};
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struct dynamicinfo_change_flag {
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__u32 fgBitrate;
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__u32 fgFrameQp;
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__u32 fgSliceHeaderSpacing;
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__u32 fgForceI;
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__u32 fgBaseLayerPid;
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__u32 fgMarkLTR;
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__u32 fgUseLTR;
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__u32 fgTemporalLayerCount;
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};
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struct temporal_layer_count {
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__u32 nPLayerCountActual;
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__u32 nBLayerCountActual;
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};
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struct inputqueue_dynamic_info {
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struct dynamicinfo_change_flag changed;
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__u64 nTimeStamp;
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__u32 nBitrate;
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__u32 nFrameQp;
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__u32 bSliceHeaderSpacing;
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__u32 bForceI;
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__u32 nBaseLayerPid;
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__u32 nMarkLTR;
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__u32 nUseLTR;
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__u32 reserved;
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struct temporal_layer_count sTemporalLayerCount;
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};
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/**
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* struct vdec_pic_info - picture size information
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* @pic_w: picture width
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* @pic_h: picture height
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* @buf_w : picture buffer width (codec aligned up from pic_w)
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* @buf_h : picture buffer heiht (codec aligned up from pic_h)
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* @fb_sz: frame buffer size
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* @bitdepth: Sequence bitdepth
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* @layout_mode: mediatek frame layout mode
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* @fourcc: frame buffer color format
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* @field: enum v4l2_field, field type of this sequence
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* E.g. suppose picture size is 176x144,
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* buffer size will be aligned to 176x160.
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*/
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struct vdec_pic_info {
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__u32 pic_w;
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__u32 pic_h;
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__u32 buf_w;
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__u32 buf_h;
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__u32 fb_sz[VIDEO_MAX_PLANES];
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__u32 bitdepth;
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__u32 layout_mode;
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__u32 fourcc;
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__u32 field;
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};
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/**
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* struct vdec_dec_info - decode information
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* @dpb_sz : decoding picture buffer size
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* @vdec_changed_info : some changed flags
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* @bs_dma : Input bit-stream buffer dma address
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* @bs_fd : Input bit-stream buffer dmabuf fd
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* @fb_dma : Y frame buffer dma address
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* @fb_fd : Y frame buffer dmabuf fd
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* @vdec_bs_va : VDEC bitstream buffer struct virtual address
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* @vdec_fb_va : VDEC frame buffer struct virtual address
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* @fb_num_planes : frame buffer plane count
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* @reserved : reserved variable for 64bit align
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*/
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struct vdec_dec_info {
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__u32 dpb_sz;
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__u32 vdec_changed_info;
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__u64 bs_dma;
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__u64 bs_fd;
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__u64 fb_dma[VIDEO_MAX_PLANES];
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__u64 fb_fd[VIDEO_MAX_PLANES];
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__u64 vdec_bs_va;
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__u64 vdec_fb_va;
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__u32 fb_num_planes;
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__u32 index;
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__u32 wait_key_frame;
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__u32 error_map;
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__u64 timestamp;
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__u32 queued_frame_buf_count;
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__u32 vpeek;
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};
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#define HDR10_PLUS_MAX_SIZE (128)
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struct hdr10plus_info {
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__u8 data[HDR10_PLUS_MAX_SIZE];
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__u32 size;
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};
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enum vcodec_mem_type {
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MEM_TYPE_FOR_SW = 0, /* /< External memory for SW */
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MEM_TYPE_FOR_HW, /* /< External memory for HW */
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MEM_TYPE_FOR_UBE_HW, /* /< External memory for UBE reserved memory */
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MEM_TYPE_FOR_SEC_SW, /* /< External memory for secure SW */
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MEM_TYPE_FOR_SEC_HW, /* /< External memory for secure HW */
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MEM_TYPE_FOR_SEC_UBE_HW, /* /< External memory for secure UBE */
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MEM_TYPE_FOR_SHM, /* /< External memory for share memory */
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MEM_TYPE_FOR_SEC_WFD_HW, /* /< External memory for secure WFD */
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MEM_TYPE_MAX = 0xFFFFFFFF /* /< Max memory type */
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};
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/**
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* struct mem_obj - memory buffer allocated in kernel
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*
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* @flag: flag of buffer
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* @iova: iova of buffer
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* @len: buffer length
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* @pa: physical address
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* @va: kernel virtual address
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*/
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struct vcodec_mem_obj {
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__u32 type;
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__u32 len;
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__u64 iova;
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__u64 pa;
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__u64 va;
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};
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#endif
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