626 lines
17 KiB
C
626 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Tiffany Lin <tiffany.lin@mediatek.com>
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*/
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#include <linux/errno.h>
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#include <linux/wait.h>
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#include <linux/module.h>
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#include "mtk_vcodec_intr.h"
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#include "mtk_vcodec_util.h"
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int g_dec_irq[MTK_VDEC_IRQ_NUM] = { 0 };
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enum mtk_vdec_hw_id mtk_vdec_map_irq_to_hwid(int irq)
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{
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enum mtk_vdec_hw_id core_id = MTK_VDEC_IRQ_NUM;
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if (irq == g_dec_irq[MTK_VDEC_CORE])
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core_id = MTK_VDEC_CORE;
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else if (irq == g_dec_irq[MTK_VDEC_CORE1])
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core_id = MTK_VDEC_CORE1;
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else if (irq == g_dec_irq[MTK_VDEC_LAT])
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core_id = MTK_VDEC_LAT;
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else if (irq == g_dec_irq[MTK_VDEC_LAT1])
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core_id = MTK_VDEC_LAT1;
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else if (irq == g_dec_irq[MTK_VDEC_LINE_COUNT])
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core_id = MTK_VDEC_LINE_COUNT;
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return core_id;
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}
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int mtk_vcodec_wait_for_done_ctx(struct mtk_vcodec_ctx *ctx,
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int core_id, int command, unsigned int timeout_ms)
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{
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int status = 0;
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#ifndef FPGA_INTERRUPT_API_DISABLE
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wait_queue_head_t *waitqueue;
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long timeout_jiff, ret;
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if (ctx == NULL) {
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mtk_v4l2_err("ctx is NULL! (core_id %d, command 0x%x)", core_id, command);
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return -1;
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}
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if (core_id >= MTK_VDEC_IRQ_NUM || core_id < 0) {
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mtk_v4l2_err("ctx %d, invalid core_id=%d", ctx->id, core_id);
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return -1;
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}
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waitqueue = (wait_queue_head_t *)&ctx->queue[core_id];
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timeout_jiff = msecs_to_jiffies(timeout_ms);
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ret = wait_event_interruptible_timeout(*waitqueue,
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ctx->int_cond[core_id],
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timeout_jiff);
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if (!ret) {
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status = -1; /* timeout */
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mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, core_id %d timeout time=%ums out %d %d!",
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ctx->id, command, ctx->type, core_id, timeout_ms,
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ctx->int_cond[core_id], ctx->int_type);
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if (ctx->type == MTK_INST_ENCODER)
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mtk_vcodec_enc_timeout_dump(ctx);
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} else if (-ERESTARTSYS == ret) {
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mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, core_id %d timeout interrupted by a signal %d %d",
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ctx->id, ctx->type, core_id,
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command, ctx->int_cond[core_id],
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ctx->int_type);
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status = -2;
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}
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ctx->int_cond[core_id] = 0;
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ctx->int_type = 0;
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#endif
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return status;
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}
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EXPORT_SYMBOL_GPL(mtk_vcodec_wait_for_done_ctx);
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/* Wake up context wait_queue */
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void wake_up_dec_ctx(struct mtk_vcodec_ctx *ctx, int core_id)
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{
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ctx->int_cond[core_id] = 1;
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wake_up_interruptible(&ctx->queue[core_id]);
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}
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irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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u32 cg_status = 0;
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unsigned int dec_done_status = 0;
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enum mtk_vdec_hw_id core_id;
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enum mtk_dec_dtsi_reg_idx misc_index;
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void __iomem *vdec_misc_addr;
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core_id = mtk_vdec_map_irq_to_hwid(irq);
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if (!((core_id == MTK_VDEC_CORE) || (core_id == MTK_VDEC_CORE1))) {
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mtk_v4l2_err("DEC ISR, core_id(%d) is not right", core_id);
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return IRQ_HANDLED;
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}
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ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE);
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if (ctx == NULL)
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return IRQ_HANDLED;
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misc_index = ((core_id == MTK_VDEC_CORE) ? VDEC_MISC : VDEC_CORE1_MISC);
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vdec_misc_addr = dev->dec_reg_base[misc_index] +
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MTK_VDEC_IRQ_CFG_REG;
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if (ctx->dec_params.svp_mode != OPEN_TEE) {
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/* check if HW active or not */
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cg_status = readl(dev->dec_reg_base[0]);
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if ((cg_status & MTK_VDEC_HW_ACTIVE) != 0) {
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mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)",
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cg_status);
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return IRQ_HANDLED;
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}
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dec_done_status = readl(vdec_misc_addr);
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ctx->irq_status = dec_done_status;
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if ((dec_done_status & MTK_VDEC_IRQ_STATUS_DEC_SUCCESS) !=
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MTK_VDEC_IRQ_STATUS_DEC_SUCCESS)
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return IRQ_HANDLED;
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//rdma crc not to handle
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if ((readl(dev->dec_reg_base[misc_index] + 103 * 4) & 0x10) == 0x10)
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return IRQ_HANDLED;
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/* clear interrupt */
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if ((core_id == MTK_VDEC_CORE) &&
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((readl(dev->dec_reg_base[VDEC_BASE] +
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RW_MCORE_EnableDecode) & 0x01) == 1)) { /*mcore_top base*/
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//clear multi core interrupt
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/*set 1 to clear interrupt*/
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writel((readl(dev->dec_reg_base[VDEC_SOC_GCON] + 9 * 4) | 0x10000),
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(dev->dec_reg_base[VDEC_SOC_GCON] + 9 * 4));
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/*set 0 to clear status*/
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writel((readl(dev->dec_reg_base[VDEC_SOC_GCON] + 9 * 4) & ~0x10000),
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(dev->dec_reg_base[VDEC_SOC_GCON] + 9 * 4));
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} else {
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writel((readl(vdec_misc_addr) | MTK_VDEC_IRQ_CFG),
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vdec_misc_addr);
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writel((readl(vdec_misc_addr) & ~MTK_VDEC_IRQ_CLR),
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vdec_misc_addr);
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}
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}
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wake_up_dec_ctx(ctx, core_id);
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mtk_v4l2_debug(4,
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"%s :wake up ctx %d, dec_done_status=%x",
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__func__, ctx->id, dec_done_status);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(mtk_vcodec_dec_irq_handler);
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irqreturn_t mtk_vcodec_lat_dec_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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u32 cg_status = 0;
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unsigned int dec_done_status = 0;
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enum mtk_vdec_hw_id core_id;
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enum mtk_dec_dtsi_reg_idx misc_index;
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void __iomem *vdec_misc_addr;
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core_id = mtk_vdec_map_irq_to_hwid(irq);
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if (!((core_id == MTK_VDEC_LAT) || (core_id == MTK_VDEC_LAT1))) {
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mtk_v4l2_err("LAT ISR, core_id(%d) is not right", core_id);
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return IRQ_HANDLED;
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}
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ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_LAT);
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if (ctx == NULL)
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return IRQ_HANDLED;
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misc_index = ((core_id == MTK_VDEC_LAT) ?
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VDEC_LAT_MISC : VDEC_LAT1_MISC);
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vdec_misc_addr = dev->dec_reg_base[misc_index] +
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MTK_VDEC_IRQ_CFG_REG;
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if (ctx->dec_params.svp_mode != OPEN_TEE) {
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/* check if HW active or not */
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cg_status = readl(dev->dec_reg_base[0]);
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if ((cg_status & MTK_VDEC_HW_ACTIVE) != 0) {
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mtk_v4l2_err("DEC LAT ISR, VDEC active is not 0x0 (0x%08x)",
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cg_status);
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return IRQ_HANDLED;
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}
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dec_done_status = readl(vdec_misc_addr);
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ctx->irq_status = dec_done_status;
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if ((dec_done_status & MTK_VDEC_IRQ_STATUS_DEC_SUCCESS) !=
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MTK_VDEC_IRQ_STATUS_DEC_SUCCESS)
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return IRQ_HANDLED;
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/* clear interrupt */
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if ((core_id == MTK_VDEC_LAT) &&
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(dev->dec_reg_base[VDEC_LAT_TOP] != NULL) &&
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((readl(dev->dec_reg_base[VDEC_LAT_TOP] + 75 * 4) & 0x01)
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== 1)) { //multi lat clear interrupt
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if (((readl(dev->dec_reg_base[VDEC_LAT_WDMA] + 9 * 4) &
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0x01) == 0) ||
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((readl(dev->dec_reg_base[VDEC_LAT1_WDMA] + 9 * 4) &
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0x01) == 0)) {
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writel((readl(dev->dec_reg_base[VDEC_LAT_WDMA] + 9 * 4)
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| (1 << 24)),
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dev->dec_reg_base[VDEC_SOC_GCON] + 9 * 4);
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} else {
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if (readl(dev->dec_reg_base[VDEC_LAT_WDMA] + 9 * 4) &
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0x01) {
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writel((readl(dev->dec_reg_base[VDEC_LAT_MISC] +
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MTK_VDEC_IRQ_CFG_REG) |
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MTK_VDEC_IRQ_CFG),
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dev->dec_reg_base[VDEC_LAT_MISC] +
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MTK_VDEC_IRQ_CFG_REG);
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writel((readl(dev->dec_reg_base[VDEC_LAT_MISC] +
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MTK_VDEC_IRQ_CFG_REG) &
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~MTK_VDEC_IRQ_CLR),
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dev->dec_reg_base[VDEC_LAT_MISC] +
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MTK_VDEC_IRQ_CFG_REG);
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}
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if (readl(dev->dec_reg_base[VDEC_LAT1_WDMA] + 9 * 4) &
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0x01) {
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writel((readl(dev->dec_reg_base[VDEC_LAT1_MISC]
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+ MTK_VDEC_IRQ_CFG_REG) |
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MTK_VDEC_IRQ_CFG),
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dev->dec_reg_base[VDEC_LAT1_MISC] +
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MTK_VDEC_IRQ_CFG_REG);
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writel((readl(dev->dec_reg_base[VDEC_LAT1_MISC]
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+ MTK_VDEC_IRQ_CFG_REG)
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& ~MTK_VDEC_IRQ_CLR),
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dev->dec_reg_base[VDEC_LAT1_MISC] +
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MTK_VDEC_IRQ_CFG_REG);
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}
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}
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} else {
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writel((readl(vdec_misc_addr) | MTK_VDEC_IRQ_CFG),
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vdec_misc_addr);
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writel((readl(vdec_misc_addr) & ~MTK_VDEC_IRQ_CLR),
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vdec_misc_addr);
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}
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}
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wake_up_dec_ctx(ctx, core_id);
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mtk_v4l2_debug(4,
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"%s :wake up ctx %d, dec_done_status=%x",
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__func__, ctx->id, dec_done_status);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(mtk_vcodec_lat_dec_irq_handler);
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irqreturn_t mtk_vcodec_line_count_irq_handler(int irq,
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void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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unsigned int dec_done_status = 0;
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enum mtk_vdec_hw_id core_id;
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core_id = mtk_vdec_map_irq_to_hwid(irq);
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if (!(core_id == MTK_VDEC_LINE_COUNT)) {
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mtk_v4l2_err("LINE_COUNT ISR, core_id(%d) is not right",
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core_id);
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return IRQ_HANDLED;
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}
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ctx = mtk_vcodec_get_curr_ctx(dev, core_id);
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if (ctx == NULL)
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return IRQ_HANDLED;
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if (ctx->dec_params.svp_mode != OPEN_TEE) {
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dec_done_status = readl(dev->dec_reg_base[VDEC_UFO_ENC] + 122 * 4);
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ctx->irq_status = dec_done_status;
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if ((dec_done_status & (1 << 16)) != (1 << 16)) {
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mtk_v4l2_err("DEC line_count ISR, VDEC active is not 1 (0x%08x)",
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dec_done_status);
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return IRQ_HANDLED;
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}
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/* clear interrupt */
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writel((readl(dev->dec_reg_base[VDEC_UFO_ENC] + 122 * 4) | 0x1),
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dev->dec_reg_base[VDEC_UFO_ENC] + 122 * 4);
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writel((readl(dev->dec_reg_base[VDEC_UFO_ENC] + 122 * 4) & ~0x1),
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dev->dec_reg_base[VDEC_UFO_ENC] + 122 * 4);
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}
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wake_up_dec_ctx(ctx, core_id);
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mtk_v4l2_debug(4,
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"%s :wake up ctx %d, dec_done_status=%x",
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__func__, ctx->id, dec_done_status);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(mtk_vcodec_line_count_irq_handler);
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void clean_irq_status(unsigned int irq_status, void __iomem *addr)
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{
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if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE)
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writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH)
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writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_DRAM)
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writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_SPS)
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writel(MTK_VENC_IRQ_STATUS_SPS, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_PPS)
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writel(MTK_VENC_IRQ_STATUS_PPS, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_FRM)
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writel(MTK_VENC_IRQ_STATUS_FRM, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_VPS)
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writel(MTK_VENC_IRQ_STATUS_VPS, addr);
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}
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/* Wake up context wait_queue */
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void wake_up_enc_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason, int core_id)
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{
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ctx->int_cond[core_id] = 1;
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ctx->int_type = reason;
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wake_up_interruptible(&ctx->queue[core_id]);
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}
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irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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unsigned long flags;
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void __iomem *addr;
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if (!dev) {
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mtk_v4l2_err("dev null invalid");
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return IRQ_NONE;
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}
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spin_lock_irqsave(&dev->irqlock, flags);
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ctx = dev->curr_enc_ctx[0];
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spin_unlock_irqrestore(&dev->irqlock, flags);
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if (ctx == NULL)
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return IRQ_HANDLED;
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mtk_v4l2_debug(1, "id=%d", ctx->id);
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addr = dev->enc_reg_base[VENC_SYS] + MTK_VENC_IRQ_ACK_OFFSET;
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ctx->irq_status = readl(dev->enc_reg_base[VENC_SYS] +
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(MTK_VENC_IRQ_STATUS_OFFSET));
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clean_irq_status(ctx->irq_status, addr);
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wake_up_enc_ctx(ctx, MTK_INST_IRQ_RECEIVED, 0);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(mtk_vcodec_enc_irq_handler);
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irqreturn_t mtk_vcodec_c1_enc_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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unsigned long flags;
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void __iomem *addr;
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if (!dev) {
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mtk_v4l2_err("dev null invalid");
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return IRQ_NONE;
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}
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spin_lock_irqsave(&dev->irqlock, flags);
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ctx = dev->curr_enc_ctx[1];
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spin_unlock_irqrestore(&dev->irqlock, flags);
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if (ctx == NULL)
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return IRQ_HANDLED;
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mtk_v4l2_debug(1, "id=%d", ctx->id);
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addr = dev->enc_reg_base[VENC_C1_SYS] + MTK_VENC_IRQ_ACK_OFFSET;
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ctx->irq_status = readl(dev->enc_reg_base[VENC_C1_SYS] +
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(MTK_VENC_IRQ_STATUS_OFFSET));
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clean_irq_status(ctx->irq_status, addr);
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wake_up_enc_ctx(ctx, MTK_INST_IRQ_RECEIVED, 1);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(mtk_vcodec_c1_enc_irq_handler);
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int mtk_vcodec_dec_irq_setup(struct platform_device *pdev,
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struct mtk_vcodec_dev *dev)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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int i = 0;
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int ret = 0;
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if (!pdev || !dev) {
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mtk_v4l2_err("pdev %p dev %p invalid", pdev, dev);
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return -1;
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}
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for (i = 0; i < MTK_VDEC_IRQ_NUM; i++) {
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dev->dec_irq[i] = platform_get_irq(pdev, i);
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g_dec_irq[i] = dev->dec_irq[i];
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if ((i == MTK_VDEC_CORE) || (i == MTK_VDEC_CORE1))
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ret = devm_request_irq(&pdev->dev, dev->dec_irq[i],
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mtk_vcodec_dec_irq_handler, IRQF_TRIGGER_HIGH | IRQF_SHARED,
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pdev->name, dev);
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else if ((i == MTK_VDEC_LAT) || (i == MTK_VDEC_LAT1))
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ret = devm_request_irq(&pdev->dev, dev->dec_irq[i],
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mtk_vcodec_lat_dec_irq_handler, IRQF_TRIGGER_HIGH | IRQF_SHARED,
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pdev->name, dev);
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else if (i == MTK_VDEC_LINE_COUNT)
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ret = devm_request_irq(&pdev->dev, dev->dec_irq[i],
|
|
mtk_vcodec_line_count_irq_handler, IRQF_TRIGGER_HIGH | IRQF_SHARED,
|
|
pdev->name, dev);
|
|
if (ret) {
|
|
mtk_v4l2_debug(1, "Failed to install dev->dec_irq[%d] %d (%d)",
|
|
i, dev->dec_irq[i],
|
|
ret);
|
|
}
|
|
disable_irq(dev->dec_irq[i]);
|
|
}
|
|
#endif
|
|
return 0;
|
|
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_vcodec_dec_irq_setup);
|
|
|
|
|
|
int mtk_vcodec_enc_irq_setup(struct platform_device *pdev,
|
|
struct mtk_vcodec_dev *dev)
|
|
{
|
|
#ifndef FPGA_INTERRUPT_API_DISABLE
|
|
int i = 0;
|
|
int ret = 0;
|
|
|
|
if (!pdev || !dev) {
|
|
mtk_v4l2_err("pdev %p dev %p invalid", pdev, dev);
|
|
return -1;
|
|
}
|
|
|
|
for (i = 0; i < MTK_VENC_HW_NUM; i++) {
|
|
dev->enc_irq[i] = platform_get_irq(pdev, i);
|
|
if (dev->enc_irq[i] < 0) {
|
|
pr_info("no IRQ resource, hw id: %d", i);
|
|
break;
|
|
}
|
|
|
|
pr_info("get IRQ resource, hw id: %d irq %d", i, dev->enc_irq[i]);
|
|
|
|
if (i == MTK_VENC_CORE_0)
|
|
ret = devm_request_irq(&pdev->dev, dev->enc_irq[i],
|
|
mtk_vcodec_enc_irq_handler,
|
|
0, pdev->name, dev);
|
|
else if (i == MTK_VENC_CORE_1)
|
|
ret = devm_request_irq(&pdev->dev, dev->enc_irq[i],
|
|
mtk_vcodec_c1_enc_irq_handler,
|
|
0, pdev->name, dev);
|
|
|
|
if (ret) {
|
|
mtk_v4l2_debug(1, "Failed to install dev->enc_irq %d (%d)",
|
|
dev->enc_irq[i],
|
|
ret);
|
|
return -1;
|
|
}
|
|
disable_irq(dev->enc_irq[i]);
|
|
}
|
|
#endif
|
|
return 0;
|
|
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_vcodec_enc_irq_setup);
|
|
|
|
|
|
void mtk_vcodec_gce_timeout_dump(void *ctx)
|
|
{
|
|
struct mtk_vcodec_ctx *curr_ctx = ctx;
|
|
|
|
if (!ctx) {
|
|
mtk_v4l2_err("ctx null invalid");
|
|
return;
|
|
}
|
|
|
|
if (curr_ctx->type == MTK_INST_ENCODER)
|
|
mtk_vcodec_enc_timeout_dump(ctx);
|
|
else if (curr_ctx->type == MTK_INST_DECODER)
|
|
mtk_vcodec_dec_timeout_dump(ctx);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_vcodec_gce_timeout_dump);
|
|
|
|
void mtk_vcodec_enc_timeout_dump(void *ctx)
|
|
{
|
|
unsigned long value;
|
|
int i = 0, j = 0;
|
|
|
|
struct mtk_vcodec_ctx *curr_ctx = ctx;
|
|
struct mtk_vcodec_dev *dev = NULL;
|
|
|
|
#define REG1_COUNT 13
|
|
#define REG2_COUNT 46
|
|
|
|
unsigned int Reg_1[REG1_COUNT] = {
|
|
0x14, 0xEC, 0x1C0, 0x1168, 0x11C0,
|
|
0x11C4, 0xF4, 0x5C, 0x60, 0x130,
|
|
0x24, 0x114C, 0x1164};
|
|
unsigned int Reg_2[REG2_COUNT] = {
|
|
0xEC, 0x200, 0x204, 0x208, 0x20C,
|
|
0x210, 0x214, 0x218, 0x21C,
|
|
0x220, 0x224, 0x228, 0x22C,
|
|
0x230, 0x234, 0x238, 0x23C,
|
|
0x240, 0x244, 0x248, 0x24C,
|
|
0x250, 0x254, 0x258, 0x25C,
|
|
0x260, 0x264, 0x268, 0x26C,
|
|
0x270, 0x274, 0x278, 0x27C,
|
|
0x280,
|
|
0x22C, 0x230, 0xF4, 0x1168,
|
|
0x11C0, 0x11C4, 0x1030, 0x240,
|
|
0x248, 0x250, 0x130, 0x140};
|
|
|
|
if (ctx == NULL) {
|
|
mtk_v4l2_debug(0, "can't dump venc for NULL ctx");
|
|
return;
|
|
}
|
|
|
|
dev = curr_ctx->dev;
|
|
|
|
mtk_v4l2_debug(0, "ctx: %p, is_codec_suspending: %d",
|
|
ctx, dev->is_codec_suspending);
|
|
|
|
for (j = 0; j < MTK_VENC_CORE_1; j++) {
|
|
for (i = 0; i < REG1_COUNT; i++) {
|
|
value = readl(dev->enc_reg_base[j] + Reg_1[i]);
|
|
mtk_v4l2_debug(0, "[%d] 0x%x = 0x%lx",
|
|
j, Reg_1[i], value);
|
|
}
|
|
}
|
|
|
|
writel(1, dev->enc_reg_base[0] + 0xEC);
|
|
writel(0, dev->enc_reg_base[0] + 0xF4);
|
|
|
|
for (j = 0; j < MTK_VENC_CORE_1; j++) {
|
|
for (i = 0; i < REG2_COUNT; i++) {
|
|
value = readl(dev->enc_reg_base[j] + Reg_2[i]);
|
|
mtk_v4l2_debug(0, "[%d] 0x%x = 0x%lx",
|
|
j, Reg_2[i], value);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void mtk_vcodec_dec_timeout_dump(void *ctx)
|
|
{
|
|
unsigned long value;
|
|
int i = 0;
|
|
|
|
struct mtk_vcodec_ctx *curr_ctx = ctx;
|
|
struct mtk_vcodec_dev *dev = NULL;
|
|
|
|
#define LAT_REG_COUNT 26
|
|
#define CORE_MISC_REG_COUNT 30
|
|
#define CORE_VLD_REG_COUNT 5
|
|
unsigned int lat_reg[LAT_REG_COUNT] = {
|
|
0x5120, 0x512C, 0x5090, // BITCNT, POS, picture start
|
|
0x50E0, 0x50E4, 0x50E8,
|
|
0x1120, 0x1124, 0x1128, 0x112C, 0x196C, // input, cycle
|
|
0x108, 0x110, 0x114, 0x118, 0x11C, // SMI
|
|
0x120, 0x124, 0x128, 0x12C, 0x130, 0x134, 0x138, 0x13C,
|
|
0x854, 0x878}; // crc, wptr
|
|
unsigned int core_misc_reg[CORE_MISC_REG_COUNT] = {
|
|
0x3120, 0x312C, 0x3090, // BITCNT, POS, picture start
|
|
0x30E0, 0x30E4, 0x30E8, // error
|
|
0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24,
|
|
0xCB, 0xCC, 0x178, // power
|
|
0x108, 0x110, 0x114, 0x118, 0x11C, // SMI
|
|
0x120, 0x124, 0x128, 0x12C, 0x130, 0x134, 0x138, 0x13C};
|
|
unsigned int core_vld_reg[CORE_VLD_REG_COUNT] = {
|
|
0x120, 0x124, 0x128, 0x12C, 0x96C}; // input, cycle
|
|
|
|
if (ctx == NULL) {
|
|
mtk_v4l2_debug(0, "can't dump vdec for NULL ctx");
|
|
return;
|
|
}
|
|
|
|
dev = curr_ctx->dev;
|
|
|
|
mtk_v4l2_debug(0, "ctx: %p, is_codec_suspending: %d",
|
|
ctx, dev->is_codec_suspending);
|
|
|
|
if (dev->vdec_hw_ipm == VCODEC_IPM_V2) {
|
|
for (i = 0; i < LAT_REG_COUNT; i++) {
|
|
value = readl(dev->dec_reg_base[VDEC_LAT_MISC] + lat_reg[i]);
|
|
mtk_v4l2_debug(0, "[LAT][MISC] 0x%x(%d) = 0x%lx",
|
|
lat_reg[i], ((lat_reg[i]&0x0FFF)%0x800)/4, value);
|
|
}
|
|
for (i = 0; i < CORE_MISC_REG_COUNT; i++) {
|
|
value = readl(dev->dec_reg_base[VDEC_MISC] + core_misc_reg[i]);
|
|
mtk_v4l2_debug(0, "[CORE][MISC] 0x%x(%d) = 0x%lx",
|
|
core_misc_reg[i], (core_misc_reg[i] & 0x0FFF)/4, value);
|
|
}
|
|
for (i = 0; i < CORE_VLD_REG_COUNT; i++) {
|
|
value = readl(dev->dec_reg_base[VDEC_VLD] + core_vld_reg[i]);
|
|
mtk_v4l2_debug(0, "[CORE][VLD] 0x%x(%d) = 0x%lx",
|
|
core_vld_reg[i], (core_vld_reg[i] % 0x800)/4, value);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|