886 lines
25 KiB
C
886 lines
25 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: PC Chen <pc.chen@mediatek.com>
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* Tiffany Lin <tiffany.lin@mediatek.com>
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*/
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#ifndef _MTK_VCODEC_DRV_H_
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#define _MTK_VCODEC_DRV_H_
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#include <linux/platform_device.h>
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#include <linux/videodev2.h>
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#include <linux/semaphore.h>
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#include <linux/regulator/consumer.h>
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#include <linux/interconnect-provider.h>
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ioctl.h>
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#include <media/videobuf2-core.h>
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#include "mtk_vcodec_util.h"
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#include "vcodec_ipi_msg.h"
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#include "mtk_vcodec_pm.h"
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#include "mtk_vcodec_dec_pm_plat.h"
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#include "vcodec_dvfs.h"
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#include "vcodec_bw.h"
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#include "mtk_dma_contig.h"
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#include "slbc_ops.h"
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#include "mtk-v4l2-vcodec.h"
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#define ENABLE_FENCE 0
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#define ENABLE_META_BUF 0
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#if ENABLE_FENCE
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#include "mtk_sync.h"
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#endif
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#define MTK_VCODEC_DRV_NAME "mtk_vcodec_drv"
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#define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
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#define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
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#define MTK_VCU_FW_VERSION "0.2.14"
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#define MTK_SLOWMOTION_GCE_TH 120
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#define MTK_VCODEC_MAX_PLANES 3
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#define WAIT_INTR_TIMEOUT_MS 500
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#define SUSPEND_TIMEOUT_CNT 5000
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#define MTK_MAX_CTRLS_HINT 64
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#define V4L2_BUF_FLAG_OUTPUT_NOT_GENERATED 0x02000000
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#define MTK_INVALID_TIMESTAMP ((u64)-1)
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#define MTK_VDEC_ALWAYS_ON_OP_RATE 135
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#define MTK_VCODEC_IPI_THREAD_PRIORITY 1
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#define MTK_VCODEC_MAX_MQ_NODE_CNT 4
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#define MAX_CODEC_FREQ_STEP 10
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#define MTK_VDEC_PORT_NUM 64
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#define MTK_VENC_PORT_NUM 128
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#define MTK_VDEC_LARB_NUM 8
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#define MTK_VENC_LARB_NUM 8
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#define MTK_MAX_METADATA_NUM 8
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#define MAX_GEN_BUF_CNT 32
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#define MAX_META_BUF_CNT 32
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#define DEBUG_GKI 1
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enum mtk_vcodec_ipm {
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VCODEC_IPM_V1 = 1,
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VCODEC_IPM_V2 = 2,
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VCODEC_IPM_MAX,
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};
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/**
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* enum mtk_instance_type - The type of an MTK Vcodec instance.
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*/
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enum mtk_instance_type {
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MTK_INST_DECODER = 0,
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MTK_INST_ENCODER = 1,
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};
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/**
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* enum mtk_mmdvfs_type - The type of an MTK Vcodec MMDVFS.
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*/
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enum mtk_mmdvfs_type {
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MTK_INST_START = 0,
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MTK_INST_UPDATE = 1,
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MTK_INST_RESUME = 2,
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MTK_INST_SET = 3,
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MTK_INST_END = 4,
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};
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/**
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* enum mtk_instance_state - The state of an MTK Vcodec instance.
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* @MTK_STATE_FREE - default state when instance is created
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* @MTK_STATE_INIT - vcodec instance is initialized
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* @MTK_STATE_HEADER - vdec had sps/pps header parsed or venc
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* had sps/pps header encoded
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* @MTK_STATE_FLUSH - vdec is flushing. Only used by decoder
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* @MTK_STATE_STOP - vcodec instance need stop to avoid job ready
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* @MTK_STATE_ABORT - vcodec should be aborted
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*/
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enum mtk_instance_state {
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MTK_STATE_FREE = 0,
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MTK_STATE_INIT = 1,
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MTK_STATE_HEADER = 2,
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MTK_STATE_FLUSH = 3,
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MTK_STATE_STOP = 4,
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MTK_STATE_ABORT = 5,
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};
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enum mtk_codec_type {
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VDEC_VENC_UNKNOWN = 0,
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VDEC_H264,
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VDEC_H265,
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VDEC_HEIF,
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VDEC_VP8,
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VDEC_VP9,
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VDEC_MPEG4,
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VDEC_H263,
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VDEC_MPEG12,
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VDEC_WMV,
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VDEC_RV30,
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VDEC_RV40,
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VDEC_AV1,
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VENC_H264,
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VENC_H265,
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VENC_HEIF,
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VENC_VP8,
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VENC_MPEG4,
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VENC_HYBRID_H264,
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VENC_H263,
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VDEC_VENC_MAX
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};
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/**
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* struct mtk_encode_param - General encoding parameters type
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*/
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enum mtk_encode_param {
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MTK_ENCODE_PARAM_NONE = 0,
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MTK_ENCODE_PARAM_BITRATE = (1 << 0),
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MTK_ENCODE_PARAM_FRAMERATE = (1 << 1),
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MTK_ENCODE_PARAM_INTRA_PERIOD = (1 << 2),
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MTK_ENCODE_PARAM_FORCE_INTRA = (1 << 3),
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MTK_ENCODE_PARAM_GOP_SIZE = (1 << 4),
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MTK_ENCODE_PARAM_SCENARIO = (1 << 5),
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MTK_ENCODE_PARAM_NONREFP = (1 << 6),
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MTK_ENCODE_PARAM_DETECTED_FRAMERATE = (1 << 7),
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MTK_ENCODE_PARAM_RFS_ON = (1 << 8),
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MTK_ENCODE_PARAM_PREPEND_SPSPPS_TO_IDR = (1 << 9),
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MTK_ENCODE_PARAM_OPERATION_RATE = (1 << 10),
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MTK_ENCODE_PARAM_BITRATE_MODE = (1 << 11),
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MTK_ENCODE_PARAM_ROI_ON = (1 << 12),
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MTK_ENCODE_PARAM_GRID_SIZE = (1 << 13),
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MTK_ENCODE_PARAM_COLOR_DESC = (1 << 14),
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MTK_ENCODE_PARAM_SEC_ENCODE = (1 << 15),
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MTK_ENCODE_PARAM_TSVC = (1 << 16),
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MTK_ENCODE_PARAM_NONREFPFREQ = (1 << 17),
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MTK_ENCODE_PARAM_HIGHQUALITY = (1 << 18),
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MTK_ENCODE_PARAM_MAXQP = (1 << 19),
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MTK_ENCODE_PARAM_MINQP = (1 << 20),
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MTK_ENCODE_PARAM_FRAMELVLQP = (1 << 21),
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MTK_ENCODE_PARAM_IP_QPDELTA = (1 << 22),
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MTK_ENCODE_PARAM_QP_CTRL_MODE = (1 << 23),
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MTK_ENCODE_PARAM_DUMMY_NAL = (1 << 24),
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MTK_ENCODE_PARAM_FRAME_LEVEL_QP = (1 << 25)
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};
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/*
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* enum venc_yuv_fmt - The type of input yuv format
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* (VCU related: If you change the order, you must also update the VCU codes.)
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* @VENC_YUV_FORMAT_I420: I420 YUV format
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* @VENC_YUV_FORMAT_YV12: YV12 YUV format
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* @VENC_YUV_FORMAT_NV12: NV12 YUV format
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* @VENC_YUV_FORMAT_NV21: NV21 YUV format
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*/
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enum venc_yuv_fmt {
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VENC_YUV_FORMAT_I420 = 3,
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VENC_YUV_FORMAT_YV12 = 5,
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VENC_YUV_FORMAT_NV12 = 6,
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VENC_YUV_FORMAT_NV21 = 7,
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VENC_YUV_FORMAT_24bitRGB888 = 11,
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VENC_YUV_FORMAT_24bitBGR888 = 12,
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VENC_YUV_FORMAT_32bitRGBA8888 = 13,
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VENC_YUV_FORMAT_32bitBGRA8888 = 14,
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VENC_YUV_FORMAT_32bitARGB8888 = 15,
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VENC_YUV_FORMAT_32bitABGR8888 = 16,
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VENC_YUV_FORMAT_32bitRGBA1010102 = 17,
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VENC_YUV_FORMAT_32bitBGRA1010102 = 18,
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VENC_YUV_FORMAT_32bitARGB1010102 = 19,
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VENC_YUV_FORMAT_32bitABGR1010102 = 20,
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VENC_YUV_FORMAT_32bitRGBA8888_AFBC = 21,
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VENC_YUV_FORMAT_32bitBGRA8888_AFBC = 22,
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VENC_YUV_FORMAT_32bitRGBA1010102_AFBC = 23,
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VENC_YUV_FORMAT_32bitBGRA1010102_AFBC = 24,
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VENC_YUV_FORMAT_MT10 = 25,
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VENC_YUV_FORMAT_P010 = 26,
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VENC_YUV_FORMAT_NV12_AFBC = 27,
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VENC_YUV_FORMAT_NV12_10B_AFBC = 28,
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VENC_YUV_FORMAT_NV21_AFBC = 29,
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};
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/**
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* struct mtk_q_type - Type of queue
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*/
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enum mtk_q_type {
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MTK_Q_DATA_SRC = 0,
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MTK_Q_DATA_DST = 1,
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};
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/** * enum mtk_ts_mode - Mode of timestamp */
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enum mtk_ts_mode {
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MTK_TS_MODE_PTS = 0,
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MTK_TS_MODE_DTS = 1,
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MTK_TS_MODE_DETECTING = 2,
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};
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/**
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* enum input_driven_mode - decoder different input driven mode
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* @NON_INPUT_DRIVEN : non input driven, bs/frm pairwise trigger ipi
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* @INPUT_DRIVEN_CB_FRM : input driven, codec callback get frame
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* @INPUT_DRIVEN_PUT_FRM : input driven, v4l2 initiatively put frame to codec
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*/
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enum vdec_input_driven_mode {
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NON_INPUT_DRIVEN = 0,
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INPUT_DRIVEN_CB_FRM = 1,
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INPUT_DRIVEN_PUT_FRM = 2,
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};
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/**
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* enum vdec_align_status - decoder different status when align mode
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* @VDEC_ALIGN_WAIT : need to wait display vsync align
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* @VDEC_ALIGN_FULL : input output buffer pair over limit, start decode and not wait align
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* @VDEC_ALIGN_RESET : get EOS to reset so continuous decoding, don't need to wait align
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*/
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enum vdec_align_status {
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VDEC_ALIGN_WAIT = 0,
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VDEC_ALIGN_FULL = 1,
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VDEC_ALIGN_RESET = 2,
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};
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enum venc_lock {
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VENC_LOCK_NONE,
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VENC_LOCK_NORMAL,
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VENC_LOCK_SEC
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};
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enum vdec_power_type {
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VDEC_POWER_NORMAL = 0,
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VDEC_POWER_RELEASE,
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VDEC_POWER_ALWAYS,
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VDEC_POWER_ALWAYS_OP,
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VDEC_POWER_ALWAYS_FREQ,
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};
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/**
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* struct mtk_q_data - Structure used to store information about queue
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*/
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struct mtk_q_data {
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unsigned int visible_width;
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unsigned int visible_height;
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unsigned int coded_width;
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unsigned int coded_height;
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enum v4l2_field field;
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unsigned int bytesperline[MTK_VCODEC_MAX_PLANES];
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unsigned int sizeimage[MTK_VCODEC_MAX_PLANES];
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struct mtk_video_fmt *fmt;
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};
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enum mtk_dec_param {
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MTK_DEC_PARAM_NONE = 0,
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MTK_DEC_PARAM_DECODE_MODE = (1 << 0),
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MTK_DEC_PARAM_FRAME_SIZE = (1 << 1),
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MTK_DEC_PARAM_FIXED_MAX_FRAME_SIZE = (1 << 2),
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MTK_DEC_PARAM_CRC_PATH = (1 << 3),
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MTK_DEC_PARAM_GOLDEN_PATH = (1 << 4),
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MTK_DEC_PARAM_WAIT_KEY_FRAME = (1 << 5),
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MTK_DEC_PARAM_NAL_SIZE_LENGTH = (1 << 6),
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MTK_DEC_PARAM_FIXED_MAX_OUTPUT_BUFFER = (1 << 7),
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MTK_DEC_PARAM_SEC_DECODE = (1 << 8),
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MTK_DEC_PARAM_OPERATING_RATE = (1 << 9),
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MTK_DEC_PARAM_DV = (1 << 10),
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MTK_DEC_PARAM_DECODE_ERROR_HANDLE_MODE = (1 << 11)
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};
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struct mtk_dec_params {
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unsigned int decode_mode;
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unsigned int frame_size_width;
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unsigned int frame_size_height;
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unsigned int fixed_max_frame_size_width;
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unsigned int fixed_max_frame_size_height;
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unsigned int fixed_max_frame_buffer_mode;
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char *crc_path;
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char *golden_path;
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unsigned int fb_num_planes;
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unsigned int wait_key_frame;
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unsigned int decode_error_handle_mode;
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unsigned int nal_size_length;
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unsigned int svp_mode;
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unsigned int operating_rate;
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u64 timestamp;
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unsigned int total_frame_bufq_count;
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unsigned int queued_frame_buf_count;
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int priority;
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int vpeek;
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bool enable_detect_ts;
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int slice_count;
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struct hdr10plus_info hdr10plus_buf;
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};
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struct mtk_detect_ts_param {
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enum mtk_ts_mode mode;
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struct mutex lock;
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u64 first_disp_ts;
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u64 record[VB2_MAX_FRAME];
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int read_idx;
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int recorded_size;
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};
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/**
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* struct mtk_enc_params - General encoding parameters
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* @bitrate: target bitrate in bits per second
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* @num_b_frame: number of b frames between p-frame
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* @rc_frame: frame based rate control
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* @rc_mb: macroblock based rate control
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* @seq_hdr_mode: H.264 sequence header is encoded separately or joined
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* with the first frame
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* @intra_period: I frame period
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* @gop_size: group of picture size, it's used as the intra frame period
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* @framerate_num: frame rate numerator. ex: framerate_num=30 and
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* framerate_denom=1 menas FPS is 30
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* @framerate_denom: frame rate denominator. ex: framerate_num=30 and
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* framerate_denom=1 menas FPS is 30
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* @h264_max_qp: Max value for H.264 quantization parameter
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* @h264_profile: V4L2 defined H.264 profile
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* @h264_level: V4L2 defined H.264 level
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* @force_intra: force/insert intra frame
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*/
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struct mtk_enc_params {
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unsigned int bitrate;
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unsigned int num_b_frame;
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unsigned int rc_frame;
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unsigned int rc_mb;
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unsigned int seq_hdr_mode;
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unsigned int intra_period;
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unsigned int gop_size;
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unsigned int framerate_num;
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unsigned int framerate_denom;
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unsigned int h264_max_qp;
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unsigned int profile;
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unsigned int level;
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unsigned int tier;
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unsigned int force_intra;
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unsigned int scenario;
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unsigned int nonrefp;
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unsigned int detectframerate;
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unsigned int rfs;
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unsigned int prependheader;
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unsigned int operationrate;
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unsigned int bitratemode;
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unsigned int roion;
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unsigned int heif_grid_size;
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struct mtk_color_desc color_desc; // data from userspace
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struct mtk_venc_multi_ref multi_ref; //data from userspace
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unsigned int max_w;
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unsigned int max_h;
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unsigned int slbc_ready;
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unsigned int slbc_encode_performance;
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unsigned int i_qp;
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unsigned int p_qp;
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unsigned int b_qp;
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unsigned int svp_mode;
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unsigned int tsvc;
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unsigned int nonrefpfreq;
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unsigned int highquality;
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int max_qp;
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int min_qp;
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int framelvl_qp;
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int ip_qpdelta;
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unsigned int qp_control_mode;
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unsigned int dummynal;
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int priority;
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unsigned int wpp_mode;
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unsigned int low_latency_mode;
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unsigned int use_irq;
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unsigned int hier_ref_layer;
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unsigned int hier_ref_type;
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unsigned int temporal_layer_pcount;
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unsigned int temporal_layer_bcount;
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unsigned int max_ltr_num;
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unsigned int slice_header_spacing;
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struct mtk_venc_vui_info vui_info; //data from userspace
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int cb_qp_offset;
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int cr_qp_offset;
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};
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/*
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* struct venc_enc_prm - encoder settings for VENC_SET_PARAM_ENC used in
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* venc_if_set_param()
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* @input_fourcc: input yuv format
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* @h264_profile: V4L2 defined H.264 profile
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* @h264_level: V4L2 defined H.264 level
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* @width: image width
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* @height: image height
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* @buf_width: buffer width
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* @buf_height: buffer height
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* @frm_rate: frame rate in fps
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* @intra_period: intra frame period
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* @bitrate: target bitrate in bps
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* @gop_size: group of picture size
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* @sizeimage: image size for each plane
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*/
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struct venc_enc_param {
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enum venc_yuv_fmt input_yuv_fmt;
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unsigned int profile;
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unsigned int level;
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unsigned int tier;
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unsigned int width;
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unsigned int height;
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unsigned int buf_width;
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unsigned int buf_height;
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unsigned int frm_rate;
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unsigned int intra_period;
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unsigned int bitrate;
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unsigned int gop_size;
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unsigned int scenario;
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unsigned int nonrefp;
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unsigned int detectframerate;
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unsigned int rfs;
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unsigned int prependheader;
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unsigned int operationrate;
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unsigned int bitratemode;
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unsigned int roion;
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unsigned int heif_grid_size;
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// pointed to mtk_enc_params::color_desc
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struct mtk_color_desc *color_desc;
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unsigned int sizeimage[MTK_VCODEC_MAX_PLANES];
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unsigned int max_w;
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unsigned int max_h;
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unsigned int num_b_frame;
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unsigned int slbc_ready;
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unsigned int i_qp;
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unsigned int p_qp;
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unsigned int b_qp;
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unsigned int svp_mode;
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unsigned int tsvc;
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unsigned int nonrefpfreq;
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unsigned int highquality;
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unsigned int max_qp;
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unsigned int min_qp;
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unsigned int framelvl_qp;
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unsigned int qp_control_mode;
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unsigned int ip_qpdelta;
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unsigned int dummynal;
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unsigned int slbc_addr;
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char *set_vcp_buf;
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unsigned int wpp_mode;
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unsigned int low_latency_mode;
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unsigned int hier_ref_layer;
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unsigned int hier_ref_type;
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unsigned int temporal_layer_pcount;
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unsigned int temporal_layer_bcount;
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unsigned int max_ltr_num;
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unsigned int slice_header_spacing;
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struct mtk_venc_multi_ref *multi_ref;
|
|
struct mtk_venc_vui_info *vui_info;
|
|
char *log;
|
|
int cb_qp_offset;
|
|
int cr_qp_offset;
|
|
};
|
|
|
|
/*
|
|
* struct venc_frm_buf - frame buffer information used in venc_if_encode()
|
|
* @fb_addr: plane frame buffer addresses
|
|
* @num_planes: frmae buffer plane num
|
|
*/
|
|
struct venc_frm_buf {
|
|
struct mtk_vcodec_mem fb_addr[MTK_VCODEC_MAX_PLANES];
|
|
u32 index;
|
|
unsigned int num_planes;
|
|
u64 timestamp;
|
|
bool has_meta;
|
|
struct dma_buf *meta_dma;
|
|
struct dma_buf_attachment *buf_att;
|
|
struct sg_table *sgt;
|
|
dma_addr_t meta_addr;
|
|
struct dma_buf_attachment *qpmap_dma_att;
|
|
struct sg_table *qpmap_sgt;
|
|
unsigned int meta_offset;
|
|
bool has_qpmap;
|
|
struct dma_buf *qpmap_dma;
|
|
dma_addr_t qpmap_dma_addr;
|
|
struct dma_buf *metabuffer_dma;
|
|
dma_addr_t metabuffer_addr;
|
|
dma_addr_t dyparams_dma_addr;
|
|
struct dma_buf *dyparams_dma;
|
|
};
|
|
|
|
struct dma_gen_buf {
|
|
void *va;
|
|
struct dma_buf *dmabuf;
|
|
dma_addr_t dma_general_addr;
|
|
struct dma_buf_attachment *buf_att;
|
|
struct sg_table *sgt;
|
|
};
|
|
|
|
struct dma_meta_buf {
|
|
struct dma_buf *dmabuf;
|
|
dma_addr_t dma_meta_addr;
|
|
struct dma_buf_attachment *buf_att;
|
|
struct sg_table *sgt;
|
|
};
|
|
|
|
enum metadata_type {
|
|
METADATA_HDR = 0,
|
|
METADATA_QPMAP = 1,
|
|
METADATA_DYNAMICPARAM = 2
|
|
};
|
|
|
|
struct meta_describe {
|
|
uint8_t invalid; //1: valid 0:invalid
|
|
uint8_t fd_flag; //whether pass with fd - 1:yes 0:no
|
|
uint32_t type;
|
|
uint32_t size; //size of metadata (total in 32 bits length)
|
|
uint32_t value; //fd number or memory offset from the begginning of metadata buffer
|
|
};
|
|
|
|
struct metadata_info {
|
|
struct meta_describe metadata_dsc[MTK_MAX_METADATA_NUM];
|
|
};
|
|
|
|
struct vdec_set_frame_work_struct {
|
|
struct work_struct work;
|
|
struct mtk_vcodec_ctx *ctx;
|
|
};
|
|
|
|
struct vdec_check_alive_work_struct {
|
|
struct work_struct work;
|
|
struct mtk_vcodec_ctx *ctx;
|
|
struct mtk_vcodec_dev *dev;
|
|
};
|
|
|
|
/**
|
|
* struct mtk_vcodec_ctx - Context (instance) private data.
|
|
*
|
|
* @type: type of the instance - decoder or encoder
|
|
* @dev: pointer to the mtk_vcodec_dev of the device
|
|
* @list: link to ctx_list of mtk_vcodec_dev
|
|
* @fh: struct v4l2_fh
|
|
* @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
|
|
* @q_data: store information of input and output queue
|
|
* of the context
|
|
* @id: index of the context that this structure describes
|
|
* @state: state of the context
|
|
* @dec_param_change: indicate decode parameter type
|
|
* @dec_params: decoding parameters
|
|
* @param_change: indicate encode parameter type
|
|
* @enc_params: encoding parameters
|
|
* @dec_if: hooked decoder driver interface
|
|
* @enc_if: hoooked encoder driver interface
|
|
* @drv_handle: driver handle for specific decode/encode instance
|
|
*
|
|
* @picinfo: store picture info after header parsing
|
|
* @dpb_size: store dpb count after header parsing
|
|
* @int_cond: variable used by the waitqueue
|
|
* @int_type: type of the last interrupt
|
|
* @queue: waitqueue that can be used to wait for this context to
|
|
* finish
|
|
* @irq_status: irq status
|
|
*
|
|
* @ctrl_hdl: handler for v4l2 framework
|
|
* @decode_work: worker for the decoding
|
|
* @encode_work: worker for the encoding
|
|
* @last_decoded_picinfo: pic information get from latest decode
|
|
* @dec_flush_buf: a fake size-1 output buffer that indicates flush
|
|
* @enc_flush_buf: a fake size-1 output buffer that indicates flush
|
|
* @oal_vcodec: 1: oal encoder, 0:non-oal encoder
|
|
* @pend_src_buf: pending source buffer
|
|
*
|
|
* @colorspace: enum v4l2_colorspace; supplemental to pixelformat
|
|
* @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
|
|
* @quantization: enum v4l2_quantization, colorspace quantization
|
|
* @xfer_func: enum v4l2_xfer_func, colorspace transfer function
|
|
* @lock: protect variables accessed by V4L2 threads and worker thread such as
|
|
* mtk_video_dec_buf.
|
|
*/
|
|
struct mtk_vcodec_ctx {
|
|
enum mtk_instance_type type;
|
|
struct mtk_vcodec_dev *dev;
|
|
struct list_head list;
|
|
unsigned int add_list_cnt;
|
|
|
|
struct v4l2_fh fh;
|
|
struct v4l2_m2m_ctx *m2m_ctx;
|
|
struct device *general_dev;
|
|
struct mtk_q_data q_data[2];
|
|
int id;
|
|
enum mtk_instance_state state;
|
|
enum mtk_dec_param dec_param_change;
|
|
struct mtk_dec_params dec_params;
|
|
enum mtk_encode_param param_change;
|
|
struct mtk_enc_params enc_params;
|
|
|
|
const struct vdec_common_if *dec_if;
|
|
const struct venc_common_if *enc_if;
|
|
unsigned long drv_handle;
|
|
uintptr_t bs_list[VB2_MAX_FRAME+1];
|
|
uintptr_t fb_list[VB2_MAX_FRAME+1];
|
|
|
|
struct vdec_pic_info picinfo;
|
|
int dpb_size;
|
|
int last_dpb_size;
|
|
int is_hdr;
|
|
int last_is_hdr;
|
|
unsigned int errormap_info[VB2_MAX_FRAME];
|
|
u32 err_msg;
|
|
s64 input_max_ts;
|
|
struct mtk_detect_ts_param detect_ts_param;
|
|
|
|
bool is_flushing;
|
|
unsigned int eos_type;
|
|
u64 early_eos_ts;
|
|
|
|
int int_cond[MTK_VDEC_IRQ_NUM];
|
|
int int_type;
|
|
wait_queue_head_t queue[MTK_VDEC_IRQ_NUM];
|
|
unsigned int irq_status;
|
|
|
|
struct v4l2_ctrl_handler ctrl_hdl;
|
|
struct work_struct decode_work;
|
|
struct work_struct encode_work;
|
|
struct vdec_pic_info last_decoded_picinfo;
|
|
struct mtk_video_dec_buf *dec_flush_buf;
|
|
struct mtk_video_enc_buf *enc_flush_buf;
|
|
struct vb2_buffer *pend_src_buf;
|
|
wait_queue_head_t fm_wq;
|
|
wait_queue_head_t bs_wq;
|
|
unsigned int *ipi_blocked;
|
|
enum vdec_input_driven_mode input_driven;
|
|
bool align_mode;
|
|
atomic_t align_type; // flag for enum vdec_align_status
|
|
unsigned char *wait_align; // flag for waiting display vsync
|
|
int align_start_cnt;
|
|
unsigned char *src_cnt;
|
|
unsigned char *dst_cnt;
|
|
|
|
struct workqueue_struct *vdec_set_frame_wq;
|
|
struct vdec_set_frame_work_struct vdec_set_frame_work;
|
|
|
|
/* for user lock HW case release check */
|
|
struct mutex hw_status;
|
|
enum vdec_power_type power_type[MTK_VDEC_HW_NUM];
|
|
int hw_locked[MTK_VDEC_HW_NUM];
|
|
int core_locked[MTK_VENC_HW_NUM];
|
|
int async_mode;
|
|
int oal_vcodec;
|
|
|
|
enum v4l2_colorspace colorspace;
|
|
enum v4l2_ycbcr_encoding ycbcr_enc;
|
|
enum v4l2_quantization quantization;
|
|
enum v4l2_xfer_func xfer_func;
|
|
|
|
int init_cnt;
|
|
int decoded_frame_cnt;
|
|
int last_decoded_frame_cnt; // used for timer to check active state of decoded ctx
|
|
|
|
/* used for vcp background idle check */
|
|
unsigned int vcp_action_cnt;
|
|
unsigned int last_vcp_action_cnt;
|
|
bool is_vcp_active;
|
|
struct mutex vcp_active_mutex;
|
|
|
|
struct mutex buf_lock;
|
|
struct mutex worker_lock;
|
|
struct slbc_data sram_data;
|
|
struct mutex q_mutex;
|
|
int use_slbc;
|
|
unsigned int slbc_addr;
|
|
int sysram_enable;
|
|
#if ENABLE_FENCE
|
|
struct sync_timeline *p_timeline_obj;
|
|
#endif
|
|
bool use_fence;
|
|
int fence_idx;
|
|
struct dma_gen_buf dma_buf_list[MAX_GEN_BUF_CNT];
|
|
struct dma_meta_buf dma_meta_list[MAX_META_BUF_CNT];
|
|
struct mutex gen_buf_va_lock;
|
|
/*
|
|
* need resched or not
|
|
* core want to re-schedule m2m ctx if disp/free list is not empty
|
|
*/
|
|
bool resched;
|
|
struct mutex resched_lock;
|
|
unsigned char is_active;
|
|
};
|
|
|
|
/*
|
|
* struct venc_frm_buf - frame buffer information used in venc_if_encode()
|
|
* @fb_addr: plane frame buffer addresses
|
|
* @num_planes: frmae buffer plane num
|
|
*/
|
|
struct venc_larb_port {
|
|
unsigned int total_port_num;
|
|
unsigned int port_id[MTK_VENC_PORT_NUM];
|
|
unsigned int ram_type[MTK_VENC_PORT_NUM];
|
|
};
|
|
|
|
|
|
/**
|
|
* struct mtk_vcodec_dev - driver data
|
|
* @v4l2_dev: V4L2 device to register video devices for.
|
|
* @vfd_dec: Video device for decoder
|
|
* @vfd_enc: Video device for encoder.
|
|
*
|
|
* @m2m_dev_dec: m2m device for decoder
|
|
* @m2m_dev_enc: m2m device for encoder.
|
|
* @plat_dev: platform device
|
|
* @vcu_plat_dev: mtk vcu platform device
|
|
* @ctx_list: list of struct mtk_vcodec_ctx
|
|
* @irqlock: protect data access by irq handler and work thread
|
|
* @curr_ctx: The context that is waiting for codec hardware
|
|
*
|
|
* @reg_base: Mapped address of MTK Vcodec registers.
|
|
*
|
|
* @id_counter: used to identify current opened instance
|
|
*
|
|
* @encode_workqueue: encode work queue
|
|
*
|
|
* @int_cond: used to identify interrupt condition happen
|
|
* @int_type: used to identify what kind of interrupt condition happen
|
|
* @dev_mutex: video_device lock
|
|
* @queue: waitqueue for waiting for completion of device commands
|
|
*
|
|
* @dec_irq: decoder irq resource
|
|
* @enc_irq: h264 encoder irq resource
|
|
* @enc_lt_irq: vp8 encoder irq resource
|
|
*
|
|
* @dec_sem: decoder hw lock. Use sem for gce different thread lock unlock
|
|
* @enc_sem: encoder hw lock. Use sem for gce different thread lock unlock
|
|
*
|
|
* @pm: power management control
|
|
* @dec_capability: used to identify decode capability, ex: 4k
|
|
* @enc_capability: used to identify encode capability
|
|
*/
|
|
struct mtk_vcodec_dev {
|
|
struct v4l2_device v4l2_dev;
|
|
struct video_device *vfd_dec;
|
|
struct video_device *vfd_enc;
|
|
struct iommu_domain *io_domain;
|
|
|
|
const char *platform;
|
|
enum mtk_vcodec_ipm vdec_hw_ipm;
|
|
enum mtk_vcodec_ipm venc_hw_ipm;
|
|
|
|
struct v4l2_m2m_dev *m2m_dev_dec;
|
|
struct v4l2_m2m_dev *m2m_dev_enc;
|
|
struct platform_device *plat_dev;
|
|
struct platform_device *vcu_plat_dev;
|
|
struct list_head ctx_list;
|
|
struct notifier_block vcp_notify;
|
|
spinlock_t irqlock;
|
|
struct mtk_vcodec_ctx *curr_dec_ctx[MTK_VDEC_HW_NUM];
|
|
struct mtk_vcodec_ctx *curr_enc_ctx[MTK_VENC_HW_NUM];
|
|
void __iomem *dec_reg_base[NUM_MAX_VDEC_REG_BASE];
|
|
void __iomem *enc_reg_base[NUM_MAX_VENC_REG_BASE];
|
|
|
|
bool dec_is_power_on[MTK_VDEC_HW_NUM];
|
|
bool enc_is_power_on[MTK_VENC_HW_NUM];
|
|
spinlock_t dec_power_lock[MTK_VDEC_HW_NUM];
|
|
spinlock_t enc_power_lock[MTK_VENC_HW_NUM];
|
|
int dec_m4u_ports[NUM_MAX_VDEC_M4U_PORT];
|
|
atomic_t dec_clk_ref_cnt[MTK_VDEC_HW_NUM];
|
|
atomic_t dec_larb_ref_cnt;
|
|
|
|
unsigned long id_counter;
|
|
|
|
struct workqueue_struct *decode_workqueue;
|
|
struct workqueue_struct *encode_workqueue;
|
|
struct workqueue_struct *check_alive_workqueue;
|
|
struct vdec_check_alive_work_struct check_alive_work;
|
|
struct mutex check_alive_mutex;
|
|
|
|
int int_cond;
|
|
int int_type;
|
|
struct mutex ctx_mutex;
|
|
struct mutex dev_mutex;
|
|
struct mutex ipi_mutex;
|
|
struct mutex ipi_mutex_res;
|
|
struct mtk_vcodec_msgq mq;
|
|
|
|
int dec_irq[MTK_VDEC_IRQ_NUM];
|
|
int enc_irq[MTK_VENC_HW_NUM];
|
|
int enc_lt_irq;
|
|
|
|
struct semaphore dec_sem[MTK_VDEC_HW_NUM];
|
|
struct semaphore enc_sem[MTK_VENC_HW_NUM];
|
|
unsigned int dec_always_on[MTK_VDEC_HW_NUM]; // ref count
|
|
bool dec_is_suspend_off;
|
|
bool dvfs_is_suspend_off;
|
|
struct mutex dec_always_on_mutex;
|
|
atomic_t dec_hw_active[MTK_VDEC_HW_NUM];
|
|
|
|
struct mutex dec_dvfs_mutex;
|
|
struct mutex enc_dvfs_mutex;
|
|
|
|
struct mtk_vcodec_pm pm;
|
|
struct notifier_block pm_notifier;
|
|
bool is_codec_suspending;
|
|
bool codec_stop_done;
|
|
|
|
int dec_cnt;
|
|
int enc_cnt;
|
|
|
|
struct share_obj dec_ipi_data;
|
|
struct share_obj enc_ipi_data;
|
|
int *dec_mem_slot_stat;
|
|
int *enc_mem_slot_stat;
|
|
|
|
int dec_hw_cnt;
|
|
int enc_hw_cnt;
|
|
|
|
struct plist_head vdec_rlist[MTK_VDEC_HW_NUM];
|
|
struct plist_head venc_rlist[MTK_VENC_HW_NUM];
|
|
struct icc_path *vdec_qos_req[MTK_VDEC_PORT_NUM];
|
|
struct icc_path *venc_qos_req[MTK_VENC_PORT_NUM];
|
|
|
|
int vdec_freq_cnt;
|
|
int venc_freq_cnt;
|
|
unsigned long vdec_freqs[MAX_CODEC_FREQ_STEP];
|
|
unsigned long venc_freqs[MAX_CODEC_FREQ_STEP];
|
|
|
|
struct regulator *vdec_reg;
|
|
struct regulator *venc_reg;
|
|
struct venc_larb_port venc_ports[MTK_VENC_HW_NUM];
|
|
struct workqueue_struct *vdec_buf_wq;
|
|
struct work_struct vdec_buf_work;
|
|
|
|
int vdec_op_rate_cnt;
|
|
//int venc_op_rate_cnt;
|
|
int vdec_tput_cnt;
|
|
int venc_tput_cnt;
|
|
int vdec_cfg_cnt;
|
|
int venc_cfg_cnt;
|
|
int vdec_port_cnt;
|
|
int venc_port_cnt;
|
|
int venc_larb_cnt;
|
|
int vdec_larb_cnt;
|
|
int vdec_port_idx[MTK_VDEC_HW_NUM];
|
|
int venc_port_idx[MTK_VENC_HW_NUM];
|
|
struct mtk_tf_info *tf_info;
|
|
struct vcodec_perf *vdec_tput;
|
|
struct vcodec_perf *venc_tput;
|
|
//struct vcodec_config *vdec_cfg;
|
|
struct vcodec_config *venc_cfg;
|
|
struct vcodec_op_rate *vdec_dflt_op_rate;
|
|
//struct vcodec_op_rate *venc_dflt_op_rate;
|
|
struct clk *vdec_mmdvfs_clk;
|
|
struct clk *venc_mmdvfs_clk;
|
|
struct list_head vdec_dvfs_inst;
|
|
struct list_head venc_dvfs_inst;
|
|
struct dvfs_params vdec_dvfs_params;
|
|
struct dvfs_params venc_dvfs_params;
|
|
struct vcodec_port_bw *vdec_port_bw;
|
|
struct vcodec_port_bw *venc_port_bw;
|
|
struct vcodec_larb_bw *vdec_larb_bw;
|
|
struct vcodec_larb_bw *venc_larb_bw;
|
|
/**
|
|
* struct ion_client *ion_vdec_client;
|
|
* struct ion_client *ion_venc_client;
|
|
**/
|
|
struct list_head log_param_list;
|
|
struct list_head prop_param_list;
|
|
struct mutex log_param_mutex;
|
|
struct mutex prop_param_mutex;
|
|
};
|
|
|
|
static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
|
|
{
|
|
return container_of(fh, struct mtk_vcodec_ctx, fh);
|
|
}
|
|
|
|
static inline struct mtk_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
|
|
{
|
|
return container_of(ctrl->handler, struct mtk_vcodec_ctx, ctrl_hdl);
|
|
}
|
|
|
|
#endif /* _MTK_VCODEC_DRV_H_ */
|