94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_CAM_AOV_H
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#define __MTK_CAM_AOV_H
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#define MAX_DEST_NUM 4
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struct seninf_vc_out_dest {
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u8 mux; // allocated per group
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u8 mux_vr; // allocated per group
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u8 cam; // assigned by cam driver
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u8 tag; // assigned by cam driver
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u8 cam_type; // assigned by cam driver
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};
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struct seninf_vc {
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u8 vc;
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u8 dt;
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u8 feature;
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u8 out_pad;
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u8 pixel_mode;
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u8 group;
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u8 dest_cnt;
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struct seninf_vc_out_dest dest[MAX_DEST_NUM];
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u8 enable;
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u16 exp_hsize;
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u16 exp_vsize;
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u8 bit_depth;
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u8 dt_remap_to_type;
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u8 muxvr_offset;
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};
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/* camsys supported parameter */
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struct mtk_seninf_aov_param {
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struct seninf_vc vc;
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unsigned int sensor_idx;
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unsigned int is_cphy:1;
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int num_data_lanes;
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s64 mipi_pixel_rate;
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s64 width;
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s64 height;
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s64 hblank;
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s64 vblank;
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int fps_n;
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int fps_d;
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s64 customized_pixel_rate;
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int port;
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int portA;
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int portB;
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unsigned int is_4d1c:1;
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int seninfIdx;
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u32 cphy_settle;
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u32 dphy_clk_settle;
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u32 dphy_data_settle;
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u32 dphy_trail;
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u8 legacy_phy;
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u8 not_fixed_trail_settle;
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int cnt;
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int is_test_model;
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int isp_freq;
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int camtg;
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int seninf_dphy_settle_delay_dt;
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int cphy_settle_delay_dt;
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int dphy_settle_delay_dt;
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int settle_delay_ck;
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int hs_trail_parameter;
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u32 dphy_csi2_resync_dmy_cycle;
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u8 not_fixed_dphy_settle;
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};
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enum AOV_DEINIT_TYPE {
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DEINIT_NORMAL = 0,
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DEINIT_ABNORMAL_USR_FD_KILL,
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DEINIT_ABNORMAL_SCP_STOP,
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};
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enum AOV_INIT_TYPE {
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INIT_NORMAL = 0,
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INIT_ABNORMAL_SCP_READY,
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};
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extern int mtk_cam_seninf_s_aov_param(unsigned int sensor_id,
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struct mtk_seninf_aov_param *aov_seninf_param,
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enum AOV_INIT_TYPE aov_seninf_init_type);
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extern int mtk_cam_seninf_aov_runtime_suspend(unsigned int sensor_id);
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extern int mtk_cam_seninf_aov_runtime_resume(unsigned int sensor_id,
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enum AOV_DEINIT_TYPE aov_seninf_deinit_type);
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#endif /* __MTK_CAM_AOV_H */
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