650 lines
15 KiB
C
650 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*/
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#ifndef __MTK_IMG_IPI_H__
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#define __MTK_IMG_IPI_H__
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#include <linux/types.h>
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#include <linux/time.h>
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#include "mtk_header_desc.h"
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#ifndef __KERNEL__
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#define BIT(nr) (1UL << (nr))
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typedef u_int8_t u8;
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typedef int8_t s8;
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typedef u_int16_t u16;
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typedef int16_t s16;
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typedef u_int32_t u32;
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typedef int32_t s32;
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typedef u_int64_t u64;
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typedef int64_t s64;
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#endif
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/* updated in W1948.1 */
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#define HEADER_VER 19481
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/* ISP-MDP generic input information */
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#define MTK_V4L2_BATCH_MODE_SUPPORT 1
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#define MTK_V4L2_SKIP_TILE_SUPPORT 0
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#define MTK_V4L2_CTRL_META_SUPPORT 1
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/* TODO */
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#define IMG_MAX_HW_INPUTS 3
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#define IMG_MAX_HW_OUTPUTS 4
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#define IMG_MAX_HW_DMAS 88
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#define IMG_MAX_PLANES 3
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#define IMG_IPI_INIT 1
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#define IMG_IPI_DEINIT 2
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#define IMG_IPI_FRAME 3
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#define IMG_IPI_DEBUG 4
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#define IMG_MODULE_SET 5
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struct module_init_info {
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uint64_t c_wbuf;
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uint64_t c_wbuf_dma;
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uint32_t c_wbuf_sz;
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uint32_t c_wbuf_fd;
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uint64_t t_wbuf;
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uint64_t t_wbuf_dma;
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uint32_t t_wbuf_sz;
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uint32_t t_wbuf_fd;
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} __packed;
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struct img_init_info {
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uint32_t header_version;
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uint32_t isp_version;
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uint32_t dip_save_file;
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uint32_t param_pack_size;
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uint32_t dip_param_size;
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uint32_t frameparam_size;
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uint32_t reg_phys_addr;
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uint32_t reg_range;
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uint64_t hw_buf_fd;
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uint64_t hw_buf;
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uint32_t hw_buf_size;
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uint32_t reg_table_size;
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uint32_t sub_frm_size;
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uint32_t cq_size;
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uint64_t drv_data;
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/*new add, need refine*/
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struct module_init_info module_info[IMG_MODULE_SET];
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uint32_t g_wbuf_fd;
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uint64_t g_wbuf;
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uint32_t g_wbuf_sz;
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uint32_t sec_tag;
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uint16_t full_wd;
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uint16_t full_ht;
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uint32_t smvr_mode;
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} __packed;
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#define KFENCE_MAX 4
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struct fence_event {
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int fence_fd;
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uint64_t *dma_fence;
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int gce_event;
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} __packed;
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struct img_swfrm_info {
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uint32_t hw_comb;
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int sw_ridx;
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uint8_t is_time_shared;
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uint8_t is_secFrm;
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uint8_t is_earlycb;
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uint8_t is_lastingroup;
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uint64_t sw_goft;
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uint64_t sw_bwoft;
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int subfrm_idx;
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void *g_swbuf;
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void *bw_swbuf;
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uint64_t pixel_bw;
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int wait_fence_num;
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struct fence_event wait_fence_list[KFENCE_MAX];
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int notify_fence_num;
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struct fence_event notify_fence_list[KFENCE_MAX];
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} __packed;
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struct img_addr {
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u64 va; /* Used by Linux OS access */
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u32 pa; /* Used by CM4 access */
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u32 iova; /* Used by IOMMU HW access */
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u32 offset; /* Used by User Daemon access */
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#ifdef MTK_V4L2_BATCH_MODE_SUPPORT
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// Batch mode {
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int fd;
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// } Batch mode
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#endif
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} __packed;
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struct tuning_addr {
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u64 va; /* Used by Linux OS access */
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u64 present;
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u32 pa; /* Used by CM4 access */
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u32 iova; /* Used by IOMMU HW access */
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} __packed;
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struct img_sw_addr {
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u64 va; /* Used by APMCU access */
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u32 pa; /* Used by CM4 access */
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u32 offset; /* Used by User Daemon access */
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#ifdef MTK_V4L2_BATCH_MODE_SUPPORT
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// Batch mode {
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u32 fd; /* Used by User Daemon access */
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// } Batch mode
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#endif
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} __packed;
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struct img_plane_format {
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u32 size;
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u16 stride;
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} __packed;
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struct img_pix_format {
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u16 width;
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u16 height;
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u32 colorformat; /* enum mdp_color */
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u16 ycbcr_prof; /* enum mdp_ycbcr_profile */
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struct img_plane_format plane_fmt[IMG_MAX_PLANES];
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} __packed;
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struct img_image_buffer {
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struct img_pix_format format;
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u32 iova[IMG_MAX_PLANES];
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/* enum mdp_buffer_usage, FD or advanced ISP usages */
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u32 usage;
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s32 fd[IMG_MAX_PLANES];
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} __packed;
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struct img_rect {
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int16_t left;
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int16_t top;
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uint16_t width;
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uint16_t height;
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} __packed;
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#define IMG_SUBPIXEL_SHIFT 20
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struct img_crop {
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s16 left;
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s16 top;
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u16 width;
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u16 height;
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u32 left_subpix;
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u32 top_subpix;
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u32 width_subpix;
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u32 height_subpix;
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} __packed;
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#define IMG_CTRL_FLAG_HFLIP BIT(0)
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#define IMG_CTRL_FLAG_DITHER BIT(1)
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#define IMG_CTRL_FLAG_SHARPNESS BIT(4)
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#define IMG_CTRL_FLAG_HDR BIT(5)
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#define IMG_CTRL_FLAG_DRE BIT(6)
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struct img_input {
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struct img_image_buffer buffer;
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u16 flags; /* HDR, DRE, dither */
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} __packed;
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struct img_output {
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struct img_image_buffer buffer;
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struct img_crop crop;
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struct img_rect compose;
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s16 rotation;
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u16 flags; /* H-flip, sharpness, dither */
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u8 type; /* MCRP-D1, MCRP-D2 */
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} __packed;
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// Batch Mode {
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#if (MTK_V4L2_BATCH_MODE_SUPPORT == 1 || MTK_V4L2_CTRL_META_SUPPORT == 1)
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#define MAX_SRZ_CONFIGS 5
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#define MAX_EXTRA_PARAMS 5
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enum dip_srz_module {
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DIP_SRZ_NONE = 0x0000,
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DIP_SRZ1 = 0x0001,
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DIP_SRZ2 = 0x0002,
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DIP_SRZ3 = 0x0004,
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DIP_SRZ4 = 0x0008,
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DIP_SRZ5 = 0x0010,
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};
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struct srz_config {
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enum dip_srz_module srz_module_id;
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uint32_t in_w;
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uint32_t in_h;
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uint32_t out_w;
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uint32_t out_h;
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uint32_t crop_x;
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uint32_t crop_y;
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uint32_t crop_floatX; /* x float precise - 32 bit */
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uint32_t crop_floatY; /* y float precise - 32 bit */
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unsigned long crop_w;
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unsigned long crop_h;
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} __packed;
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/* need to refine it for better memory usage.
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* See FEInfo(48B), FMInfo(32B), CrspInfo(24B), MFBConfig(...)
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*/
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#define EXTRA_PARAM_SIZE (64)
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struct extra_param {
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uint32_t cmd_idx;
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uint8_t module_struct[EXTRA_PARAM_SIZE];
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} __packed;
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struct dip_param {
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uint32_t frame_no;
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uint32_t request_no;
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uint32_t unique_key;
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/*struct timeval expected_end_time;*/
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int32_t user_enum;
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uint8_t num_srz_cfg;
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struct srz_config srz_cfg[MAX_SRZ_CONFIGS];
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uint8_t num_extra_param;
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struct extra_param extra_param[MAX_EXTRA_PARAMS];
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// V3 batch mode added {
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uint64_t next_frame;
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// } V3 batch mode added
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#if MTK_V4L2_SKIP_TILE_SUPPORT
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u32 frameflag;
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#endif
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#if MTK_V4L2_CTRL_META_SUPPORT == 1
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u8 StreamTag;
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#endif
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} __packed;
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#endif
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// } Batch Mode
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struct dip_config_data {
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struct img_addr ref;
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struct img_addr alloc_buf;
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struct img_addr output;
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};
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#define SHARED_BUFFER
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#ifdef SHARED_BUFFER
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#define TIME_MAX (192)
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struct img_ipi_frameparam {
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u8 dmas_enable[IMG_MAX_HW_DMAS][TIME_MAX];
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struct header_desc dmas[IMG_MAX_HW_DMAS];
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struct header_desc tuning_meta;
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struct header_desc ctrl_meta;
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};
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#else
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struct img_ipi_frameparam {
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u32 index;
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u32 frame_no;
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u64 timestamp;
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u8 type; /* enum mdp_stream_type */
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u8 state;
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u8 num_inputs;
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u8 num_outputs;
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u64 drv_data;
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struct img_input inputs[IMG_MAX_HW_INPUTS];
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struct img_output outputs[IMG_MAX_HW_OUTPUTS];
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struct tuning_addr tuning_data;
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struct header_desc dmas[IMG_MAX_HW_DMAS];
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struct header_desc tuning_meta;
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struct header_desc ctrl_meta;
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#if MTK_V4L2_SKIP_TILE_SUPPORT == 0
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struct img_addr subfrm_data;
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#else
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struct dip_config_data subfrm_data;
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#endif
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struct img_sw_addr config_data;
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struct img_sw_addr self_data;
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#if (MTK_V4L2_BATCH_MODE_SUPPORT == 1 || MTK_V4L2_CTL_META_SUPPORT == 1)
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struct dip_param dip_param;
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#endif
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#ifdef MTK_V4L2_BATCH_MODE_SUPPORT
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/* pointer to arrays of img_ipi_frameparam and dip_param. */
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uint64_t framepack_buf_va;
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#endif
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} __packed;
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#endif
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struct img_sw_buffer {
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u64 handle; /* Used by APMCU access */
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u32 scp_addr; /* Used by CM4 access */
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u32 fd; /* Used by User Daemon access */
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u32 offset; /* Used by User Daemon access */
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} __packed;
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struct img_ipi_param {
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u8 usage;
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u8 smvr_mode;
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struct img_sw_buffer frm_param;
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#ifdef MTK_V4L2_BATCH_MODE_SUPPORT
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// V3 batch mode added {
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u8 is_batch_mode;
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u8 num_frames;
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u64 req_addr_va;
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u64 frm_param_offset;
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// } V3 batch mode added
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#endif
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} __packed;
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#ifdef __KERNEL__
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struct img_frameparam {
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struct list_head list_entry;
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struct img_ipi_frameparam frameparam;
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};
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#endif
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/* ISP-MDP generic output information */
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struct img_comp_frame {
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u32 output_disable:1;
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u32 bypass:1;
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u16 in_width;
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u16 in_height;
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u16 out_width;
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u16 out_height;
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struct img_crop crop;
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u16 in_total_width;
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u16 out_total_width;
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} __packed;
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struct img_region {
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s16 left;
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s16 right;
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s16 top;
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s16 bottom;
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} __packed;
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struct img_offset {
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s16 left;
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s16 top;
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u32 left_subpix;
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u32 top_subpix;
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} __packed;
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struct img_comp_subfrm {
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u32 tile_disable:1;
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struct img_region in;
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struct img_region out;
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struct img_offset luma;
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struct img_offset chroma;
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s16 out_vertical; /* Output vertical index */
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s16 out_horizontal; /* Output horizontal index */
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} __packed;
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#define IMG_MAX_SUBFRAMES 14
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struct mdp_rdma_subfrm {
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u32 offset[IMG_MAX_PLANES];
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u32 offset_0_p;
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u32 src;
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u32 clip;
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u32 clip_ofst;
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} __packed;
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struct mdp_rdma_data {
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u32 src_ctrl;
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u32 cmpr_ctrl;
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u32 control;
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u32 iova[IMG_MAX_PLANES];
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u32 iova_end[IMG_MAX_PLANES];
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u32 mf_bkgd;
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u32 mf_bkgd_in_pxl;
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u32 sf_bkgd;
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u32 ufo_dec_y;
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u32 ufo_dec_c;
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u32 transform;
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struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
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} __packed;
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struct mdp_rsz_subfrm {
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u32 control2;
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u32 src;
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u32 clip;
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} __packed;
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struct mdp_rsz_data {
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u32 coeff_step_x;
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u32 coeff_step_y;
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u32 control1;
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u32 control2;
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struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES];
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} __packed;
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struct mdp_wrot_subfrm {
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u32 offset[IMG_MAX_PLANES];
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u32 src;
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u32 clip;
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u32 clip_ofst;
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u32 main_buf;
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} __packed;
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struct mdp_wrot_data {
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u32 iova[IMG_MAX_PLANES];
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u32 control;
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u32 scan_10bit;
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u32 pending_zero;
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u32 stride[IMG_MAX_PLANES];
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u32 mat_ctrl;
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u32 fifo_test;
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u32 filter;
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struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES];
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} __packed;
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struct mdp_wdma_subfrm {
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u32 offset[IMG_MAX_PLANES];
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u32 src;
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u32 clip;
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u32 clip_ofst;
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} __packed;
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struct mdp_wdma_data {
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u32 wdma_cfg;
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u32 iova[IMG_MAX_PLANES];
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u32 w_in_byte;
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u32 uv_stride;
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struct mdp_wdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
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} __packed;
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struct mdp_hdr_subfrm {
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uint32_t hist_left;
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} __packed;
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struct mdp_hdr_data {
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uint32_t rounding;
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struct mdp_hdr_subfrm subfrms[IMG_MAX_SUBFRAMES];
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} __packed;
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#define MAX_READ_REG_NUM 4
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struct dip_data {
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/* subset of ISP_DRIVER_CONFIG_STRUCT */
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// TODO: DIP settings for GCE cmd
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unsigned int cq_basePA;
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//E_ISP_DIP_CQ p2Cq;
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unsigned long DesCqPa;
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unsigned long DesCqVa; // for debugging
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unsigned int *pIspVirRegAddr_pa;
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unsigned int *pIspVirRegAddr_va;
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unsigned long tpipeTablePa;
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unsigned int *tpipeTableVa;
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unsigned int RingBufIdx;
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unsigned int burstCqIdx;
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unsigned int dupCqIdx;
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unsigned int cqIdx; //! index of pass2 cmdQ
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unsigned int frameflag;
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unsigned long smx1iPa;
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unsigned long smx2iPa;
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unsigned long smx3iPa;
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unsigned long smx4iPa;
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//ISP2MDP_STRUCT isp2mdpcfg;
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char *m_pMetLogBuf;
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unsigned int m_MetLogBufSize;
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unsigned int debugRegDump; // dump isp reg from GCE
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//total width of in-dma for frame mode only
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unsigned int framemode_total_in_w;
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//total width od out-dma for frame mode only
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unsigned int framemode_total_out_w;
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unsigned int framemode_h; //height for frame mode only
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unsigned int total_data_size; // add for bandwidth
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unsigned int dmgi_data_size;
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unsigned int depi_data_size;
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unsigned int lcei_data_size;
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unsigned int timgo_data_size;
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unsigned int regCount;
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unsigned int ReadAddrList[MAX_READ_REG_NUM];
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unsigned long imgi_base_addr;
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unsigned long tpipeTablePa_wpe;
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unsigned int *tpipeTableVa_wpe;
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unsigned long tpipeTablePa_mfb;
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unsigned int *tpipeTableVa_mfb;
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unsigned int *dl_tpipeTableVa_wpe;
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unsigned int dupCqIdx_wpe;
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unsigned int regCount_wpe;
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unsigned int ReadAddrList_wpe[MAX_READ_REG_NUM];
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unsigned int *wpecommand;
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unsigned int *mfbcommand;
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// DIP settings for GCE cmd
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unsigned long cqSecHdl;
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unsigned long cqSecSize;
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unsigned long DesCqOft;
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unsigned long DesCqSize;
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unsigned long VirtRegPa;
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unsigned long VirtRegVa;
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unsigned long VirtRegOft;
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unsigned long tpipeTableSecHdl;
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unsigned long tpipeTableSecSize;
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unsigned long tpipeTableOft;
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unsigned long smxSecHdl;
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unsigned long smxSecSize;
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unsigned long smx1iOft;
|
|
unsigned long smx2iOft;
|
|
unsigned long smx3iOft;
|
|
unsigned long smx4iOft;
|
|
unsigned long dip_ctl_yuv_en;
|
|
unsigned long dip_ctl_yuv2_en;
|
|
unsigned long dip_ctl_rgb_en;
|
|
unsigned long dip_ctl_rgb2_en;
|
|
unsigned long dip_ctl_dma_en;
|
|
unsigned long dip_ctl_dma2_en;
|
|
unsigned long dip_ctl_fmt_sel;
|
|
unsigned long dip_ctl_fmt2_sel;
|
|
unsigned long dip_ctl_mux_sel;
|
|
unsigned long dip_ctl_mux2_sel;
|
|
unsigned long dip_ctl_misc_sel;
|
|
unsigned long dip_img2o_base_addr;
|
|
unsigned long dip_img2bo_base_addr;
|
|
unsigned long dip_img3o_base_addr;
|
|
unsigned long dip_img3bo_base_addr;
|
|
unsigned long dip_img3co_base_addr;
|
|
unsigned long dip_feo_base_addr;
|
|
unsigned long dip_dceso_base_addr;
|
|
unsigned long dip_timgo_base_addr;
|
|
unsigned long dip_imgi_base_addr;
|
|
unsigned long dip_imgbi_base_addr;
|
|
unsigned long dip_imgci_base_addr;
|
|
unsigned long dip_vipi_base_addr;
|
|
unsigned long dip_vip2i_base_addr;
|
|
unsigned long dip_vip3i_base_addr;
|
|
unsigned long dip_dmgi_base_addr;
|
|
unsigned long dip_depi_base_addr;
|
|
unsigned long dip_lcei_base_addr;
|
|
unsigned long dip_ufdi_base_addr;
|
|
unsigned long dip_imgbi_base_vaddr;
|
|
unsigned long dip_imgci_base_vaddr;
|
|
unsigned long dip_dmgi_base_vaddr;
|
|
unsigned long dip_depi_base_vaddr;
|
|
unsigned long dip_lcei_base_vaddr;
|
|
unsigned int dip_img2o_size[3];
|
|
unsigned int dip_img3o_size[3];
|
|
unsigned int dip_feo_size[3];
|
|
unsigned int dip_dceso_size[3];
|
|
unsigned int dip_timgo_size[3];
|
|
unsigned int dip_imgi_size[3];
|
|
unsigned int dip_imgbi_size[3];
|
|
unsigned int dip_imgci_size[3];
|
|
unsigned int dip_vipi_size[3];
|
|
unsigned int dip_dmgi_size[3];
|
|
unsigned int dip_depi_size[3];
|
|
unsigned int dip_lcei_size[3];
|
|
unsigned int dip_ufdi_size[3];
|
|
unsigned int dip_secure_tag;
|
|
unsigned int dip_img2o_secure_tag;
|
|
unsigned int dip_img2bo_secure_tag;
|
|
unsigned int dip_img3o_secure_tag;
|
|
unsigned int dip_img3bo_secure_tag;
|
|
unsigned int dip_img3co_secure_tag;
|
|
unsigned int dip_feo_secure_tag;
|
|
unsigned int dip_dceso_secure_tag;
|
|
unsigned int dip_timgo_secure_tag;
|
|
unsigned int dip_imgi_secure_tag;
|
|
unsigned int dip_imgbi_secure_tag;
|
|
unsigned int dip_imgci_secure_tag;
|
|
unsigned int dip_vipi_secure_tag;
|
|
unsigned int dip_vip2i_secure_tag;
|
|
unsigned int dip_vip3i_secure_tag;
|
|
unsigned int dip_dmgi_secure_tag;
|
|
unsigned int dip_depi_secure_tag;
|
|
unsigned int dip_lcei_secure_tag;
|
|
unsigned int dip_ufdi_secure_tag;
|
|
} __packed;
|
|
|
|
struct isp_data {
|
|
u64 dl_flags; /* 1 << (enum mdp_comp_type) */
|
|
u32 smxi_iova[4];
|
|
u32 cq_idx;
|
|
u32 cq_iova;
|
|
u32 tpipe_iova[IMG_MAX_SUBFRAMES];
|
|
u32 mfb_iova[IMG_MAX_SUBFRAMES];
|
|
struct dip_data dip_data; // TODO: declared in a platform header
|
|
} __packed;
|
|
|
|
struct img_compparam {
|
|
u16 type; /* enum mdp_comp_type */
|
|
u16 id; /* enum mdp_comp_id */
|
|
u32 input;
|
|
u32 outputs[IMG_MAX_HW_OUTPUTS];
|
|
u32 num_outputs;
|
|
struct img_comp_frame frame;
|
|
struct img_comp_subfrm subfrms[IMG_MAX_SUBFRAMES];
|
|
u32 num_subfrms;
|
|
union {
|
|
struct mdp_rdma_data rdma;
|
|
struct mdp_rsz_data rsz;
|
|
struct mdp_wrot_data wrot;
|
|
struct mdp_wdma_data wdma;
|
|
struct mdp_hdr_data hdr;
|
|
struct isp_data isp;
|
|
/* struct wpe_data wpe; */
|
|
};
|
|
} __packed;
|
|
|
|
#define IMG_MAX_COMPONENTS 20
|
|
|
|
struct img_mux {
|
|
u32 reg;
|
|
u32 value;
|
|
};
|
|
|
|
struct img_mmsys_ctrl {
|
|
struct img_mux sets[IMG_MAX_COMPONENTS * 2];
|
|
u32 num_sets;
|
|
};
|
|
|
|
struct img_config {
|
|
struct img_compparam components[IMG_MAX_COMPONENTS];
|
|
u32 num_components;
|
|
struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES];
|
|
u32 num_subfrms;
|
|
} __packed;
|
|
|
|
#endif /* __MTK_IMG_IPI_H__ */
|
|
|