204 lines
7 KiB
C
204 lines
7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __GPUFREQ_COMMON_H__
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#define __GPUFREQ_COMMON_H__
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#include <linux/bits.h>
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC) && IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
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#include <mt-plat/mboot_params.h>
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#endif
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/**************************************************
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* Misc Definition
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**************************************************/
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#define GPUOP(_freq, _volt, _vsram, _posdiv, _margin, _power) \
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{ \
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.freq = _freq, \
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.volt = _volt, \
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.vsram = _vsram, \
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.posdiv = _posdiv, \
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.margin = _margin, \
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.power = _power \
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}
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#define ADJOP(_oppidx, _freq, _volt, _vsram) \
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{ \
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.oppidx = _oppidx, \
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.freq = _freq, \
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.volt = _volt, \
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.vsram = _vsram, \
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}
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#define REGOP(_addr, _val) \
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{ \
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.addr = _addr, \
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.val = _val, \
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}
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#ifndef MAX
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#define MAX(x, y) (((x) < (y)) ? (y) : (x))
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#endif
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#ifndef MIN
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#define MIN(x, y) (((x) < (y)) ? (x) : (y))
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#endif
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/**************************************************
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* Shader Present Setting
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**************************************************/
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#define T0C0 (BIT(0))
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#define T1C0 (BIT(1))
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#define T2C0 (BIT(2))
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#define T3C0 (BIT(3))
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#define T0C1 (BIT(4))
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#define T1C1 (BIT(5))
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#define T2C1 (BIT(6))
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#define T3C1 (BIT(7))
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#define T0C2 (BIT(8))
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#define T1C2 (BIT(9))
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#define T2C2 (BIT(10))
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#define T3C2 (BIT(11))
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#define T0C3 (BIT(12))
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#define T1C3 (BIT(13))
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#define T2C3 (BIT(14))
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#define T3C3 (BIT(15))
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#define T4C0 (BIT(16))
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#define T5C0 (BIT(17))
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#define T6C0 (BIT(18))
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#define T7C0 (BIT(19))
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#define T4C1 (BIT(20))
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#define T5C1 (BIT(21))
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#define T6C1 (BIT(22))
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#define T7C1 (BIT(23))
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/**************************************************
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* Enumeration
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**************************************************/
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/**************************************************
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* Structure
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**************************************************/
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/**************************************************
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* Platform Function Declaration
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**************************************************/
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/* Common */
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unsigned int __gpufreq_power_ctrl_enable(void);
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unsigned int __gpufreq_active_idle_ctrl_enable(void);
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unsigned int __gpufreq_get_power_state(void);
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unsigned int __gpufreq_get_dvfs_state(void);
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unsigned int __gpufreq_get_shader_present(void);
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int __gpufreq_power_control(enum gpufreq_power_state power);
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int __gpufreq_active_idle_control(enum gpufreq_power_state power);
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void __gpufreq_dump_infra_status(void);
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int __gpufreq_get_batt_oc_idx(int batt_oc_level);
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int __gpufreq_get_batt_percent_idx(int batt_percent_level);
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int __gpufreq_get_low_batt_idx(int low_batt_level);
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void __gpufreq_set_mfgsys_config(enum gpufreq_config_target target, enum gpufreq_config_value val);
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struct gpufreq_core_mask_info *__gpufreq_get_core_mask_table(void);
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unsigned int __gpufreq_get_core_num(void);
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void __gpufreq_pdca_config(enum gpufreq_power_state power);
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void __gpufreq_update_debug_opp_info(void);
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void __gpufreq_set_shared_status(struct gpufreq_shared_status *shared_status);
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void __gpufreq_update_temperature(unsigned int instant_dvfs);
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int __gpufreq_mssv_commit(unsigned int target, unsigned int val);
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/* GPU */
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unsigned int __gpufreq_get_cur_fgpu(void);
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unsigned int __gpufreq_get_cur_vgpu(void);
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unsigned int __gpufreq_get_cur_pgpu(void);
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unsigned int __gpufreq_get_max_pgpu(void);
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unsigned int __gpufreq_get_min_pgpu(void);
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unsigned int __gpufreq_get_cur_vcore(void);
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int __gpufreq_get_cur_idx_gpu(void);
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int __gpufreq_get_opp_num_gpu(void);
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int __gpufreq_get_signed_opp_num_gpu(void);
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unsigned int __gpufreq_get_fgpu_by_idx(int oppidx);
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unsigned int __gpufreq_get_pgpu_by_idx(int oppidx);
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int __gpufreq_get_idx_by_fgpu(unsigned int freq);
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int __gpufreq_get_idx_by_vgpu(unsigned int volt);
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int __gpufreq_get_idx_by_pgpu(unsigned int power);
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unsigned int __gpufreq_get_lkg_pgpu(unsigned int volt);
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unsigned int __gpufreq_get_dyn_pgpu(unsigned int freq, unsigned int volt);
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int __gpufreq_generic_commit_gpu(int target_oppidx, enum gpufreq_dvfs_state key);
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int __gpufreq_fix_target_oppidx_gpu(int oppidx);
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int __gpufreq_fix_custom_freq_volt_gpu(unsigned int freq, unsigned int volt);
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/* SRAM */
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unsigned int __gpufreq_get_cur_vsram_gpu(void);
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unsigned int __gpufreq_get_cur_vsram_stack(void);
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/* GPUSTACK */
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unsigned int __gpufreq_get_cur_fstack(void);
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unsigned int __gpufreq_get_cur_vstack(void);
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unsigned int __gpufreq_get_cur_pstack(void);
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unsigned int __gpufreq_get_max_pstack(void);
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unsigned int __gpufreq_get_min_pstack(void);
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int __gpufreq_get_cur_idx_stack(void);
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int __gpufreq_get_opp_num_stack(void);
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int __gpufreq_get_signed_opp_num_stack(void);
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unsigned int __gpufreq_get_fstack_by_idx(int oppidx);
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unsigned int __gpufreq_get_pstack_by_idx(int oppidx);
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int __gpufreq_get_idx_by_fstack(unsigned int freq);
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int __gpufreq_get_idx_by_vstack(unsigned int volt);
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int __gpufreq_get_idx_by_pstack(unsigned int power);
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unsigned int __gpufreq_get_lkg_pstack(unsigned int volt);
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unsigned int __gpufreq_get_dyn_pstack(unsigned int freq, unsigned int volt);
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int __gpufreq_generic_commit_stack(int target_oppidx, enum gpufreq_dvfs_state key);
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int __gpufreq_fix_target_oppidx_stack(int oppidx);
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int __gpufreq_fix_custom_freq_volt_stack(unsigned int freq, unsigned int volt);
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/**************************************************
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* Function
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**************************************************/
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static inline void __gpufreq_reset_footprint(void)
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{
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC) && IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
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aee_rr_rec_gpu_dvfs_vgpu(0);
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aee_rr_rec_gpu_dvfs_power_count(0);
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aee_rr_rec_gpu_dvfs_oppidx(GENMASK(7, 0));
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#endif /* CONFIG_MTK_AEE_IPANIC && CONFIG_MTK_AEE_FEATURE */
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}
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static inline void __gpufreq_footprint_power_step(unsigned int step)
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{
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC) && IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
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aee_rr_rec_gpu_dvfs_vgpu(step & GENMASK(7, 0));
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#else
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GPUFREQ_UNREFERENCED(step);
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#endif /* CONFIG_MTK_AEE_IPANIC && CONFIG_MTK_AEE_FEATURE */
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}
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static inline void __gpufreq_footprint_oppidx(int oppidx)
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{
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC) && IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
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aee_rr_rec_gpu_dvfs_oppidx(oppidx);
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#else
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GPUFREQ_UNREFERENCED(oppidx);
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#endif /* CONFIG_MTK_AEE_IPANIC && CONFIG_MTK_AEE_FEATURE */
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}
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static inline void __gpufreq_footprint_power_count(int power_count)
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{
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#if IS_ENABLED(CONFIG_MTK_AEE_IPANIC) && IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
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aee_rr_rec_gpu_dvfs_power_count(power_count);
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#else
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GPUFREQ_UNREFERENCED(power_count);
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#endif /* CONFIG_MTK_AEE_IPANIC && CONFIG_MTK_AEE_FEATURE */
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}
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static inline void __gpufreq_abort(const char *exception_string, ...)
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{
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va_list args;
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int cx = 0;
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char tmp_string[1024];
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va_start(args, exception_string);
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cx = vsnprintf(tmp_string, sizeof(tmp_string), exception_string, args);
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va_end(args);
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GPUFREQ_LOGE("[ABORT]: %s", tmp_string);
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__gpufreq_dump_infra_status();
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BUG_ON(1);
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}
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#endif /* __GPUFREQ_COMMON_H__ */
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