110 lines
2.2 KiB
C
110 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
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*/
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#ifndef __DRV_CLKCHK_MT6886_H
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#define __DRV_CLKCHK_MT6886_H
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enum chk_sys_id {
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top = 0,
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ifrao = 1,
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infracfg = 2,
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apmixed = 3,
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emi_reg = 4,
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emi_bus = 5,
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perao = 6,
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afe = 7,
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impc = 8,
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ufscfg_ao_bus = 9,
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ufsao = 10,
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ufspdn = 11,
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impes = 12,
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impw = 13,
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impe = 14,
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gpu_eb_rpc = 15,
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mfg_ao = 16,
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mfgsc_ao = 17,
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mm = 18,
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img = 19,
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img_sub0_bus = 20,
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img_sub1_bus = 21,
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dip_top_dip1 = 22,
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dip_nr1_dip1 = 23,
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dip_nr2_dip1 = 24,
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wpe1_dip1 = 25,
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wpe2_dip1 = 26,
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wpe3_dip1 = 27,
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traw_dip1 = 28,
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vde2 = 29,
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ven = 30,
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cam_sub0_bus = 31,
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cam_sub2_bus = 32,
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cam_sub1_bus = 33,
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spm = 34,
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vlpcfg = 35,
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vlp_ck = 36,
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scp = 37,
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scp_iic = 38,
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cam_m = 39,
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cam_ra = 40,
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cam_ya = 41,
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cam_rb = 42,
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cam_yb = 43,
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cam_mr = 44,
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ccu = 45,
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dvfsrc_apb = 46,
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mminfra_config = 47,
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mdp = 48,
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cci = 49,
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cpu_ll = 50,
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cpu_bl = 51,
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ptp = 52,
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hwv_wrt = 53,
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hwv = 54,
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hwv_ext = 55,
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chk_sys_num = 56,
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};
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enum chk_pd_id {
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MT6886_CHK_PD_MFG1 = 0,
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MT6886_CHK_PD_MFG2 = 1,
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MT6886_CHK_PD_MFG9 = 2,
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MT6886_CHK_PD_MFG10 = 3,
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MT6886_CHK_PD_MFG11 = 4,
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MT6886_CHK_PD_MFG12 = 5,
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MT6886_CHK_PD_MD1 = 6,
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MT6886_CHK_PD_CONN = 7,
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MT6886_CHK_PD_UFS0 = 8,
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MT6886_CHK_PD_UFS0_PHY = 9,
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MT6886_CHK_PD_AUDIO = 10,
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MT6886_CHK_PD_ADSP_TOP = 11,
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MT6886_CHK_PD_ADSP_INFRA = 12,
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MT6886_CHK_PD_ISP_MAIN = 13,
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MT6886_CHK_PD_ISP_DIP1 = 14,
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MT6886_CHK_PD_ISP_VCORE = 15,
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MT6886_CHK_PD_VDE0 = 16,
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MT6886_CHK_PD_VEN0 = 17,
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MT6886_CHK_PD_CAM_MAIN = 18,
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MT6886_CHK_PD_CAM_MRAW = 19,
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MT6886_CHK_PD_CAM_SUBA = 20,
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MT6886_CHK_PD_CAM_SUBB = 21,
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MT6886_CHK_PD_CAM_VCORE = 22,
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MT6886_CHK_PD_MDP0 = 23,
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MT6886_CHK_PD_DIS0 = 24,
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MT6886_CHK_PD_MM_INFRA = 25,
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MT6886_CHK_PD_MM_PROC = 26,
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MT6886_CHK_PD_APU = 27,
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MT6886_CHK_PD_NUM,
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};
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#ifdef CONFIG_MTK_DVFSRC_HELPER
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extern int get_sw_req_vcore_opp(void);
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#endif
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extern void print_subsys_reg_mt6886(enum chk_sys_id id);
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extern void set_subsys_reg_dump_mt6886(enum chk_sys_id id[]);
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extern void get_subsys_reg_dump_mt6886(void);
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extern u32 get_mt6886_reg_value(u32 id, u32 ofs);
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#endif /* __DRV_CLKCHK_MT6886_H */
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