79 lines
1.6 KiB
C
79 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chuan-Wen Chen <chuan-wen.chen@mediatek.com>
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*/
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#ifndef __DRV_CLKCHK_MT6835_H
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#define __DRV_CLKCHK_MT6835_H
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enum chk_sys_id {
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top = 0,
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ifrao = 1,
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infracfg = 2,
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apmixed = 3,
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nemi_reg = 4,
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dpmaif = 5,
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emi_bus = 6,
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perao = 7,
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afe = 8,
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impc = 9,
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ufsao = 10,
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ufspdn = 11,
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impws = 12,
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imps = 13,
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impen = 14,
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mfgcfg = 15,
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mm = 16,
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imgsys1 = 17,
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vde2 = 18,
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ven1 = 19,
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spm = 20,
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vlpcfg = 21,
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vlp_ck = 22,
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scp_iic = 23,
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cam_m = 24,
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cam_sub1_bus = 25,
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cam_sub0_bus = 26,
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cam_ra = 27,
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cam_rb = 28,
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ipe = 29,
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dvfsrc_apb = 30,
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sramrc_apb = 31,
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mminfra_config = 32,
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mdp = 33,
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chk_sys_num = 34,
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};
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enum chk_pd_id {
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MT6835_CHK_PD_MD1 = 0,
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MT6835_CHK_PD_CONN = 1,
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MT6835_CHK_PD_UFS0 = 2,
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MT6835_CHK_PD_AUDIO = 3,
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MT6835_CHK_PD_ISP_DIP1 = 4,
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MT6835_CHK_PD_ISP_IPE = 5,
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MT6835_CHK_PD_VDE0 = 6,
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MT6835_CHK_PD_VEN0 = 7,
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MT6835_CHK_PD_CAM_MAIN = 8,
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MT6835_CHK_PD_CAM_SUBA = 9,
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MT6835_CHK_PD_CAM_SUBB = 10,
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MT6835_CHK_PD_DIS0 = 11,
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MT6835_CHK_PD_MM_INFRA = 12,
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MT6835_CHK_PD_MM_PROC = 13,
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MT6835_CHK_PD_MFG0 = 14,
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MT6835_CHK_PD_MFG1 = 15,
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MT6835_CHK_PD_MFG2 = 16,
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MT6835_CHK_PD_MFG3 = 17,
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MT6835_CHK_PD_APU = 18,
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MT6835_CHK_PD_NUM,
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};
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#ifdef CONFIG_MTK_DVFSRC_HELPER
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extern int get_sw_req_vcore_opp(void);
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#endif
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extern void print_subsys_reg_mt6835(enum chk_sys_id id);
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extern void set_subsys_reg_dump_mt6835(enum chk_sys_id id[]);
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extern void get_subsys_reg_dump_mt6835(void);
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extern u32 get_mt6835_reg_value(u32 id, u32 ofs);
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#endif /* __DRV_CLKCHK_MT6835_H */
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