70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2020 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs apu_vcore_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APU_VCORE(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &apu_vcore_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate apu_vcore_clks[] = {
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GATE_APU_VCORE(CLK_APU_VCORE_AHB, "apu_vcore_ahb", "ipu_if_sel", 0),
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GATE_APU_VCORE(CLK_APU_VCORE_AXI, "apu_vcore_axi", "ipu_if_sel", 1),
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GATE_APU_VCORE(CLK_APU_VCORE_ADL, "apu_vcore_adl", "ipu_if_sel", 2),
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GATE_APU_VCORE(CLK_APU_VCORE_QOS, "apu_vcore_qos", "ipu_if_sel", 3),
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};
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static int clk_mt8192_apu_vcore_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_APU_VCORE_NR_CLK);
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mtk_clk_register_gates(node, apu_vcore_clks, ARRAY_SIZE(apu_vcore_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id of_match_clk_mt8192_apu_vcore[] = {
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{ .compatible = "mediatek,mt8192-apu_vcore", },
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{}
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};
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static struct platform_driver clk_mt8192_apu_vcore_drv = {
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.probe = clk_mt8192_apu_vcore_probe,
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.driver = {
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.name = "clk-mt8192-apu_vcore",
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.of_match_table = of_match_clk_mt8192_apu_vcore,
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},
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};
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static int __init clk_mt8192_apu_vcore_init(void)
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{
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return platform_driver_register(&clk_mt8192_apu_vcore_drv);
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}
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static void __exit clk_mt8192_apu_vcore_exit(void)
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{
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platform_driver_unregister(&clk_mt8192_apu_vcore_drv);
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}
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arch_initcall(clk_mt8192_apu_vcore_init);
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module_exit(clk_mt8192_apu_vcore_exit);
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MODULE_LICENSE("GPL");
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