294 lines
8.6 KiB
C
294 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6985-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs mdp10_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mdp11_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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#define GATE_MDP10(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp10_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MDP11(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp11_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mdp1_clks[] = {
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/* MDP10 */
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GATE_MDP10(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0",
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"mdp1_ck"/* parent */, 0),
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GATE_MDP10(CLK_MDP1_APB_BUS, "mdp1_apb_bus",
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"mdp1_ck"/* parent */, 1),
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GATE_MDP10(CLK_MDP1_SMI0, "mdp1_smi0",
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"mdp1_ck"/* parent */, 2),
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GATE_MDP10(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0",
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"mdp1_ck"/* parent */, 3),
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GATE_MDP10(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2",
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"mdp1_ck"/* parent */, 4),
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GATE_MDP10(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0",
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"mdp1_ck"/* parent */, 5),
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GATE_MDP10(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0",
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"mdp1_ck"/* parent */, 6),
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GATE_MDP10(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0",
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"mdp1_ck"/* parent */, 7),
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GATE_MDP10(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0",
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"mdp1_ck"/* parent */, 8),
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GATE_MDP10(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0",
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"mdp1_ck"/* parent */, 9),
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GATE_MDP10(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0",
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"mdp1_ck"/* parent */, 10),
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GATE_MDP10(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0",
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"mdp1_ck"/* parent */, 11),
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GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0",
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"mdp1_ck"/* parent */, 12),
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GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1",
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"mdp1_ck"/* parent */, 13),
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GATE_MDP10(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1",
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"mdp1_ck"/* parent */, 15),
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GATE_MDP10(CLK_MDP1_MDP_RDMA3, "mdp1_mdp_rdma3",
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"mdp1_ck"/* parent */, 16),
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GATE_MDP10(CLK_MDP1_MDP_HDR1, "mdp1_mdp_hdr1",
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"mdp1_ck"/* parent */, 17),
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GATE_MDP10(CLK_MDP1_MDP_AAL1, "mdp1_mdp_aal1",
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"mdp1_ck"/* parent */, 18),
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GATE_MDP10(CLK_MDP1_MDP_RSZ1, "mdp1_mdp_rsz1",
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"mdp1_ck"/* parent */, 19),
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GATE_MDP10(CLK_MDP1_MDP_TDSHP1, "mdp1_mdp_tdshp1",
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"mdp1_ck"/* parent */, 20),
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GATE_MDP10(CLK_MDP1_MDP_COLOR1, "mdp1_mdp_color1",
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"mdp1_ck"/* parent */, 21),
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GATE_MDP10(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1",
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"mdp1_ck"/* parent */, 22),
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GATE_MDP10(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2",
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"mdp1_ck"/* parent */, 24),
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GATE_MDP10(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2",
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"mdp1_ck"/* parent */, 25),
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GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0",
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"mdp1_ck"/* parent */, 26),
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GATE_MDP10(CLK_MDP1_MDP_RSZ3, "mdp1_mdp_rsz3",
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"mdp1_ck"/* parent */, 28),
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GATE_MDP10(CLK_MDP1_MDP_WROT3, "mdp1_mdp_wrot3",
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"mdp1_ck"/* parent */, 29),
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GATE_MDP10(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1",
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"mdp1_ck"/* parent */, 30),
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GATE_MDP10(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2",
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"mdp1_ck"/* parent */, 31),
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/* MDP11 */
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GATE_MDP11(CLK_MDP1_MDP_DLI_ASYNC3, "mdp1_mdp_dli_async3",
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"mdp1_ck"/* parent */, 0),
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GATE_MDP11(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2",
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"mdp1_ck"/* parent */, 1),
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GATE_MDP11(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3",
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"mdp1_ck"/* parent */, 2),
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GATE_MDP11(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0",
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"mdp1_ck"/* parent */, 3),
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GATE_MDP11(CLK_MDP1_MDP_BIRSZ1, "mdp1_mdp_birsz1",
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"mdp1_ck"/* parent */, 4),
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GATE_MDP11(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0",
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"mdp1_ck"/* parent */, 5),
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GATE_MDP11(CLK_MDP1_IMG_DL_ASYNC1, "mdp1_img_dl_async1",
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"mdp1_ck"/* parent */, 6),
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GATE_MDP11(CLK_MDP1_HRE_TOP_MDPSYS, "mdp1_hre_mdpsys",
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"mdp1_ck"/* parent */, 7),
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};
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static const struct mtk_clk_desc mdp1_mcd = {
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.clks = mdp1_clks,
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.num_clks = CLK_MDP1_NR_CLK,
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};
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static const struct mtk_gate_regs mdp0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mdp1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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#define GATE_MDP0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MDP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mdp_clks[] = {
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/* MDP0 */
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GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0",
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"mdp0_ck"/* parent */, 0),
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GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus",
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"mdp0_ck"/* parent */, 1),
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GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0",
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"mdp0_ck"/* parent */, 2),
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GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0",
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"mdp0_ck"/* parent */, 3),
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GATE_MDP0(CLK_MDP_RDMA2, "mdp_rdma2",
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"mdp0_ck"/* parent */, 4),
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GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0",
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"mdp0_ck"/* parent */, 5),
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GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0",
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"mdp0_ck"/* parent */, 6),
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GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0",
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"mdp0_ck"/* parent */, 7),
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GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0",
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"mdp0_ck"/* parent */, 8),
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GATE_MDP0(CLK_MDP_COLOR0, "mdp_color0",
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"mdp0_ck"/* parent */, 9),
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GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0",
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"mdp0_ck"/* parent */, 10),
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GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0",
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"mdp0_ck"/* parent */, 11),
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GATE_MDP0(CLK_MDP_DLI_ASYNC0, "mdp_dli_async0",
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"mdp0_ck"/* parent */, 12),
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GATE_MDP0(CLK_MDP_DLI_ASYNC1, "mdp_dli_async1",
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"mdp0_ck"/* parent */, 13),
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GATE_MDP0(CLK_MDP_RDMA1, "mdp_rdma1",
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"mdp0_ck"/* parent */, 15),
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GATE_MDP0(CLK_MDP_RDMA3, "mdp_rdma3",
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"mdp0_ck"/* parent */, 16),
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GATE_MDP0(CLK_MDP_HDR1, "mdp_hdr1",
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"mdp0_ck"/* parent */, 17),
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GATE_MDP0(CLK_MDP_AAL1, "mdp_aal1",
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"mdp0_ck"/* parent */, 18),
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GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1",
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"mdp0_ck"/* parent */, 19),
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GATE_MDP0(CLK_MDP_TDSHP1, "mdp_tdshp1",
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"mdp0_ck"/* parent */, 20),
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GATE_MDP0(CLK_MDP_COLOR1, "mdp_color1",
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"mdp0_ck"/* parent */, 21),
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GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1",
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"mdp0_ck"/* parent */, 22),
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GATE_MDP0(CLK_MDP_RSZ2, "mdp_rsz2",
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"mdp0_ck"/* parent */, 24),
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GATE_MDP0(CLK_MDP_WROT2, "mdp_wrot2",
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"mdp0_ck"/* parent */, 25),
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GATE_MDP0(CLK_MDP_DLO_ASYNC0, "mdp_dlo_async0",
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"mdp0_ck"/* parent */, 26),
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GATE_MDP0(CLK_MDP_RSZ3, "mdp_rsz3",
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"mdp0_ck"/* parent */, 28),
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GATE_MDP0(CLK_MDP_WROT3, "mdp_wrot3",
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"mdp0_ck"/* parent */, 29),
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GATE_MDP0(CLK_MDP_DLO_ASYNC1, "mdp_dlo_async1",
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"mdp0_ck"/* parent */, 30),
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GATE_MDP0(CLK_MDP_DLI_ASYNC2, "mdp_dli_async2",
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"mdp0_ck"/* parent */, 31),
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/* MDP1 */
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GATE_MDP1(CLK_MDP_DLI_ASYNC3, "mdp_dli_async3",
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"mdp0_ck"/* parent */, 0),
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GATE_MDP1(CLK_MDP_DLO_ASYNC2, "mdp_dlo_async2",
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"mdp0_ck"/* parent */, 1),
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GATE_MDP1(CLK_MDP_DLO_ASYNC3, "mdp_dlo_async3",
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"mdp0_ck"/* parent */, 2),
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GATE_MDP1(CLK_MDP_BIRSZ0, "mdp_birsz0",
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"mdp0_ck"/* parent */, 3),
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GATE_MDP1(CLK_MDP_BIRSZ1, "mdp_birsz1",
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"mdp0_ck"/* parent */, 4),
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GATE_MDP1(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0",
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"mdp0_ck"/* parent */, 5),
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GATE_MDP1(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1",
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"mdp0_ck"/* parent */, 6),
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GATE_MDP1(CLK_MDP_HRE_TOP_MDPSYS, "mdp_hre_mdpsys",
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"mdp0_ck"/* parent */, 7),
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};
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static const struct mtk_clk_desc mdp_mcd = {
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.clks = mdp_clks,
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.num_clks = CLK_MDP_NR_CLK,
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};
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static const struct of_device_id of_match_clk_mt6985_mdpsys[] = {
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{
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.compatible = "mediatek,mt6985-mdpsys1",
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.data = &mdp1_mcd,
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}, {
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.compatible = "mediatek,mt6985-mdpsys",
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.data = &mdp_mcd,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6985_mdpsys_grp_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init begin\n", __func__, pdev->name);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init end\n", __func__, pdev->name);
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#endif
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return r;
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}
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static struct platform_driver clk_mt6985_mdpsys_drv = {
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.probe = clk_mt6985_mdpsys_grp_probe,
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.driver = {
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.name = "clk-mt6985-mdpsys",
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.of_match_table = of_match_clk_mt6985_mdpsys,
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},
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};
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module_platform_driver(clk_mt6985_mdpsys_drv);
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MODULE_LICENSE("GPL");
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