409 lines
10 KiB
C
409 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6886-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs impc_cg_regs = {
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.set_ofs = 0xE08,
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.clr_ofs = 0xE04,
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.sta_ofs = 0xE00,
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};
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#define GATE_IMPC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impc_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impc_clks[] = {
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GATE_IMPC(CLK_IMPC_I2C5, "impc_i2c5",
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"i2c_pseudo_ck"/* parent */, 0),
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GATE_IMPC(CLK_IMPC_I2C6, "impc_i2c6",
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"i2c_pseudo_ck"/* parent */, 1),
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GATE_IMPC(CLK_IMPC_I2C10, "impc_i2c10",
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"i2c_pseudo_ck"/* parent */, 2),
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GATE_IMPC(CLK_IMPC_I2C11, "impc_i2c11",
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"i2c_pseudo_ck"/* parent */, 3),
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};
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static const struct mtk_clk_desc impc_mcd = {
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.clks = impc_clks,
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.num_clks = CLK_IMPC_NR_CLK,
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};
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static const struct mtk_gate_regs impe_cg_regs = {
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.set_ofs = 0xE08,
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.clr_ofs = 0xE04,
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.sta_ofs = 0xE00,
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};
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#define GATE_IMPE(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impe_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impe_clks[] = {
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GATE_IMPE(CLK_IMPE_I2C3, "impe_i2c3",
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"i2c_pseudo_ck"/* parent */, 0),
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GATE_IMPE(CLK_IMPE_I2C7, "impe_i2c7",
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"i2c_pseudo_ck"/* parent */, 1),
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GATE_IMPE(CLK_IMPE_I2C8, "impe_i2c8",
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"i2c_pseudo_ck"/* parent */, 2),
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};
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static const struct mtk_clk_desc impe_mcd = {
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.clks = impe_clks,
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.num_clks = CLK_IMPE_NR_CLK,
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};
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static const struct mtk_gate_regs impes_cg_regs = {
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.set_ofs = 0xE08,
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.clr_ofs = 0xE04,
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.sta_ofs = 0xE00,
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};
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#define GATE_IMPES(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impes_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impes_clks[] = {
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GATE_IMPES(CLK_IMPES_I2C2, "impes_i2c2",
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"i2c_pseudo_ck"/* parent */, 0),
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GATE_IMPES(CLK_IMPES_I2C4, "impes_i2c4",
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"i2c_pseudo_ck"/* parent */, 1),
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GATE_IMPES(CLK_IMPES_I2C9, "impes_i2c9",
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"i2c_pseudo_ck"/* parent */, 2),
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};
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static const struct mtk_clk_desc impes_mcd = {
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.clks = impes_clks,
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.num_clks = CLK_IMPES_NR_CLK,
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};
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static const struct mtk_gate_regs impw_cg_regs = {
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.set_ofs = 0xE08,
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.clr_ofs = 0xE04,
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.sta_ofs = 0xE00,
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};
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#define GATE_IMPW(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impw_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impw_clks[] = {
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GATE_IMPW(CLK_IMPW_I2C0, "impw_i2c0",
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"i2c_pseudo_ck"/* parent */, 0),
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GATE_IMPW(CLK_IMPW_I2C1, "impw_i2c1",
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"i2c_pseudo_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc impw_mcd = {
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.clks = impw_clks,
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.num_clks = CLK_IMPW_NR_CLK,
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};
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static const struct mtk_gate_regs perao0_cg_regs = {
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.set_ofs = 0x28,
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.clr_ofs = 0x2C,
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.sta_ofs = 0x10,
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};
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static const struct mtk_gate_regs perao1_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x34,
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.sta_ofs = 0x14,
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};
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static const struct mtk_gate_regs perao2_cg_regs = {
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.set_ofs = 0x38,
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.clr_ofs = 0x3C,
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.sta_ofs = 0x18,
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};
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#define GATE_PERAO0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &perao0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_PERAO1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &perao1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_PERAO2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &perao2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate perao_clks[] = {
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/* PERAO0 */
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GATE_PERAO0(CLK_PERAO_UART0, "perao_uart0",
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"uart_ck"/* parent */, 0),
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GATE_PERAO0(CLK_PERAO_UART1, "perao_uart1",
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"uart_ck"/* parent */, 1),
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GATE_PERAO0(CLK_PERAO_PWM_H, "perao_pwm_h",
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"peri_axi_ck"/* parent */, 4),
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GATE_PERAO0(CLK_PERAO_PWM_B, "perao_pwm_b",
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"pwm_ck"/* parent */, 5),
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GATE_PERAO0(CLK_PERAO_PWM_FB1, "perao_pwm_fb1",
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"pwm_ck"/* parent */, 6),
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GATE_PERAO0(CLK_PERAO_PWM_FB2, "perao_pwm_fb2",
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"pwm_ck"/* parent */, 7),
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GATE_PERAO0(CLK_PERAO_PWM_FB3, "perao_pwm_fb3",
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"pwm_ck"/* parent */, 8),
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GATE_PERAO0(CLK_PERAO_PWM_FB4, "perao_pwm_fb4",
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"pwm_ck"/* parent */, 9),
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GATE_PERAO0(CLK_PERAO_BTIF_B, "perao_btif_b",
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"pwm_ck"/* parent */, 10),
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GATE_PERAO0(CLK_PERAO_DISP_PWM0, "perao_disp_pwm0",
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"disp_pwm_ck"/* parent */, 11),
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GATE_PERAO0(CLK_PERAO_SPI0_B, "perao_spi0_b",
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"spi_ck"/* parent */, 12),
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GATE_PERAO0(CLK_PERAO_SPI1_B, "perao_spi1_b",
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"spi_ck"/* parent */, 13),
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GATE_PERAO0(CLK_PERAO_SPI2_B, "perao_spi2_b",
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"spi_ck"/* parent */, 14),
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GATE_PERAO0(CLK_PERAO_SPI3_B, "perao_spi3_b",
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"spi_ck"/* parent */, 15),
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GATE_PERAO0(CLK_PERAO_SPI4_B, "perao_spi4_b",
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"spi_ck"/* parent */, 16),
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GATE_PERAO0(CLK_PERAO_SPI5_B, "perao_spi5_b",
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"spi_ck"/* parent */, 17),
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GATE_PERAO0(CLK_PERAO_SPI6_B, "perao_spi6_b",
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"spi_ck"/* parent */, 18),
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GATE_PERAO0(CLK_PERAO_SPI7_B, "perao_spi7_b",
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"spi_ck"/* parent */, 19),
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GATE_PERAO0(CLK_PERAO_APDMA, "perao_apdma",
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"peri_axi_ck"/* parent */, 29),
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/* PERAO1 */
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GATE_PERAO1(CLK_PERAO_USB_SYS, "perao_usb_sys",
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"usb_ck"/* parent */, 2),
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GATE_PERAO1(CLK_PERAO_USB_XHCI, "perao_usb_xhci",
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"ssusb_xhci_ck"/* parent */, 3),
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GATE_PERAO1(CLK_PERAO_USB_BUS, "perao_usb_bus",
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"peri_axi_ck"/* parent */, 5),
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GATE_PERAO1(CLK_PERAO_MSDC1, "perao_msdc1",
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"msdc30_1_ck"/* parent */, 6),
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GATE_PERAO1(CLK_PERAO_MSDC1_H, "perao_msdc1_h",
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"peri_axi_ck"/* parent */, 7),
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/* PERAO2 */
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GATE_PERAO2(CLK_PERAO_AUDIO_SLV_CKP, "perao_audio_slv_ckp",
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"peri_axi_ck"/* parent */, 0),
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GATE_PERAO2(CLK_PERAO_AUDIO_MST_CKP, "perao_audio_mst_ckp",
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"peri_axi_ck"/* parent */, 1),
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GATE_PERAO2(CLK_PERAO_INTBUS_CKP, "perao_intbus_ckp",
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"aud_intbus_ck"/* parent */, 2),
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GATE_PERAO2(CLK_PERAO_AUDIO_MST_IDLE_EN, "perao_aud_mst_idl_en",
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"peri_axi_ck"/* parent */, 3),
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};
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static const struct mtk_clk_desc perao_mcd = {
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.clks = perao_clks,
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.num_clks = CLK_PERAO_NR_CLK,
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};
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static const struct mtk_gate_regs scp_iic_cg_regs = {
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.set_ofs = 0xE18,
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.clr_ofs = 0xE14,
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.sta_ofs = 0xE10,
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};
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#define GATE_SCP_IIC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &scp_iic_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate scp_iic_clks[] = {
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GATE_SCP_IIC(CLK_SCP_IIC_I2C0, "scp_iic_i2c0",
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"ulposc_ck"/* parent */, 0),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C1, "scp_iic_i2c1",
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"ulposc_ck"/* parent */, 1),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C2, "scp_iic_i2c2",
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"ulposc_ck"/* parent */, 2),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C3, "scp_iic_i2c3",
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"ulposc_ck"/* parent */, 3),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C4, "scp_iic_i2c4",
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"ulposc_ck"/* parent */, 4),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C5, "scp_iic_i2c5",
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"ulposc_ck"/* parent */, 5),
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GATE_SCP_IIC(CLK_SCP_IIC_I2C6, "scp_iic_i2c6",
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"ulposc_ck"/* parent */, 6),
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};
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static const struct mtk_clk_desc scp_iic_mcd = {
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.clks = scp_iic_clks,
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.num_clks = CLK_SCP_IIC_NR_CLK,
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};
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static const struct mtk_gate_regs ufsao_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xC,
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.sta_ofs = 0x4,
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};
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#define GATE_UFSAO(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ufsao_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate ufsao_clks[] = {
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GATE_UFSAO(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym",
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"f26m_ck"/* parent */, 0),
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GATE_UFSAO(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0",
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"f26m_ck"/* parent */, 1),
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GATE_UFSAO(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1",
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"f26m_ck"/* parent */, 2),
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GATE_UFSAO(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys",
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"ufs_ck"/* parent */, 3),
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GATE_UFSAO(CLK_UFSAO_UNIPRO_PHY_SAP, "ufsao_unipro_phy_sap",
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"f26m_ck"/* parent */, 8),
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};
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static const struct mtk_clk_desc ufsao_mcd = {
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.clks = ufsao_clks,
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.num_clks = CLK_UFSAO_NR_CLK,
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};
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static const struct mtk_gate_regs ufspdn_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xC,
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.sta_ofs = 0x4,
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};
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#define GATE_UFSPDN(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ufspdn_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate ufspdn_clks[] = {
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GATE_UFSPDN(CLK_UFSPDN_UFSHCI_UFS, "ufspdn_ufshci_ufs",
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"ufs_ck"/* parent */, 0),
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GATE_UFSPDN(CLK_UFSPDN_UFSHCI_AES, "ufspdn_ufshci_aes",
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"aes_ufsfde_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc ufspdn_mcd = {
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.clks = ufspdn_clks,
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.num_clks = CLK_UFSPDN_NR_CLK,
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};
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static const struct of_device_id of_match_clk_mt6886_peri[] = {
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{
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.compatible = "mediatek,mt6886-imp_iic_wrap_c",
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.data = &impc_mcd,
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}, {
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.compatible = "mediatek,mt6886-imp_iic_wrap_e",
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.data = &impe_mcd,
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}, {
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.compatible = "mediatek,mt6886-imp_iic_wrap_es",
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.data = &impes_mcd,
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}, {
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.compatible = "mediatek,mt6886-imp_iic_wrap_w",
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.data = &impw_mcd,
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}, {
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.compatible = "mediatek,mt6886-pericfg_ao",
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.data = &perao_mcd,
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}, {
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.compatible = "mediatek,mt6886-scp_iic",
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.data = &scp_iic_mcd,
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}, {
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.compatible = "mediatek,mt6886-ufscfg_ao",
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.data = &ufsao_mcd,
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}, {
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.compatible = "mediatek,mt6886-ufscfg_pdn",
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.data = &ufspdn_mcd,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6886_peri_grp_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init begin\n", __func__, pdev->name);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init end\n", __func__, pdev->name);
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#endif
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return r;
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}
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static struct platform_driver clk_mt6886_peri_drv = {
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.probe = clk_mt6886_peri_grp_probe,
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.driver = {
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.name = "clk-mt6886-peri",
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.of_match_table = of_match_clk_mt6886_peri,
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},
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};
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module_platform_driver(clk_mt6886_peri_drv);
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MODULE_LICENSE("GPL");
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