242 lines
6.5 KiB
C
242 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6886-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs mm0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mm1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs mm2_cg_regs = {
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.set_ofs = 0x1A4,
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.clr_ofs = 0x1A8,
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.sta_ofs = 0x1A0,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MM2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mm_clks[] = {
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/* MM0 */
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GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0",
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"disp0_ck"/* parent */, 0),
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
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"disp0_ck"/* parent */, 1),
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GATE_MM0(CLK_MM_DISP_MERGE0, "mm_disp_merge0",
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"disp0_ck"/* parent */, 2),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0",
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"disp0_ck"/* parent */, 3),
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GATE_MM0(CLK_MM_INLINEROT0, "mm_inlinerot0",
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"disp0_ck"/* parent */, 4),
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GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
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"disp0_ck"/* parent */, 5),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1",
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"disp0_ck"/* parent */, 6),
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GATE_MM0(CLK_MM_DISP_OVL0_2L_NW, "mm_disp_ovl0_2l_nw",
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"disp0_ck"/* parent */, 8),
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GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
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"disp0_ck"/* parent */, 9),
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GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1",
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"disp0_ck"/* parent */, 10),
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GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0",
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"disp0_ck"/* parent */, 17),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0",
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"disp0_ck"/* parent */, 18),
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GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
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"disp0_ck"/* parent */, 19),
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GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1",
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"disp0_ck"/* parent */, 20),
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GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0",
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"disp0_ck"/* parent */, 21),
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GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
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"disp0_ck"/* parent */, 22),
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GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0",
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"disp0_ck"/* parent */, 23),
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GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
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"disp0_ck"/* parent */, 24),
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GATE_MM0(CLK_MM_DISP_CM0, "mm_disp_cm0",
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"disp0_ck"/* parent */, 25),
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GATE_MM0(CLK_MM_DISP_SPR0, "mm_disp_spr0",
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"disp0_ck"/* parent */, 26),
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GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0",
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"disp0_ck"/* parent */, 27),
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GATE_MM0(CLK_MM_FMM_DISP_DSI0, "mm_fmm_clk0",
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"disp0_ck"/* parent */, 29),
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GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0",
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"disp0_ck"/* parent */, 30),
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GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1",
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"disp0_ck"/* parent */, 31),
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/* MM1 */
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GATE_MM1(CLK_MM_APB_BUS, "mm_apb_bus",
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"disp0_ck"/* parent */, 1),
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GATE_MM1(CLK_MM_DISP_C3D0, "mm_disp_c3d0",
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"disp0_ck"/* parent */, 3),
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GATE_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0",
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"disp0_ck"/* parent */, 4),
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GATE_MM1(CLK_MM_DISP_CHIST0, "mm_disp_chist0",
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"disp0_ck"/* parent */, 6),
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GATE_MM1(CLK_MM_DISP_CHIST1, "mm_disp_chist1",
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"disp0_ck"/* parent */, 7),
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GATE_MM1(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l",
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"disp0_ck"/* parent */, 8),
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GATE_MM1(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3",
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"disp0_ck"/* parent */, 9),
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GATE_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3",
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"disp0_ck"/* parent */, 10),
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GATE_MM1(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l",
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"disp0_ck"/* parent */, 12),
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GATE_MM1(CLK_MM_DISP_OVL1_2L_NW, "mm_disp_ovl1_2l_nw",
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"disp0_ck"/* parent */, 16),
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GATE_MM1(CLK_MM_SMI_COMMON, "mm_smi_common",
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"disp0_ck"/* parent */, 20),
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/* MM2 */
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GATE_MM2(CLK_MM_DISP_DSI0, "mm_clk0",
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"f26m_ck"/* parent */, 0),
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GATE_MM2(CLK_MM_SIG_EMI, "mm_sig_emi",
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"f26m_ck"/* parent */, 11),
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};
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static const struct mtk_clk_desc mm_mcd = {
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.clks = mm_clks,
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.num_clks = CLK_MM_NR_CLK,
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};
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static const struct mtk_gate_regs mminfra_config0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mminfra_config1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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#define GATE_MMINFRA_CONFIG0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mminfra_config0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MMINFRA_CONFIG1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mminfra_config1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mminfra_config_clks[] = {
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/* MMINFRA_CONFIG0 */
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GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, "mminfra_gce_d",
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"mminfra_ck"/* parent */, 0),
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GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, "mminfra_gce_m",
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"mminfra_ck"/* parent */, 1),
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/* MMINFRA_CONFIG1 */
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GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, "mminfra_gce_26m",
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"mminfra_ck"/* parent */, 17),
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};
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static const struct mtk_clk_desc mminfra_config_mcd = {
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.clks = mminfra_config_clks,
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.num_clks = CLK_MMINFRA_CONFIG_NR_CLK,
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};
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static const struct of_device_id of_match_clk_mt6886_mmsys[] = {
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{
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.compatible = "mediatek,mt6886-mmsys0",
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.data = &mm_mcd,
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}, {
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.compatible = "mediatek,mt6886-mminfra_config",
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.data = &mminfra_config_mcd,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6886_mmsys_grp_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init begin\n", __func__, pdev->name);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init end\n", __func__, pdev->name);
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#endif
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return r;
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}
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static struct platform_driver clk_mt6886_mmsys_drv = {
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.probe = clk_mt6886_mmsys_grp_probe,
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.driver = {
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.name = "clk-mt6886-mmsys",
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.of_match_table = of_match_clk_mt6886_mmsys,
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},
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};
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module_platform_driver(clk_mt6886_mmsys_drv);
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MODULE_LICENSE("GPL");
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