343 lines
8.3 KiB
C
343 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6886-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs dip_nr1_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_DIP_NR1_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &dip_nr1_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate dip_nr1_dip1_clks[] = {
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GATE_DIP_NR1_DIP1(CLK_DIP_NR1_DIP1_LARB, "dip_nr1_dip1_larb",
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"img1_ck"/* parent */, 0),
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GATE_DIP_NR1_DIP1(CLK_DIP_NR1_DIP1_DIP_NR1, "dip_nr1_dip1_dip_nr1",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc dip_nr1_dip1_mcd = {
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.clks = dip_nr1_dip1_clks,
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.num_clks = CLK_DIP_NR1_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs dip_nr2_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_DIP_NR2_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &dip_nr2_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate dip_nr2_dip1_clks[] = {
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GATE_DIP_NR2_DIP1(CLK_DIP_NR2_DIP1_LARB15, "dip_nr2_dip1_larb15",
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"img1_ck"/* parent */, 0),
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GATE_DIP_NR2_DIP1(CLK_DIP_NR2_DIP1_DIP_NR, "dip_nr2_dip1_dip_nr",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc dip_nr2_dip1_mcd = {
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.clks = dip_nr2_dip1_clks,
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.num_clks = CLK_DIP_NR2_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs dip_top_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_DIP_TOP_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &dip_top_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate dip_top_dip1_clks[] = {
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GATE_DIP_TOP_DIP1(CLK_DIP_TOP_DIP1_LARB10, "dip_dip1_larb10",
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"img1_ck"/* parent */, 0),
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GATE_DIP_TOP_DIP1(CLK_DIP_TOP_DIP1_DIP_TOP, "dip_dip1_dip_top",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc dip_top_dip1_mcd = {
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.clks = dip_top_dip1_clks,
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.num_clks = CLK_DIP_TOP_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs img0_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs img1_cg_regs = {
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.set_ofs = 0x54,
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.clr_ofs = 0x58,
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.sta_ofs = 0x50,
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};
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#define GATE_IMG0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &img0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_IMG1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &img1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate img_clks[] = {
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/* IMG0 */
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GATE_IMG0(CLK_IMG_LARB9, "img_larb9",
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"img1_ck"/* parent */, 0),
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GATE_IMG0(CLK_IMG_TRAW0, "img_traw0",
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"img1_ck"/* parent */, 1),
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GATE_IMG0(CLK_IMG_TRAW1, "img_traw1",
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"img1_ck"/* parent */, 2),
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GATE_IMG0(CLK_IMG_VCORE_GALS, "img_vcore_gals",
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"img1_ck"/* parent */, 3),
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GATE_IMG0(CLK_IMG_DIP0, "img_dip0",
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"img1_ck"/* parent */, 8),
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GATE_IMG0(CLK_IMG_WPE0, "img_wpe0",
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"img1_ck"/* parent */, 9),
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GATE_IMG0(CLK_IMG_IPE, "img_ipe",
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"img1_ck"/* parent */, 10),
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GATE_IMG0(CLK_IMG_WPE1, "img_wpe1",
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"img1_ck"/* parent */, 12),
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GATE_IMG0(CLK_IMG_WPE2, "img_wpe2",
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"img1_ck"/* parent */, 13),
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GATE_IMG0(CLK_IMG_AVS, "img_avs",
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"imgavs_ck"/* parent */, 17),
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GATE_IMG0(CLK_IMG_GALS, "img_gals",
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"img1_ck"/* parent */, 31),
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/* IMG1 */
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GATE_IMG1(CLK_IMG_FDVT, "img_fdvt",
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"ipe_ck"/* parent */, 0),
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GATE_IMG1(CLK_IMG_ME, "img_me",
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"ipe_ck"/* parent */, 1),
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GATE_IMG1(CLK_IMG_MMG, "img_mmg",
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"ipe_ck"/* parent */, 2),
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GATE_IMG1(CLK_IMG_LARB12, "img_larb12",
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"ipe_ck"/* parent */, 3),
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};
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static const struct mtk_clk_desc img_mcd = {
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.clks = img_clks,
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.num_clks = CLK_IMG_NR_CLK,
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};
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static const struct mtk_gate_regs traw_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_TRAW_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &traw_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate traw_dip1_clks[] = {
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GATE_TRAW_DIP1(CLK_TRAW_DIP1_LARB28, "traw_dip1_larb28",
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"img1_ck"/* parent */, 0),
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GATE_TRAW_DIP1(CLK_TRAW_DIP1_TRAW, "traw_dip1_traw",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc traw_dip1_mcd = {
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.clks = traw_dip1_clks,
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.num_clks = CLK_TRAW_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs wpe1_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_WPE1_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &wpe1_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate wpe1_dip1_clks[] = {
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GATE_WPE1_DIP1(CLK_WPE1_DIP1_LARB11, "wpe1_dip1_larb11",
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"img1_ck"/* parent */, 0),
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GATE_WPE1_DIP1(CLK_WPE1_DIP1_WPE, "wpe1_dip1_wpe",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc wpe1_dip1_mcd = {
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.clks = wpe1_dip1_clks,
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.num_clks = CLK_WPE1_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs wpe2_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_WPE2_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &wpe2_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate wpe2_dip1_clks[] = {
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GATE_WPE2_DIP1(CLK_WPE2_DIP1_LARB11, "wpe2_dip1_larb11",
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"img1_ck"/* parent */, 0),
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GATE_WPE2_DIP1(CLK_WPE2_DIP1_WPE, "wpe2_dip1_wpe",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc wpe2_dip1_mcd = {
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.clks = wpe2_dip1_clks,
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.num_clks = CLK_WPE2_DIP1_NR_CLK,
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};
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static const struct mtk_gate_regs wpe3_dip1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_WPE3_DIP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &wpe3_dip1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate wpe3_dip1_clks[] = {
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GATE_WPE3_DIP1(CLK_WPE3_DIP1_LARB11, "wpe3_dip1_larb11",
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"img1_ck"/* parent */, 0),
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GATE_WPE3_DIP1(CLK_WPE3_DIP1_WPE, "wpe3_dip1_wpe",
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"img1_ck"/* parent */, 1),
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};
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static const struct mtk_clk_desc wpe3_dip1_mcd = {
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.clks = wpe3_dip1_clks,
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.num_clks = CLK_WPE3_DIP1_NR_CLK,
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};
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static const struct of_device_id of_match_clk_mt6886_img[] = {
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{
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.compatible = "mediatek,mt6886-dip_nr1_dip1",
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.data = &dip_nr1_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-dip_nr2_dip1",
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.data = &dip_nr2_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-dip_top_dip1",
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.data = &dip_top_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-imgsys_main",
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.data = &img_mcd,
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}, {
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.compatible = "mediatek,mt6886-traw_dip1",
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.data = &traw_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-wpe1_dip1",
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.data = &wpe1_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-wpe2_dip1",
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.data = &wpe2_dip1_mcd,
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}, {
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.compatible = "mediatek,mt6886-wpe3_dip1",
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.data = &wpe3_dip1_mcd,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6886_img_grp_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init begin\n", __func__, pdev->name);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init end\n", __func__, pdev->name);
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#endif
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return r;
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}
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static struct platform_driver clk_mt6886_img_drv = {
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.probe = clk_mt6886_img_grp_probe,
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.driver = {
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.name = "clk-mt6886-img",
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.of_match_table = of_match_clk_mt6886_img,
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},
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};
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module_platform_driver(clk_mt6886_img_drv);
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MODULE_LICENSE("GPL");
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