kernel-brax3-ubuntu-touch/tools/perf/util/cacheline.h
erascape f319b992b1 kernel-5.15: Initial import brax3 UT kernel
* halium configs enabled

Signed-off-by: erascape <erascape@proton.me>
2025-09-23 15:17:10 +00:00

21 lines
448 B
C

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef PERF_CACHELINE_H
#define PERF_CACHELINE_H
#include <linux/compiler.h>
int __pure cacheline_size(void);
static inline u64 cl_address(u64 address)
{
/* return the cacheline of the address */
return (address & ~(cacheline_size() - 1));
}
static inline u64 cl_offset(u64 address)
{
/* return the cacheline of the address */
return (address & (cacheline_size() - 1));
}
#endif // PERF_CACHELINE_H